US20070176259A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20070176259A1 US20070176259A1 US11/699,336 US69933607A US2007176259A1 US 20070176259 A1 US20070176259 A1 US 20070176259A1 US 69933607 A US69933607 A US 69933607A US 2007176259 A1 US2007176259 A1 US 2007176259A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000003990 capacitor Substances 0.000 claims description 50
- 238000009792 diffusion process Methods 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 238000000034 method Methods 0.000 description 19
- 230000008569 process Effects 0.000 description 18
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 239000010949 copper Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 11
- 230000003071 parasitic effect Effects 0.000 description 11
- 229910052721 tungsten Inorganic materials 0.000 description 11
- 239000010937 tungsten Substances 0.000 description 11
- -1 tungsten nitride Chemical class 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 230000004907 flux Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 230000002265 prevention Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device.
- capacitor elements are critical components for analog circuits. While a capacitor element has been conventionally configured to have a polysilicon layer or an impurity diffusion layer employed as an electrode, a type of a capacitor element so called metal-insulator-metal (MIM) capacitor newly attracts attention in recent years.
- MIM capacitor is a capacitor element, which is configured by providing an insulating film sandwiched between electrodes that are composed of a metal, and draws much attention since the MIM capacitor is capable of providing an improved frequency characteristics.
- Cu is employed for an interconnect material
- Cu is also often employed for an electrode of a MIM capacitor.
- FIG. 18 illustrates a plan view of a MIM capacitor disclosed in Japanese Patent Laid-Open No. 2001-237,375.
- FIG. 19 is a cross-sectional view along line A-A′ of FIG. 18 .
- a lattice-shaped trench is formed, and the interior of this trench is filled with a metallic film 212 composed of a metallic material having lower resistance (for example, Cu).
- the metallic film 212 filling the interior of the trench in the semiconductor substrate 211 serves as a first electrode of the MIM capacitor. While the layout of the first electrode in the MIM capacitor is designed to be lattice-shaped, such layout is for solving the issue of the dishing in the damascene process.
- a silicon nitride (SiN) film 213 is formed on the semiconductor substrate 211 except a region to be provided with a capacitor of the MIM capacitor.
- the region to be provided with a capacitor of the MIM capacitor forms a groove surrounded by the walls of the silicon nitride film 213 .
- a tungsten nitride (WN) film 214 is formed in the region to be provided with a capacitor of the MIM capacitor.
- the tungsten nitride film 214 functions as a diffusion barrier film for the metallic film 212 , and also functions as increasing the capacitor area by being disposed above the lattice-shaped first electrode.
- a capacitor insulating film (for example, tantalum oxide (Ta 2 O 5 ) film) 215 is formed on the tungsten nitride film 214 .
- a tungsten nitride (WN) film 216 is formed on the capacitor insulating film 215 .
- the tungsten nitride film 216 functions as a diffusion barrier film for a metallic material (for example, Cu) serving as a second electrode of the MIM capacitor as described later and also functions as increasing the capacitor area by being disposed under the lattice-shaped second electrode.
- a silicon nitride (SiN) film 217 is formed on the tungsten nitride film 216 .
- the silicon nitride film 217 functions as an etch stop film in the etch process (i.e., in the process for forming trench), together with the silicon nitride film 213 .
- a silicon oxide (SiO 2 ) film 218 is formed on the silicon nitride films 213 and 217 , and a silicon nitride film 219 is formed on the silicon oxide film 218 .
- the silicon nitride film 219 functions as an etch stop film in the process for forming the trench in the dual damascene process.
- a silicon oxide (SiO 2 ) film 220 is formed on the silicon nitride film 219 , and a silicon nitride film 221 is formed on the silicon oxide film 220 .
- the silicon nitride film 221 functions as an etch stop film in the CMP process.
- a lattice-shaped trench, or a trench for an interconnect or a pad, for example, is formed within the silicon oxide film 220 (portion thereof above the silicon nitride film 219 ).
- trenches via holes that reach to the metallic film 212 or the tungsten nitride film 216 are formed in the silicon oxide film 218 and the silicon nitride film 213 .
- the interior of these trenches are filled with metallic films 222 A and 222 B, which are composed of a metallic material having lower resistance and larger diffusion constant (for example, Cu).
- the metallic film 222 A filling the interior of the trench serves as a second electrode of the MIM capacitor.
- the tungsten nitride film 214 is formed to be flat-shaped in the region to be provided with capacitors.
- the tungsten nitride film 216 is formed to be flat-shaped on the capacitor insulating film 215
- the second electrode of the MIM capacitor composed of the metallic film 222 A is formed to be lattice-shaped.
- the tungsten nitride films 214 are 216 are formed under and above the capacitor insulating film 215 , respectively, the tungsten nitride films 214 and 216 substantially constitutes electrodes of the MIM capacitor.
- the operation for forming the metallic films 212 and 222 A to be lattice-shaped and the operation for forming the tungsten nitride films 214 and 216 to be flat-shaped are required to form the electrodes of the MIM capacitor, leading to a problem of an increased number of the process operations and thus an increased manufacturing cost.
- a semiconductor device comprising: a first electrode provided on a semiconductor substrate; a capacitive film, provided on the first electrode so as to be in contact with the first electrode; a second electrode, provided on the capacitive film so as to be in contact with the capacitive film, the second electrode, the first electrode and the capacitive film constituting a capacitor element; a first opening portion, provided in the first electrode and extending through the first electrode; and a second opening portion, provided in the second electrode and extending through the second electrode, wherein an insulating film is embedded within the first opening portion and the second opening portion.
- the semiconductor device is configured that the first and the second opening portions are provided in the first and the second electrodes, respectively.
- the device is also configured that the insulating films are embedded in the opening portions.
- Such configuration provides a structure, in which the above-described insulating films are exposed in portions of the surfaces of the first and the second electrodes. Having such configuration, a generation of a dishing can be inhibited in such process for manufacturing the semiconductor devices.
- first and the second opening portions extend through the first and the second electrodes, respectively. More specifically, the first and the second opening portions are provided over the whole of the first and the second electrodes along a vertical direction (direction to be normal to the substrate surface of the semiconductor substrate), respectively. Consequently, unlikely as the semiconductor device described in the above-described Japanese Patent Laid-Open No. 2001-237,375, an increase of a manufacturing cost can be inhibited.
- a semiconductor device which is capable of providing a solution for the issue of dishing, can be achieved while inhibiting an increase of the manufacturing cost.
- FIG. 1 is a cross-sectional view, illustrating first embodiment of a semiconductor device according to the present invention
- FIG. 2 is a plan view, illustrating the semiconductor device of FIG. 1 ;
- FIG. 3 is a graph, useful in describing an advantageous effect of the semiconductor device of FIG. 1 ;
- FIG. 4 is a cross-sectional view of the semiconductor device, useful in describing an advantageous effect of the semiconductor device of FIG. 1 ;
- FIG. 5 is a cross-sectional view of the semiconductor device, useful in describing an advantageous effect of the semiconductor device of FIG. 1 ;
- FIG. 6 is a plan view of the semiconductor device, useful in describing an advantageous effect of the semiconductor device of FIG. 1 ;
- FIG. 7 is a cross-sectional view of the semiconductor device, useful in describing an advantageous effect of the semiconductor device of FIG. 1 ;
- FIG. 8 is a graph, useful in describing an advantageous effect of the semiconductor device of FIG. 1 ;
- FIG. 9 is a cross-sectional view, illustrating second embodiment of a semiconductor device according to the present invention.
- FIG. 10 is a cross-sectional view, illustrating third embodiment of a semiconductor device according to the present invention.
- FIG. 11 is a cross-sectional view, illustrating a modified embodiment of a semiconductor device according to an embodiment
- FIG. 12 is a plan view of the semiconductor device of FIG. 11 ;
- FIG. 13 is a cross-sectional view, illustrating other modified embodiment of a semiconductor device according to an embodiment
- FIG. 14 is a plan view of the semiconductor device of FIG. 13 ;
- FIG. 15 is a plan view, illustrating other modified embodiment of a semiconductor device according to an embodiment
- FIG. 16 is a plan view, illustrating other modified embodiment of a semiconductor device according to an embodiment
- FIG. 17 is a plan view, illustrating other modified embodiment of a semiconductor device according to an embodiment
- FIG. 18 is a plan view, illustrating a conventional semiconductor device.
- FIG. 19 is a plan view of the semiconductor device of FIG. 18 .
- FIG. 1 is a cross-sectional view, illustrating first embodiment of a semiconductor device according to the present invention.
- FIG. 2 is a plan view, illustrating the semiconductor device of FIG. 1 .
- the cross section along line A-A′ in FIG. 2 corresponds to the cross-sectional view of FIG. 1 .
- a semiconductor device 1 includes:
- a lower electrode 102 (first electrode) provided on a semiconductor substrate 101 ;
- an insulating film 105 (capacitive film), provided on the lower electrode 102 so as to be in contact with the lower electrode 102 ;
- an upper electrode 103 (second electrode), provided on the insulating film 105 so as to be in contact with the insulating film 105 ;
- a opening portion 121 (first opening portion), provided in the lower electrode 102 and extending through the lower electrode 102 ;
- a opening portion 122 (second opening portion), provided in the upper electrode 103 and extending through the upper electrode 103 .
- the semiconductor substrate 101 may be, for example, a p-type silicon substrate.
- An insulating film 104 , an insulating film 123 , an insulating film 105 and an insulating film 124 are sequentially deposited on the semiconductor substrate 101 .
- a silicon dioxide (SiO 2 ) film may be, for example, employed for these insulating films 104 , 105 , 123 and 124 .
- the lower electrode 102 and the upper electrode 103 are formed in the insulating film 123 and in the insulating film 124 , respectively.
- the lower electrode 102 and the upper electrode 103 are formed as metallic films such as Cu film or the like.
- the lower electrode 102 and the upper electrode 103 may be formed via, for example, a damascene process. It is configured that the insulating film 123 is embedded in the opening portion 121 that is provided in the lower electrode 102 . Similarly, it is configured that the insulating film 124 is embedded in the opening portion 122 that is provided in the upper electrode 103 .
- the lower electrode 102 and the upper electrode 103 are flat plate-shaped, which are in a mutually parallel relationship.
- Such capacitor element 106 is a MIM capacitor.
- the opening portion 121 and the opening portion 122 are slit-shaped in plan view.
- the opening portion 121 is identical to the opening portion 122 , in terms of geometry, dimension and position. More specifically, an orthogonal projection of the opening portion 121 to a plane that is parallel with the substrate surface of the semiconductor substrate 101 is identical to an orthogonal projection of the opening portion 122 to the above-described plane.
- a width S 1 of the opening portion 121 is equal to or shorter than a thickness T 1 of the lower electrode 102 .
- a width S 2 of the opening portion 122 is equal to or shorter than a thickness T 2 of the upper electrode 103 .
- S 1 equal to S 2 .
- a width of the opening portion may be defined as a length thereof along a direction perpendicular to a longitudinal direction of the slit in plan view (see FIG. 2 ).
- the opening portion 121 and the opening portion 122 are provided in the lower electrode 102 and in the upper electrode 103 , respectively.
- the insulating film 123 and the insulating film 124 are embedded in the opening portion 121 and the opening portion 122 , respectively. Therefore, the insulating film 123 and the insulating film 124 are exposed in portions of the surfaces of the lower electrode 102 and the upper electrode 103 , respectively. Having such configuration, a generation of a dishing can be inhibited in the process for manufacturing the semiconductor device 1 .
- the opening portion 121 and the opening portion 122 extend through the lower electrode 102 and the upper electrode 103 , respectively. More specifically, the opening portion 121 and the opening portion 122 are provided over the whole of the lower electrode 102 and the upper electrode 103 along a vertical direction (direction to be perpendicular to the substrate surface of the semiconductor substrate 101 ), respectively. Consequently, unlikely as the semiconductor device described in the above-described Japanese Patent Laid-Open No. 2001-237,375, an increase of a manufacturing cost can be inhibited. Therefore, the semiconductor device 1 , which is capable of providing a solution for the issue of dishing, can be achieved while inhibiting an increase of the manufacturing cost.
- FIG. 3 is a graph, showing a relationship of a dishing phenomenon with a size of an electrode. Abscissa represents a size of an electrode [ ⁇ m], and ordinate represents a level of a dishing.
- Lines C 1 to C 5 correspond to respective cases described as follows. The slits described here correspond to the above-described opening portions 121 and 122 .
- line L 1 indicates the upper limit of a level of a dishing phenomenon tolerated in the manufacturing process. More specifically, it is meant that a non-defective semiconductor device can not be obtained if a dishing of a level beyond the line L 1 is created.
- the configuration including slits provides moderating the level of the dishing phenomenon, thereby increasing the size of the electrode formed in the process.
- the designed size of the electrode can be increased up to 24 ⁇ m.
- FIG. 4 shows a schematic diagrams, illustrating mock-ups of electric flux line generated from the lower electrode 102 of the capacitor element 106 and electric flux line generated from the upper electrode 103 , in the case that the width of the opening portion 121 and the width of the opening portion 122 are larger than the thickness of the lower electrode 102 and the thickness of the upper electrode 103 , respectively.
- Arrows 107 and arrows 108 represent electric flux line generated from side surfaces of the lower electrode 102 and from side surfaces of the upper electrode 103 , respectively. As can be seen from FIG.
- the configuration is electrically equivalent to a configuration, in which a plurality of isolated smaller electrodes are arranged.
- a geometric variation of the formed electrodes is increased, providing an increased variation in capacitance, leading to deteriorating characteristics of analog circuits.
- FIG. 5 shows a schematic diagrams, illustrating mock-ups of electric flux line generated from the lower electrode 102 of the capacitor element 106 and electric flux line generated from the upper electrode 103 , in the case that the width of the opening portion 121 and the width of the opening portion 122 are equal to or smaller than the thickness of the lower electrode 102 and the thickness of the upper electrode 103 , respectively.
- FIG. 5 smaller amount of electric flux line leak out from the slits (opening portions 121 and 122 ) in this case, and thus it is appeared that the configuration is electrically equivalent to a configuration, in which no slit is included therein, and one larger electrode is included.
- the size of electrodes is larger, a geometric variation of the formed electrodes is decreased, providing a reduced variation in capacitance, thereby leading to maintaining better characteristics of analog circuits.
- FIG. 6 shows a layout pattern, which is employed for obtaining a relationship of obtained capacitance values of the capacitor element 106 with slit widths S (corresponding to the above-described widths S 1 and S 2 ) via a three-dimensional capacitance simulator.
- FIG. 7 is a graph, showing results of the capacitance values obtained via the three-dimensional capacitance simulator. Abscissa represents a width of slit [ ⁇ m] and ordinate represents a capacitance value. However, value of ordinate represents a dimensionless capacitance value obtained by a ratio of the obtained capacitance value to a capacitance value without slit (i.e., ratio of [measured capacitance value]/[capacitance value without slit]).
- Fixed W 1 and H 1 which represent outer dimension of the lower electrode 102 shown in FIG. 6 and fixed W 2 and H 2 , which represent outer dimension of the upper electrode 103 , are employed in the simulation, and the slit width S is changed.
- FIG. 8 a graph showing a relationship of a parasitic capacitance caused in the upper electrode 103 of the capacitor element 106 over the semiconductor substrate 101 with the slit width S in the layout pattern of FIG. 6 , obtained by employing the three-dimensional capacitance simulator.
- Abscissa represents a width of slit [ ⁇ m]
- ordinate represents a parasitic capacitance.
- value of ordinate represents a dimensionless parasitic capacitance value obtained by a ratio of the obtained parasitic capacitance value to a parasitic capacitance value without slit (i.e., ratio of [measured parasitic capacitance value]/[parasitic capacitance value without slit]).
- Steeper slope of the curve representing the parasitic capacitance value (cf.
- the MIM capacitance is configured that the lower electrode 102 and the upper electrode 103 of the capacitor element 106 are provided with the opening portions (slit in this embodiment) having a width smaller than the thickness thereof, so that a prevention of an influence by a dishing and a reduction in variation of capacitance value resulting from geometric variation can be achieved, thereby providing the MIM capacitance, which is suitable for analog circuits.
- the opening portion 121 is identical to the opening portion 122 , in terms of geometry, dimension and position. This configuration further facilitates the manufacture of the semiconductor device 1 .
- FIG. 9 is a cross-sectional view, illustrating second embodiment of a semiconductor device according to the present invention.
- a semiconductor device 2 includes:
- a lower electrode 132 (first electrode) provided on a semiconductor substrate 101 ;
- an insulating film 105 (capacitive film), provided on the lower electrode 132 so as to be in contact with the lower electrode 132 ;
- an upper electrode 134 (second electrode), provided on the insulating film 105 so as to be in contact with the insulating film 105 ;
- a opening portion 121 (first opening portion), provided in the lower electrode 132 and extending through the lower electrode 132 ;
- a opening portion 122 (second opening portion), provided in the upper electrode 134 and extending through the upper electrode 134 .
- the lower electrode 132 is composed of a metallic film 131 and diffusion barrier films 109 and 110 covering a surface of the metallic film 131 . More specifically, an upper surface and a lower surface of the metallic film 131 are covered with the diffusion barrier film 110 and the diffusion barrier film 109 , respectively. The opening portion 121 extends through both of the metallic film 131 and the diffusion barrier films 109 and 110 .
- the upper electrode 134 is composed of a metallic film 133 and diffusion barrier films 111 and 112 covering a surface of the metallic film 133 . More specifically, an upper surface and a lower surface of the metallic film 133 are covered with the diffusion barrier film 112 and the diffusion barrier film 111 , respectively.
- the opening portion 122 extends through both of the metallic film 133 and the diffusion barrier films 111 and 112 .
- the metallic films 131 and 133 are, for example, Cu films.
- the diffusion barrier films 109 , 110 , 111 and 112 are, for example, tungsten nitride films.
- the lower electrode 132 , the upper electrode 134 and the insulating film 105 constitute a capacitor element 113 .
- the rest of elements in the configuration of the semiconductor device 2 is similar to that of the semiconductor device 1 .
- the semiconductor device 2 having such configuration is capable of providing advantageous effects described below, in addition to the advantageous effects described above in reference to the semiconductor device 1 .
- the metallic film 131 is covered with the diffusion barrier films 109 and 110
- the metallic film 133 is covered with the diffusion barrier films 111 and 112 .
- This configuration provides an effective prevention of the metallic material composing the metallic film 131 and the metallic film 133 from diffusing therein.
- the opening portion 121 extended through the diffusion barrier films 109 and 110 , in addition to extending through the metallic film 131 .
- the opening portion 122 extended through the diffusion barrier films 111 and 112 , in addition to extending through the metallic film 133 .
- the diffusion barrier films 109 and 110 and the diffusion barrier films 111 and 112 are provided with the slits (opening portion 121 and 122 ) having geometry same as the metallic film 131 and the metallic film 133 , respectively. Consequently, only a smaller number of additional operations for forming the slit is required, such that an increase of the manufacturing cost can be avoided.
- a capacitance value is reduced, as compared with a case of employing an electrode provided with no opening portion.
- a decrease of the capacitance caused by providing the opening portion can be reduced by having the width of the opening portion to be equal to or smaller than the thickness of the electrode.
- FIG. 10 is a cross-sectional view, illustrating third embodiment of a semiconductor device according to the present invention.
- a semiconductor device 3 includes:
- an insulating film 105 provided on the lower electrode 102 so as to be in contact with the lower electrode 102 ;
- an upper electrode 103 provided on the insulating film 105 so as to be in contact with the insulating film 105 ;
- a opening portion 121 provided in the lower electrode 102 and extending through the lower electrode 102 ;
- a opening portion 122 provided in the upper electrode 103 and extending through the upper electrode 103 .
- the semiconductor device 3 includes:
- an insulating film 114 (second capacitive film), provided on the upper electrode 103 so as to be in contact with the upper electrode 103 ;
- an electrode 115 (third electrode), provided on the insulating film 114 so as to be in contact with the insulating film 114 ;
- a opening portion 141 (third opening portion), provided in the electrode 115 and extending through the electrode 115 .
- An insulating film 104 , an insulating film 123 , the insulating film 105 , an insulating film 124 , the insulating film 114 and the insulating film 142 are sequentially deposited on the semiconductor substrate 101 .
- a silicon dioxide (SiO 2 ) film may be, for example, employed for the insulating films 114 and 142 .
- the electrode 115 is formed in the insulating film 142 .
- the electrode 115 is formed as a metallic film such as Cu film or the like.
- the electrode 115 may be formed via, for example, a damascene process.
- the insulating film 142 is embedded in the opening portion 141 that is provided in the electrode 115 .
- the electrode 115 is flat plate-shaped, which is in parallel with the lower electrode 102 and the upper electrode 103 .
- the electrode 115 together with the upper electrode 103 and the insulating film 114 , constitutes a MIM capacitor.
- the MIM capacitance composed of the lower electrode 102 , the upper electrode 103 and the insulating film 105 is coupled with the MIM capacitance composed of the electrode 115 , the upper electrode 103 and the insulating film 114 in parallel.
- the electrode 115 also functions as a lower electrode, similarly as the lower electrode 102 .
- the opening portion 141 is slit-shaped in plan view, similarly as the opening portion 121 and the opening portion 122 .
- the opening portion 121 , the opening portion 122 and the opening portion 141 are identical in terms of geometry, dimension and position.
- a width S 3 of the opening portion 141 is equal to or shorter than a thickness T 3 of the electrode 115 .
- the rest of elements in the configuration of the semiconductor device 3 is similar to that of the semiconductor device 1 .
- the semiconductor device 3 having such configuration is capable of providing advantageous effects described below, in addition to the advantageous effects described above in reference to the semiconductor device 1 .
- both of the lower electrode 102 and the electrode 115 function as a lower electrode.
- This configuration provides a configuration, in which the MIM capacitance between the lower electrode 102 and the upper electrode 103 is coupled to the MIM capacitance between the upper electrode 103 and the electrode 115 in parallel, thereby achieving an increased capacitance value per unit area.
- the MIM capacitance which is suitable in providing a prevention of an influence by a dishing and a reduction in variation of capacitance value resulting from geometric variation, can be achieved.
- FIG. 11 the opening portion 121 and the opening portion 122 may be provided in different positions in plan view.
- a plan view of the semiconductor device of FIG. 11 is shown in FIG. 12 .
- a cross section along line A-A′ of FIG. 12 corresponds to the cross sectional view of FIG. 11 .
- the opening portion 121 may have a dimension in plan view that is different from a dimension of the opening portion 122 .
- a plan view of the semiconductor device of FIG. 13 is shown in FIG. 14 .
- a cross section along line A-A′ of FIG. 14 corresponds to the cross sectional view of FIG. 13 .
- the lower electrode 102 and the upper electrode 103 may be ladder-shaped in plan view.
- the opening portion 121 and the opening portion 122 may be annular-shaped in plan view.
- a plurality of opening portions 121 and a plurality of opening portions 122 may be provided, and are arranged to form a lattice pattern in plan view.
- a plurality of opening portions 121 (opening portions 122 ) are arranged to form a diagonal lattice pattern.
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Abstract
A problem of an increased manufacturing cost is caused in conventional semiconductor devices. A semiconductor device 1 includes: a lower electrode 102 provided on a semiconductor substrate 101; an insulating film 105, provided on the lower electrode 102 so as to be in contact with the lower electrode 102; an upper electrode 103, provided on the insulating film 105 so as to be in contact with the insulating film 105; an opening portion 121, provided in the lower electrode 102 and extending through the lower electrode 102; and an opening portion 122, provided in the upper electrode 103 and extending through the upper electrode 103. The insulating film 123 is embedded in the opening portion 121 that is provided in the lower electrode 102. Similarly, the insulating film 124 is embedded in the opening portion 122 that is provided in the upper electrode 103.
Description
- This application is based on Japanese patent application No. 2006-22,842, the content of which is incorporated hereinto by reference.
- 1. Technical Field
- The present invention relates to a semiconductor device.
- 2. Related Art
- In recent years, developments in large scale integrated circuits (LSI) having analog circuits (analog devices) and digital circuits (digital devices) integrated in one chip is progressed. Among these technical trends, miniaturizations of digital devices are progressed year by year, in which a reduced gate length in a metal oxide semiconductor (MOS) transistor of on the order of about 0.1 μm was achieved, and in such situation, copper (Cu), which is a low resistivity material, has widely been employed for an interconnect material, for the purpose of providing a reduced interconnect resistance, and a damascene process has been employed for forming the interconnects.
- Meanwhile, capacitor elements are critical components for analog circuits. While a capacitor element has been conventionally configured to have a polysilicon layer or an impurity diffusion layer employed as an electrode, a type of a capacitor element so called metal-insulator-metal (MIM) capacitor newly attracts attention in recent years. The MIM capacitor is a capacitor element, which is configured by providing an insulating film sandwiched between electrodes that are composed of a metal, and draws much attention since the MIM capacitor is capable of providing an improved frequency characteristics. When Cu is employed for an interconnect material, Cu is also often employed for an electrode of a MIM capacitor.
- Nonetheless, when an electrode of a MIM capacitor is formed via a damascene process employing Cu for a material of the process, a problem of a dishing (phenomenon of causing positional variation in polishing-ability in a planarizing operation of a Cu interconnect via a chemical mechanical polishing (CMP) process, and more specifically a center of an interconnect is more considerably polished as compared with both ends of the interconnect, leading to a locally thinner interconnect film in the center) is caused, so that a process for forming the MIM capacitor without causing an issue of the dishing is expected. In particular, since degree of integration in a transistor is increasingly improved as levels of the miniaturization is increased, a critical issue is how the capacitor elements in an analog circuit would be formed to have higher capacity without disturbing higher integration level of devices. In addition, since characteristics of the integrated analog circuits are increasingly improved, a formation of capacitor elements with less variation of capacities is a critical problem for the purpose of providing improved characteristics of analog circuits.
- A conventional structure for preventing such issue of dishing caused in the process for forming the electrode in the MIM capacitor is described in Japanese Patent Laid-Open No. 2001-237,375.
FIG. 18 illustrates a plan view of a MIM capacitor disclosed in Japanese Patent Laid-Open No. 2001-237,375.FIG. 19 is a cross-sectional view along line A-A′ ofFIG. 18 . In thesemiconductor substrate 211, a lattice-shaped trench is formed, and the interior of this trench is filled with ametallic film 212 composed of a metallic material having lower resistance (for example, Cu). Themetallic film 212 filling the interior of the trench in thesemiconductor substrate 211 serves as a first electrode of the MIM capacitor. While the layout of the first electrode in the MIM capacitor is designed to be lattice-shaped, such layout is for solving the issue of the dishing in the damascene process. - A silicon nitride (SiN)
film 213 is formed on thesemiconductor substrate 211 except a region to be provided with a capacitor of the MIM capacitor. The region to be provided with a capacitor of the MIM capacitor forms a groove surrounded by the walls of thesilicon nitride film 213. Then, a tungsten nitride (WN)film 214 is formed in the region to be provided with a capacitor of the MIM capacitor. Thetungsten nitride film 214 functions as a diffusion barrier film for themetallic film 212, and also functions as increasing the capacitor area by being disposed above the lattice-shaped first electrode. - A capacitor insulating film (for example, tantalum oxide (Ta2O5) film) 215 is formed on the
tungsten nitride film 214. A tungsten nitride (WN) film 216 is formed on thecapacitor insulating film 215. The tungsten nitride film 216 functions as a diffusion barrier film for a metallic material (for example, Cu) serving as a second electrode of the MIM capacitor as described later and also functions as increasing the capacitor area by being disposed under the lattice-shaped second electrode. - A silicon nitride (SiN)
film 217 is formed on the tungsten nitride film 216. Thesilicon nitride film 217 functions as an etch stop film in the etch process (i.e., in the process for forming trench), together with thesilicon nitride film 213. - A silicon oxide (SiO2)
film 218 is formed on thesilicon nitride films silicon nitride film 219 is formed on thesilicon oxide film 218. Thesilicon nitride film 219 functions as an etch stop film in the process for forming the trench in the dual damascene process. A silicon oxide (SiO2)film 220 is formed on thesilicon nitride film 219, and asilicon nitride film 221 is formed on thesilicon oxide film 220. Thesilicon nitride film 221 functions as an etch stop film in the CMP process. - A lattice-shaped trench, or a trench for an interconnect or a pad, for example, is formed within the silicon oxide film 220 (portion thereof above the silicon nitride film 219). In addition, trenches (via holes) that reach to the
metallic film 212 or the tungsten nitride film 216 are formed in thesilicon oxide film 218 and thesilicon nitride film 213. The interior of these trenches are filled withmetallic films metallic film 222A filling the interior of the trench serves as a second electrode of the MIM capacitor. - However, an issue of increasing a manufacturing cost described as follows may be caused in such technique. More specifically, while the first electrode of the MIM capacitor composed of the
metallic film 212 is formed to be lattice-shaped, thetungsten nitride film 214 is formed to be flat-shaped in the region to be provided with capacitors. In addition, while the tungsten nitride film 216 is formed to be flat-shaped on the capacitorinsulating film 215, the second electrode of the MIM capacitor composed of themetallic film 222A is formed to be lattice-shaped. - Since the
tungsten nitride films 214 are 216 are formed under and above thecapacitor insulating film 215, respectively, thetungsten nitride films 214 and 216 substantially constitutes electrodes of the MIM capacitor. As described above, the operation for forming themetallic films tungsten nitride films 214 and 216 to be flat-shaped are required to form the electrodes of the MIM capacitor, leading to a problem of an increased number of the process operations and thus an increased manufacturing cost. - According to one aspect of the present invention, there is provided a semiconductor device, comprising: a first electrode provided on a semiconductor substrate; a capacitive film, provided on the first electrode so as to be in contact with the first electrode; a second electrode, provided on the capacitive film so as to be in contact with the capacitive film, the second electrode, the first electrode and the capacitive film constituting a capacitor element; a first opening portion, provided in the first electrode and extending through the first electrode; and a second opening portion, provided in the second electrode and extending through the second electrode, wherein an insulating film is embedded within the first opening portion and the second opening portion.
- The semiconductor device is configured that the first and the second opening portions are provided in the first and the second electrodes, respectively. The device is also configured that the insulating films are embedded in the opening portions. Such configuration provides a structure, in which the above-described insulating films are exposed in portions of the surfaces of the first and the second electrodes. Having such configuration, a generation of a dishing can be inhibited in such process for manufacturing the semiconductor devices.
- Further, the first and the second opening portions extend through the first and the second electrodes, respectively. More specifically, the first and the second opening portions are provided over the whole of the first and the second electrodes along a vertical direction (direction to be normal to the substrate surface of the semiconductor substrate), respectively. Consequently, unlikely as the semiconductor device described in the above-described Japanese Patent Laid-Open No. 2001-237,375, an increase of a manufacturing cost can be inhibited.
- According to the present invention, a semiconductor device, which is capable of providing a solution for the issue of dishing, can be achieved while inhibiting an increase of the manufacturing cost.
- The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a cross-sectional view, illustrating first embodiment of a semiconductor device according to the present invention; -
FIG. 2 is a plan view, illustrating the semiconductor device ofFIG. 1 ; -
FIG. 3 is a graph, useful in describing an advantageous effect of the semiconductor device ofFIG. 1 ; -
FIG. 4 is a cross-sectional view of the semiconductor device, useful in describing an advantageous effect of the semiconductor device ofFIG. 1 ; -
FIG. 5 is a cross-sectional view of the semiconductor device, useful in describing an advantageous effect of the semiconductor device ofFIG. 1 ; -
FIG. 6 is a plan view of the semiconductor device, useful in describing an advantageous effect of the semiconductor device ofFIG. 1 ; -
FIG. 7 is a cross-sectional view of the semiconductor device, useful in describing an advantageous effect of the semiconductor device ofFIG. 1 ; -
FIG. 8 is a graph, useful in describing an advantageous effect of the semiconductor device ofFIG. 1 ; -
FIG. 9 is a cross-sectional view, illustrating second embodiment of a semiconductor device according to the present invention; -
FIG. 10 is a cross-sectional view, illustrating third embodiment of a semiconductor device according to the present invention; -
FIG. 11 is a cross-sectional view, illustrating a modified embodiment of a semiconductor device according to an embodiment; -
FIG. 12 is a plan view of the semiconductor device ofFIG. 11 ; -
FIG. 13 is a cross-sectional view, illustrating other modified embodiment of a semiconductor device according to an embodiment; -
FIG. 14 is a plan view of the semiconductor device ofFIG. 13 ; -
FIG. 15 is a plan view, illustrating other modified embodiment of a semiconductor device according to an embodiment; -
FIG. 16 is a plan view, illustrating other modified embodiment of a semiconductor device according to an embodiment; -
FIG. 17 is a plan view, illustrating other modified embodiment of a semiconductor device according to an embodiment; -
FIG. 18 is a plan view, illustrating a conventional semiconductor device; and -
FIG. 19 is a plan view of the semiconductor device ofFIG. 18 . - The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed.
- Preferable embodiments according to the present invention will be described as follows in further detail, in reference to the annexed figures. In all figures, an identical numeral is assigned to an element commonly appeared in the figures, and the detailed description thereof will not be repeated.
-
FIG. 1 is a cross-sectional view, illustrating first embodiment of a semiconductor device according to the present invention.FIG. 2 is a plan view, illustrating the semiconductor device ofFIG. 1 . The cross section along line A-A′ inFIG. 2 corresponds to the cross-sectional view ofFIG. 1 . Asemiconductor device 1 includes: - a lower electrode 102 (first electrode) provided on a
semiconductor substrate 101; - an insulating film 105 (capacitive film), provided on the
lower electrode 102 so as to be in contact with thelower electrode 102; - an upper electrode 103 (second electrode), provided on the insulating
film 105 so as to be in contact with the insulatingfilm 105; - a opening portion 121 (first opening portion), provided in the
lower electrode 102 and extending through thelower electrode 102; and - a opening portion 122 (second opening portion), provided in the
upper electrode 103 and extending through theupper electrode 103. - The
semiconductor substrate 101 may be, for example, a p-type silicon substrate. - An insulating
film 104, an insulatingfilm 123, an insulatingfilm 105 and an insulatingfilm 124 are sequentially deposited on thesemiconductor substrate 101. A silicon dioxide (SiO2) film may be, for example, employed for these insulatingfilms lower electrode 102 and theupper electrode 103 are formed in the insulatingfilm 123 and in the insulatingfilm 124, respectively. Thelower electrode 102 and theupper electrode 103 are formed as metallic films such as Cu film or the like. Thelower electrode 102 and theupper electrode 103 may be formed via, for example, a damascene process. It is configured that the insulatingfilm 123 is embedded in theopening portion 121 that is provided in thelower electrode 102. Similarly, it is configured that the insulatingfilm 124 is embedded in theopening portion 122 that is provided in theupper electrode 103. - The
lower electrode 102 and theupper electrode 103 are flat plate-shaped, which are in a mutually parallel relationship. Thelower electrode 102 and theupper electrode 103, together with the insulatingfilm 105 interposing therebetween, constitute acapacitor element 106.Such capacitor element 106 is a MIM capacitor. - As shown in
FIG. 2 , theopening portion 121 and theopening portion 122 are slit-shaped in plan view. In particular in the present embodiment, theopening portion 121 is identical to theopening portion 122, in terms of geometry, dimension and position. More specifically, an orthogonal projection of theopening portion 121 to a plane that is parallel with the substrate surface of thesemiconductor substrate 101 is identical to an orthogonal projection of theopening portion 122 to the above-described plane. - Here, it is preferable that a width S1 of the
opening portion 121 is equal to or shorter than a thickness T1 of thelower electrode 102. Similarly, it is preferable that a width S2 of theopening portion 122 is equal to or shorter than a thickness T2 of theupper electrode 103. In the present embodiment, S1 equal to S2. In addition to above, when the opening portion is slit-shaped, a width of the opening portion may be defined as a length thereof along a direction perpendicular to a longitudinal direction of the slit in plan view (seeFIG. 2 ). - Subsequently, an advantageous effect obtainable by employing the configuration of the
semiconductor device 1 will be described. In thesemiconductor device 1, theopening portion 121 and theopening portion 122 are provided in thelower electrode 102 and in theupper electrode 103, respectively. The insulatingfilm 123 and the insulatingfilm 124 are embedded in theopening portion 121 and theopening portion 122, respectively. Therefore, the insulatingfilm 123 and the insulatingfilm 124 are exposed in portions of the surfaces of thelower electrode 102 and theupper electrode 103, respectively. Having such configuration, a generation of a dishing can be inhibited in the process for manufacturing thesemiconductor device 1. - Further, the
opening portion 121 and theopening portion 122 extend through thelower electrode 102 and theupper electrode 103, respectively. More specifically, theopening portion 121 and theopening portion 122 are provided over the whole of thelower electrode 102 and theupper electrode 103 along a vertical direction (direction to be perpendicular to the substrate surface of the semiconductor substrate 101), respectively. Consequently, unlikely as the semiconductor device described in the above-described Japanese Patent Laid-Open No. 2001-237,375, an increase of a manufacturing cost can be inhibited. Therefore, thesemiconductor device 1, which is capable of providing a solution for the issue of dishing, can be achieved while inhibiting an increase of the manufacturing cost. -
FIG. 3 is a graph, showing a relationship of a dishing phenomenon with a size of an electrode. Abscissa represents a size of an electrode [μm], and ordinate represents a level of a dishing. Lines C1 to C5 correspond to respective cases described as follows. The slits described here correspond to the above-describedopening portions - C1: no slit
- C2: one slit (0.2 μm-wide)
- C3: one slit (0.4 μm-wide)
- C4: two slits (each 0.2 μm-wide)
- C5: two slits (each 0.4 μm-wide)
- As can be seen from
FIG. 3 , larger size of the electrode provides larger level of the dishing phenomenon. Under such circumstances, if the level of the dishing phenomenon exceeds a certain limit (line L1), a height of a step created in the metallic film by the dishing phenomenon is excessively increased, so that processes after the next operation can not be normally conducted, eventually preventing the products from being manufactured as non-defective products. The present exemplary implementation shows that, when no slit is included (see line C1), a size of an electrode can only be increased up to 3 μm, and therefore the capacitance of the formed capacitor is considerably small. On the contrary, it can also be understood that the configuration including slits provides moderating the level of the dishing phenomenon, thereby increasing the size of the electrode formed in the process. For example, when two slits having widths of 0.4 μm is formed, (see line C5), the designed size of the electrode can be increased up to 24 μm. -
FIG. 4 shows a schematic diagrams, illustrating mock-ups of electric flux line generated from thelower electrode 102 of thecapacitor element 106 and electric flux line generated from theupper electrode 103, in the case that the width of theopening portion 121 and the width of theopening portion 122 are larger than the thickness of thelower electrode 102 and the thickness of theupper electrode 103, respectively.Arrows 107 andarrows 108 represent electric flux line generated from side surfaces of thelower electrode 102 and from side surfaces of theupper electrode 103, respectively. As can be seen fromFIG. 4 , larger amount of electric flux line leak out from the slits (openingportions 121 and 122) in this case, and thus it is appeared that the configuration is electrically equivalent to a configuration, in which a plurality of isolated smaller electrodes are arranged. When the size of electrodes is smaller, a geometric variation of the formed electrodes is increased, providing an increased variation in capacitance, leading to deteriorating characteristics of analog circuits. -
FIG. 5 shows a schematic diagrams, illustrating mock-ups of electric flux line generated from thelower electrode 102 of thecapacitor element 106 and electric flux line generated from theupper electrode 103, in the case that the width of theopening portion 121 and the width of theopening portion 122 are equal to or smaller than the thickness of thelower electrode 102 and the thickness of theupper electrode 103, respectively. As can be seen fromFIG. 5 , smaller amount of electric flux line leak out from the slits (openingportions 121 and 122) in this case, and thus it is appeared that the configuration is electrically equivalent to a configuration, in which no slit is included therein, and one larger electrode is included. When the size of electrodes is larger, a geometric variation of the formed electrodes is decreased, providing a reduced variation in capacitance, thereby leading to maintaining better characteristics of analog circuits. -
FIG. 6 shows a layout pattern, which is employed for obtaining a relationship of obtained capacitance values of thecapacitor element 106 with slit widths S (corresponding to the above-described widths S1 and S2) via a three-dimensional capacitance simulator. In addition,FIG. 7 is a graph, showing results of the capacitance values obtained via the three-dimensional capacitance simulator. Abscissa represents a width of slit [μm] and ordinate represents a capacitance value. However, value of ordinate represents a dimensionless capacitance value obtained by a ratio of the obtained capacitance value to a capacitance value without slit (i.e., ratio of [measured capacitance value]/[capacitance value without slit]). Fixed W1 and H1, which represent outer dimension of thelower electrode 102 shown inFIG. 6 and fixed W2 and H2, which represent outer dimension of theupper electrode 103, are employed in the simulation, and the slit width S is changed. - As can be seen from
FIG. 7 , steeper slope of the curve representing the capacitance value (cf. straight line L2) appears when the slit width S is larger than the thickness of the electrode (0.3 μm in this embodiment), and such result is obtained because a decrease in area of the electrode by having wider slit width S just causes a reduction in capacitance value. On the contrary, gentle slope of the curve representing the capacitance value appears when the slit width S is equal to or shorter than the thickness of the electrode, and such result is obtained because a decrease in area of the electrode by having the slit is not much influenced over the capacitance value. In other words, when the slit width S is equal to or shorter than the thickness of the electrode, it can be considered that the electrode can be almost considered as having no slit. -
FIG. 8 a graph showing a relationship of a parasitic capacitance caused in theupper electrode 103 of thecapacitor element 106 over thesemiconductor substrate 101 with the slit width S in the layout pattern ofFIG. 6 , obtained by employing the three-dimensional capacitance simulator. Abscissa represents a width of slit [μm], and ordinate represents a parasitic capacitance. However, value of ordinate represents a dimensionless parasitic capacitance value obtained by a ratio of the obtained parasitic capacitance value to a parasitic capacitance value without slit (i.e., ratio of [measured parasitic capacitance value]/[parasitic capacitance value without slit]). Steeper slope of the curve representing the parasitic capacitance value (cf. straight line L3) appears when the slit width S is larger than the thickness of the electrode, and such result is obtained because a increase in area of the side surface of the electrode by having wider slit width S just influences increase of parasitic capacitance value. On the contrary, gentle slope of the curve representing the parasitic capacitance value appears when the slit width S is equal to or shorter than the thickness of the electrode, and such result is obtained because a increase in area of the side surface of the electrode by having the slit is not much influenced over the parasitic capacitance value. In other words, when the slit width S is equal to or shorter than the thickness of the electrode, it can be considered that the electrode can be almost considered as having no slit. - As described above, the MIM capacitance is configured that the
lower electrode 102 and theupper electrode 103 of thecapacitor element 106 are provided with the opening portions (slit in this embodiment) having a width smaller than the thickness thereof, so that a prevention of an influence by a dishing and a reduction in variation of capacitance value resulting from geometric variation can be achieved, thereby providing the MIM capacitance, which is suitable for analog circuits. - In addition, in the
semiconductor device 1, theopening portion 121 is identical to theopening portion 122, in terms of geometry, dimension and position. This configuration further facilitates the manufacture of thesemiconductor device 1. -
FIG. 9 is a cross-sectional view, illustrating second embodiment of a semiconductor device according to the present invention. Asemiconductor device 2 includes: - a lower electrode 132 (first electrode) provided on a
semiconductor substrate 101; - an insulating film 105 (capacitive film), provided on the
lower electrode 132 so as to be in contact with thelower electrode 132; - an upper electrode 134 (second electrode), provided on the insulating
film 105 so as to be in contact with the insulatingfilm 105; - a opening portion 121 (first opening portion), provided in the
lower electrode 132 and extending through thelower electrode 132; and - a opening portion 122 (second opening portion), provided in the
upper electrode 134 and extending through theupper electrode 134. - The
lower electrode 132 is composed of ametallic film 131 anddiffusion barrier films metallic film 131. More specifically, an upper surface and a lower surface of themetallic film 131 are covered with thediffusion barrier film 110 and thediffusion barrier film 109, respectively. Theopening portion 121 extends through both of themetallic film 131 and thediffusion barrier films upper electrode 134 is composed of ametallic film 133 anddiffusion barrier films metallic film 133. More specifically, an upper surface and a lower surface of themetallic film 133 are covered with thediffusion barrier film 112 and thediffusion barrier film 111, respectively. Theopening portion 122 extends through both of themetallic film 133 and thediffusion barrier films metallic films diffusion barrier films - In the
semiconductor device 2, thelower electrode 132, theupper electrode 134 and the insulatingfilm 105 constitute acapacitor element 113. The rest of elements in the configuration of thesemiconductor device 2 is similar to that of thesemiconductor device 1. - The
semiconductor device 2 having such configuration is capable of providing advantageous effects described below, in addition to the advantageous effects described above in reference to thesemiconductor device 1. In thesemiconductor device 2, themetallic film 131 is covered with thediffusion barrier films metallic film 133 is covered with thediffusion barrier films metallic film 131 and themetallic film 133 from diffusing therein. - Moreover, the
opening portion 121 extended through thediffusion barrier films metallic film 131. Similarly, theopening portion 122 extended through thediffusion barrier films metallic film 133. More specifically, thediffusion barrier films diffusion barrier films portion 121 and 122) having geometry same as themetallic film 131 and themetallic film 133, respectively. Consequently, only a smaller number of additional operations for forming the slit is required, such that an increase of the manufacturing cost can be avoided. - Meanwhile, when the opening portions are formed in both of the metallic film and the diffusion barrier film that constitutes the electrode of the MIM capacitance for avoiding an increase of the manufacturing cost as described above, a capacitance value is reduced, as compared with a case of employing an electrode provided with no opening portion. With regard to the aspect, as described above in reference to
FIG. 7 , a decrease of the capacitance caused by providing the opening portion can be reduced by having the width of the opening portion to be equal to or smaller than the thickness of the electrode. -
FIG. 10 is a cross-sectional view, illustrating third embodiment of a semiconductor device according to the present invention. Asemiconductor device 3 includes: - a
lower electrode 102 provided on asemiconductor substrate 101; - an insulating
film 105, provided on thelower electrode 102 so as to be in contact with thelower electrode 102; - an
upper electrode 103, provided on the insulatingfilm 105 so as to be in contact with the insulatingfilm 105; - a
opening portion 121, provided in thelower electrode 102 and extending through thelower electrode 102; and - a
opening portion 122, provided in theupper electrode 103 and extending through theupper electrode 103. - Further, the
semiconductor device 3 includes: - an insulating film 114 (second capacitive film), provided on the
upper electrode 103 so as to be in contact with theupper electrode 103; - an electrode 115 (third electrode), provided on the insulating
film 114 so as to be in contact with the insulatingfilm 114; and - a opening portion 141 (third opening portion), provided in the
electrode 115 and extending through theelectrode 115. - An insulating
film 104, an insulatingfilm 123, the insulatingfilm 105, an insulatingfilm 124, the insulatingfilm 114 and the insulatingfilm 142 are sequentially deposited on thesemiconductor substrate 101. A silicon dioxide (SiO2) film may be, for example, employed for the insulatingfilms electrode 115 is formed in the insulatingfilm 142. Theelectrode 115 is formed as a metallic film such as Cu film or the like. Theelectrode 115 may be formed via, for example, a damascene process. The insulatingfilm 142 is embedded in theopening portion 141 that is provided in theelectrode 115. - The
electrode 115 is flat plate-shaped, which is in parallel with thelower electrode 102 and theupper electrode 103. Theelectrode 115, together with theupper electrode 103 and the insulatingfilm 114, constitutes a MIM capacitor. In thecapacitor element 116 of thesemiconductor device 3, the MIM capacitance composed of thelower electrode 102, theupper electrode 103 and the insulatingfilm 105 is coupled with the MIM capacitance composed of theelectrode 115, theupper electrode 103 and the insulatingfilm 114 in parallel. More specifically, theelectrode 115 also functions as a lower electrode, similarly as thelower electrode 102. - The
opening portion 141 is slit-shaped in plan view, similarly as theopening portion 121 and theopening portion 122. In particular in the present embodiment, theopening portion 121, theopening portion 122 and theopening portion 141 are identical in terms of geometry, dimension and position. Here, it is preferable that a width S3 of theopening portion 141 is equal to or shorter than a thickness T3 of theelectrode 115. The rest of elements in the configuration of thesemiconductor device 3 is similar to that of thesemiconductor device 1. - The
semiconductor device 3 having such configuration is capable of providing advantageous effects described below, in addition to the advantageous effects described above in reference to thesemiconductor device 1. In thesemiconductor device 3, both of thelower electrode 102 and theelectrode 115 function as a lower electrode. This configuration provides a configuration, in which the MIM capacitance between thelower electrode 102 and theupper electrode 103 is coupled to the MIM capacitance between theupper electrode 103 and theelectrode 115 in parallel, thereby achieving an increased capacitance value per unit area. Even in such case, by having the slit width S to be equal to or smaller than the thickness of the electrode, the MIM capacitance, which is suitable in providing a prevention of an influence by a dishing and a reduction in variation of capacitance value resulting from geometric variation, can be achieved. - While the preferred embodiments of the present invention have been described above in reference to the annexed figures, it should be understood that the disclosures above are presented for the purpose of illustrating the present invention only, and various modifications other than the above described configurations can also be adopted. For example, as shown in
FIG. 11 , theopening portion 121 and theopening portion 122 may be provided in different positions in plan view. A plan view of the semiconductor device ofFIG. 11 is shown inFIG. 12 . A cross section along line A-A′ ofFIG. 12 corresponds to the cross sectional view ofFIG. 11 . - As shown in
FIG. 13 , theopening portion 121 may have a dimension in plan view that is different from a dimension of theopening portion 122. A plan view of the semiconductor device ofFIG. 13 is shown inFIG. 14 . A cross section along line A-A′ ofFIG. 14 corresponds to the cross sectional view ofFIG. 13 . - As shown in
FIG. 15 , thelower electrode 102 and theupper electrode 103 may be ladder-shaped in plan view. - As shown in
FIG. 16 , theopening portion 121 and theopening portion 122, may be annular-shaped in plan view. - As shown in
FIG. 17 , a plurality of openingportions 121 and a plurality of openingportions 122 may be provided, and are arranged to form a lattice pattern in plan view. In this exemplary implementation, a plurality of opening portions 121 (opening portions 122) are arranged to form a diagonal lattice pattern. - It is apparent that the present invention is not limited to the above embodiment, and may be modified and changed without departing from the scope and spirit of the invention.
Claims (9)
1. A semiconductor device, comprising:
a first electrode provided on a semiconductor substrate;
a capacitive film, provided on said first electrode so as to be in contact with the first electrode;
a second electrode, provided on said capacitive film so as to be in contact with the capacitive film, said second electrode, said first electrode and said capacitive film constituting a capacitor element;
a first opening portion, provided in said first electrode and extending through the first electrode; and
a second opening portion, provided in said second electrode and extending through the second electrode,
wherein an insulating film is embedded within said first opening portion and said second opening portion.
2. The semiconductor device according to claim 1 , wherein a width of said first opening portion and a width said second opening portion are equal to or shorter than a thickness of said first electrode and a thickness of second said electrode, respectively.
3. The semiconductor device according to claim 1 , wherein each of said first electrode and said second electrode is composed of a metallic film and a diffusion barrier film covering a surface of the metallic film.
4. The semiconductor device according to claim 1 , further comprising:
a second capacitive film, provided on said second electrode so as to be in contact with the second electrode;
a third electrode, provided on said second capacitive film so as to be in contact with said second capacitive film, said third electrode, said second electrode and said second capacitive film constituting a capacitor element; and
a third opening portion, provided in said third electrode and extending through the third electrode,
wherein an insulating film is embedded within said third opening portion.
5. The semiconductor device according to claim 1 , wherein an orthogonal projection of said first opening portion to a plane that is parallel to a substrate surface of said semiconductor substrate is identical with an orthogonal projection of said second opening portion to said plane.
6. The semiconductor device according to claim 1 , wherein said first opening portion and said second opening portion are slit-shaped in plan view.
7. The semiconductor device according to claim 1 , wherein said first opening portion and said second opening portion are annular-shaped in plan view.
8. The semiconductor device according to claim 1 , wherein a plurality of said first opening portions and a plurality of said second opening portions are provided, and are arranged to form a lattice pattern in plan view.
9. The semiconductor device according to claim 1 , wherein said first electrode and said second electrode are ladder-shaped in plan view.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070013028A1 (en) * | 2005-07-14 | 2007-01-18 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20100001332A1 (en) * | 2008-07-03 | 2010-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating a capacitor in a metal gate last process |
US20230020162A1 (en) * | 2021-07-16 | 2023-01-19 | Key Foundry Co., Ltd. | Semiconductor device with metal-insulator-metal (mim) capacitor and mim manufacturing method thereof |
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US9382180B2 (en) | 2012-12-06 | 2016-07-05 | Dow Technology Investments Llc | Hydroformylation process |
CN104045532B (en) | 2013-03-15 | 2018-05-25 | 陶氏技术投资有限责任公司 | Hydroformylation process |
RU2649574C2 (en) | 2013-06-25 | 2018-04-04 | Дау Текнолоджи Инвестментс Ллс | Method of selective hydrogenization |
CN104513143A (en) | 2013-09-26 | 2015-04-15 | 陶氏技术投资有限责任公司 | Hydroformylation process |
PL3126319T3 (en) | 2014-03-31 | 2020-01-31 | Dow Technology Investments Llc | Hydroformylation process |
JP2024513740A (en) | 2021-03-31 | 2024-03-27 | ダウ テクノロジー インベストメンツ リミティド ライアビリティー カンパニー | Hydroformylation process |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020187604A1 (en) * | 1999-01-27 | 2002-12-12 | Shogo Inaba | Semiconductor devices and manufacturing methods thereof |
US6894331B2 (en) * | 1999-12-14 | 2005-05-17 | Kabushiki Kaisha Toshiba | MIM capacitor having flat diffusion prevention films |
US20050161725A1 (en) * | 2002-04-19 | 2005-07-28 | Nicola Da Dalt | Semiconductor component comprising an integrated latticed capacitance structure |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0376262A (en) * | 1989-08-18 | 1991-04-02 | Nec Corp | Semiconductor device |
JP3351377B2 (en) * | 1999-03-12 | 2002-11-25 | 日本電気株式会社 | High frequency circuit device |
US6611014B1 (en) * | 1999-05-14 | 2003-08-26 | Kabushiki Kaisha Toshiba | Semiconductor device having ferroelectric capacitor and hydrogen barrier film and manufacturing method thereof |
JP4173374B2 (en) * | 2003-01-08 | 2008-10-29 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
JP2005109063A (en) * | 2003-09-30 | 2005-04-21 | Matsushita Electric Ind Co Ltd | Semiconductor device |
US7169665B2 (en) * | 2004-05-04 | 2007-01-30 | Tawian Semiconductor Manufacturing Company, Ltd. | Capacitance process by using passivation film scheme |
JP5103232B2 (en) * | 2008-03-18 | 2012-12-19 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
2006
- 2006-01-31 JP JP2006022842A patent/JP2007207878A/en active Pending
-
2007
- 2007-01-17 GB GB0700887A patent/GB2434693B/en not_active Expired - Fee Related
- 2007-01-30 US US11/699,336 patent/US20070176259A1/en not_active Abandoned
- 2007-01-30 CN CNB2007100047898A patent/CN100454541C/en not_active Expired - Fee Related
-
2009
- 2009-08-04 US US12/535,282 patent/US8143698B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020187604A1 (en) * | 1999-01-27 | 2002-12-12 | Shogo Inaba | Semiconductor devices and manufacturing methods thereof |
US6894331B2 (en) * | 1999-12-14 | 2005-05-17 | Kabushiki Kaisha Toshiba | MIM capacitor having flat diffusion prevention films |
US20050161725A1 (en) * | 2002-04-19 | 2005-07-28 | Nicola Da Dalt | Semiconductor component comprising an integrated latticed capacitance structure |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070013028A1 (en) * | 2005-07-14 | 2007-01-18 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US7719085B2 (en) * | 2005-07-14 | 2010-05-18 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20100001332A1 (en) * | 2008-07-03 | 2010-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating a capacitor in a metal gate last process |
US8368136B2 (en) * | 2008-07-03 | 2013-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating a capacitor in a metal gate last process |
US20230020162A1 (en) * | 2021-07-16 | 2023-01-19 | Key Foundry Co., Ltd. | Semiconductor device with metal-insulator-metal (mim) capacitor and mim manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
GB2434693A (en) | 2007-08-01 |
JP2007207878A (en) | 2007-08-16 |
CN100454541C (en) | 2009-01-21 |
GB0700887D0 (en) | 2007-02-21 |
GB2434693B (en) | 2009-10-21 |
US20100006980A1 (en) | 2010-01-14 |
CN101013696A (en) | 2007-08-08 |
US8143698B2 (en) | 2012-03-27 |
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