CN109411473A - A kind of DRAM storage chip and its manufacturing method - Google Patents
A kind of DRAM storage chip and its manufacturing method Download PDFInfo
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- CN109411473A CN109411473A CN201811308087.3A CN201811308087A CN109411473A CN 109411473 A CN109411473 A CN 109411473A CN 201811308087 A CN201811308087 A CN 201811308087A CN 109411473 A CN109411473 A CN 109411473A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/244—Connecting portions
Abstract
This application discloses a kind of DRAM storage chip and its manufacturing methods.In the DRAM storage chip, storage array and peripheral circuit are separately positioned on different chips, i.e., peripheral circuit is arranged on the first chip, and storage array is arranged on the second chip.So, the area of chip where peripheral circuit will not occupy storage array, therefore, it is possible to be respectively provided with storage array on the first chip of full wafer, in this way, being conducive to improve the efficiency (i.e. the ratio of storage array chip occupying area) and bit line density of storage array.
Description
Technical field
This application involves technical field of semiconductor device more particularly to a kind of DRAM storage chip and its manufacturing methods.
Background technique
DRAM (Dynamic RandomAccess Memory, dynamic random access memory) is to utilize selection transistor
Storage capacitance is charged and discharged and then be realized the main memory technology of storage " 0 " and " 1 ".
DRAM storage chip not only includes multiple storage arrays for repeating storage capacitance, further includes the periphery electricity of high-speed cruising
Road, the peripheral circuit is for decoding, detecting storage array and reading data etc..
In existing DRAM storage chip, because peripheral circuit occupies biggish chip area, for example, being deposited in some DRAM
It stores up in chip, peripheral circuit occupies the chip area of more than half, in this way, causing in DRAM storage chip, storage array
Efficiency and bit line density it is smaller.
Summary of the invention
In view of this, this application provides a kind of DRAM storage chip and its manufacturing method, to improve DRAM storage chip
In, the efficiency and bit line density of storage array.
In order to solve the above-mentioned technical problem, the application adopts the technical scheme that
A kind of DRAM storage chip, comprising:
The first chip and the second chip of electrical connection；
Peripheral circuit is provided on first chip；
Storage array is provided on second chip, the storage array includes multiple storage units.
Optionally, it is stepped construction that the first chip of electrical connection and second chip, which are formed by structure,.
Optionally, it is logical that a plurality of the first metals being electrically connected with the peripheral circuit are provided in first chip front side
Hole is provided with a plurality of the second metal throuth holes being electrically connected with the storage unit in second chip front side；
First metal throuth hole is docked with second metal throuth hole and is bonded together, thus make first chip and
The second chip electrical connection.
Optionally, multiple the first conductive plungers being electrically connected with the peripheral circuit, institute are provided on first chip
It states and is provided with multiple the second conductive plungers being electrically connected with the storage unit on the second chip；
The first conductive plunger and the second conductive plunger are docking together, to make first chip and described
The electrical connection of second chip.
Optionally, the described first conductive plunger is through silicon via and/or second conductive column through first chip
Plug is through the through silicon via of second chip.
Optionally, the peripheral circuit is cmos circuit.
Optionally, the peripheral circuit includes row decoder, column decoder, control circuit, input/output (i/o) buffer, shape
At least one of state machine and Static RAM.
A kind of manufacturing method of DRAM storage chip, comprising:
Peripheral circuit is formed on the first chip, forms storage array on the second chip, the storage array includes more
A storage unit；
First chip and second chip are electrically connected.
Optionally, the method also includes:
A plurality of the first metal throuth holes being electrically connected with the peripheral circuit are formed in the front of first chip；
A plurality of the second metal throuth holes being electrically connected with the storage unit are formed in the front of second chip；
It is described that first chip and second chip are electrically connected, it specifically includes:
First metal throuth hole is docked with second metal throuth hole and is bonded together, to make first chip
It is electrically connected with second chip.
Optionally, the method also includes:
Multiple the first conductive plungers being electrically connected with the peripheral circuit are formed on first chip, described second
Multiple the second conductive plungers being electrically connected with the storage unit are formed on chip；
It is described that first chip and second chip are electrically connected, it specifically includes:
Described first conductive plunger and the second conductive plunger are docking together, to make first chip and institute
State the electrical connection of the second chip.
Compared to the prior art, the application has the advantages that
Based on above technical scheme it is found that in DRAM storage chip provided by the present application, storage array and peripheral circuit point
It is not arranged on different chips, i.e., peripheral circuit is arranged on the first chip, and storage array is arranged on the second chip.Such as
This, the area of chip where peripheral circuit will not occupy storage array, therefore, it is possible to be respectively provided with storage on the first chip of full wafer
Array, in this way, being conducive to improve the efficiency (i.e. the ratio of storage array chip occupying area) and bit line density of storage array.
Detailed description of the invention
Fig. 1 is a kind of the schematic diagram of the section structure of DRAM storage chip provided by the embodiments of the present application；
Fig. 2 is a kind of flow diagram of DRAM storage chip manufacturing method provided by the embodiments of the present application；
Fig. 3 (1) to Fig. 3 (5) is a series of a kind of processing procedures of DRAM storage chip manufacturing method provided by the embodiments of the present application
Corresponding the schematic diagram of the section structure；
Fig. 4 is the schematic diagram of the section structure of another kind DRAM storage chip provided by the embodiments of the present application；
Fig. 5 is the flow diagram of another kind DRAM storage chip manufacturing method provided by the embodiments of the present application；
Fig. 6 (1) to Fig. 6 (3) is a series of systems of another kind DRAM storage chip manufacturing method provided by the embodiments of the present application
The corresponding structural schematic diagram of journey.
Specific embodiment
Based on background technology part it is found that existing DRAM storage chip not only includes multiple storages for repeating storage capacitance
Array further includes the peripheral circuit of high-speed cruising.Peripheral circuit and storage array are located on the same chip, and in usual situation
Under, peripheral circuit can occupy biggish chip area, cause the efficiency of storage array and bit line density smaller.
In view of this, including: electrical connection in the DRAM storage chip this application provides a kind of DRAM storage chip
First chip and the second chip are provided with storage array wherein being provided with peripheral circuit on the first chip on the second chip, storage
Array may include multiple storage units, and each storage unit includes selection transistor and storage capacitance.In this way, storage array
On different chips with peripheral circuit setting, peripheral circuit will not occupy area of the storage array on chip, can be in full wafer
Storage array is respectively provided on second chip, thus, be conducive to efficiency (the i.e. storage array chip occupying area for improving storage array
Ratio) and bit line density.
In order to make the above objects, features, and advantages of the present application more apparent, with reference to the accompanying drawing to the application
Specific embodiment be described in detail.
Referring to Fig. 1, Fig. 1 is a kind of implementation of DRAM storage chip provided by the embodiments of the present application.
A kind of DRAM storage chip provided by the embodiments of the present application, comprising:
First chip 10 and the second chip 11；
Wherein, peripheral circuit 101 and a plurality of the first gold medals being electrically connected with peripheral circuit 101 are provided on the first chip 10
Belong to through-hole 102；
Storage array is provided on second chip 11, wherein storage array includes multiple storage units 111, each storage
Unit 111 includes selection transistor and storage capacitance；It a plurality of is electrically connected with storage unit in addition, being additionally provided on the second chip 11
The second metal throuth hole 112 connect.
First metal throuth hole 102 and the docking of the second metal throuth hole 112 are bonded together, to realize the first chip 10 and second
The electrical connection of chip 11.
It is to be appreciated that in the embodiment of the present application, storage unit realizes information using selection transistor and storage capacitance
Storage, the information can be stored in the form of " 0 " and " 1 ".
It, can be in the first metal throuth hole 102 and the second metal in order to realize the conducting function of metal throuth hole as an example
Through-hole 112 can be that the through-hole of its solid metal material as another example can also be in 102 He of the first metal throuth hole
The side wall of second metal throuth hole 112, which powers on, plates one layer of metal material.Wherein, the metal material that is filled in metal throuth hole or
The metal material layer being electroplated on metal throuth hole side wall can be W, Cu, TiAl, Al or other suitable metal materials.
As an example, the first metal throuth hole 102 can be realized and peripheral circuit 11 by metal interconnecting wires layer and contact hole
Electrical connection.Equally, the second metal throuth hole 112 can also realize the electricity with storage array by metal interconnecting wires layer and contact hole
Connection.
In addition, the quantity of the first metal throuth hole 102 can be identical as the quantity of the second metal throuth hole 112, in this way, docking
When bonding, docking one by one for first metal throuth hole 102 and second metal throuth hole 112 is formed.
In addition, in the embodiment of the present application, the first chip 10 of electrical connection and the second chip 11 form stepped construction, such as
This, can reduce the area of integrated circuit, effectively control the size of chip.
In the embodiment of the present application, peripheral circuit 101 can be used for decoding, detect storage array and read data.More
Specifically, which can also be row decoder, column decoder, control circuit, input/output (i/o) buffer, state machine
At least one of with Static RAM.As an example, peripheral circuit 101 can be cmos circuit,
The above are a kind of implementations of DRAM storage chip provided by the embodiments of the present application.In this implementation, it deposits
Storage array and peripheral circuit 101 are separately positioned on different chips, i.e., peripheral circuit 101 is arranged on the first chip 10, are deposited
Array is stored up to be arranged on the second chip 11.In this way, peripheral circuit 101 will not occupy the area of storage array place chip, thus,
It can be respectively provided with storage array on the first chip of full wafer 10, in this way, being conducive to improve efficiency (the i.e. storage array of storage array
The ratio of chip occupying area) and bit line density.
It should be noted that by the way that storage array and peripheral circuit 101 to be separately positioned on different chips, periphery electricity
Road 101 will not occupy the area of chip where storage array, in this way, be conducive to improve storage array efficiency and bit line it is close
Degree.And due to not influenced by peripheral circuit 101, individually storage array can also be optimized, for example, can be independent
To in storage array selection transistor and storage capacitance be adjusted, with realize reduce leakage current and longer time preservation number
According to.
In addition, because storage array and peripheral circuit 101 are arranged on different chips, therefore, the production of storage array
Journey will not influence the performance of peripheral circuit, and the selection of the process conditions of the production storage array can not be by peripheral circuit 101
Constraint limits, and therefore, can according to need the process conditions for freely selecting and forming high-performance storage unit, such as can root
Form high performance storage unit according to needing to select some high-temperature technologies, so, from the technological process of storage unit this
For one side, it is also beneficial to improve the performance of dram chip.
Similarly, peripheral circuit 101 is arranged on the first chip 10, can also individually be adjusted to peripheral circuit 101, because
For the heat affecting that not will receive storage unit, the optimization of peripheral circuit 101 may be implemented faster to run.In addition, realizing electricity
After connection, in storage array selection transistor have less leakage current also can effectively improve in peripheral circuit 101 input and
The speed of service of output buffer and reduce power consumption.
The above are the specific embodiments of DRAM storage chip provided by the embodiments of the present application, provide based on the above embodiment
DRAM storage chip, correspondingly, present invention also provides the specific implementations of DRAM storage chip manufacturing method.
It refers to Fig. 2 to Fig. 3 (5), Fig. 2 is a kind of stream of DRAM storage chip manufacturing method provided by the embodiments of the present application
Journey schematic diagram；Fig. 3 (1) to Fig. 3 (5) is a series of according to a kind of DRAM storage chip manufacturing method provided by the embodiments of the present application
The corresponding the schematic diagram of the section structure of processing procedure.
The manufacturing method of DRAM storage chip provided by the embodiments of the present application the following steps are included:
S201: peripheral circuit 101 is formed on the first chip 10.
As an example, peripheral circuit 101 can be cmos circuit, and in a particular application, peripheral circuit 101 can also be
At least one in row decoder, column decoder, control circuit, input/output (i/o) buffer, state machine and Static RAM
Kind.
Peripheral circuit 101 is arranged on the first chip 10, individually peripheral circuit 101 can be adjusted, because not
The heat affecting that will receive storage unit optimizes peripheral circuit 101, can effectively improve the speed of service and reduces function
Consumption.
It has executed shown in the corresponding the schematic diagram of the section structure of the step such as Fig. 3 (1).
S202: a plurality of the first metal throuth holes being electrically connected with peripheral circuit 101 are formed in the front of the first chip 10
102。
The step can with specifically, using the method for the dry etchings such as plasma etching on the front of the first chip 10 shape
Pluralize first metal throuth hole 102, wherein the first metal throuth hole 102 can be by metal interconnecting wires layer and contact hole and outer
Enclose the electrical connection of circuit 101.
It, can be in the first metal throuth hole 102 as an example in order to realize the conducting function of the first metal throuth hole 102
Metal material is filled up in portion, as another example, can also power in the side wall of the first metal throuth hole 102 and plate one layer of metal material
Material.Wherein, gold of the metal material or plating being filled in the first metal throuth hole 102 on 102 side wall of the first metal throuth hole
Belonging to material layer can be W, Cu, TiAl, Al or other suitable metal materials.
Having executed the corresponding the schematic diagram of the section structure of the step, such as Fig. 3 (2) are shown respectively.
S203: storage array is formed on the second chip 11.
Storage array may include multiple storage units 111, and each storage unit 111 may include selection transistor and deposit
Storage is held.
In addition, storage array is arranged on the second chip 11 different with 101 place chip of peripheral circuit, peripheral circuit
101 will not occupy the area of chip where storage array, in this way, be conducive to improve storage array efficiency and bit line it is close
Degree.And due to not influenced by peripheral circuit 101, individually storage array can also be optimized, for example, can be independent
To in storage array selection transistor and storage capacitance be adjusted, with realize reduce leakage current and longer time preservation number
According to.
It has executed shown in the corresponding the schematic diagram of the section structure of the step such as Fig. 3 (3).
S204: a plurality of the second metal throuth holes 112 being electrically connected with storage array are formed in the front of the second chip 11.
The step can with specifically, using the method for the dry etchings such as plasma etching on the front of the second chip 11 shape
Pluralize second metal throuth hole 112, wherein the second metal throuth hole 112 can pass through metal interconnecting wires layer and contact hole and the
The electrical connection of two chips 11.
It, can be in the second metal throuth hole 112 as an example in order to realize the conducting function of the second metal throuth hole 112
Metal material is filled up in portion, as another example, can also power in the side wall of the second metal throuth hole 112 and plate one layer of metal material
Material.Wherein, gold of the metal material or plating being filled in the second metal throuth hole 112 on 112 side wall of the second metal throuth hole
Belonging to material layer can be W, Cu, TiAl, Al or other suitable metal materials.
Having executed the corresponding the schematic diagram of the section structure of the step, such as Fig. 3 (4) are shown respectively.
It should be noted that the application is to the execution of S201-S202 and S203-S204 sequence and without limitation.In this way, making
For the example of the application, S201-S202 can be first carried out, then execute S203-S204, as another example, can also first held
Row S203-S204, then execute S201-S202.
S205: the first chip 10 and the second chip 11 are electrically connected by metal throuth hole.
The step can be with specifically: is inverted 10 front of the first chip and is layered on the second chip 11, makes the first chip 10
Second metal throuth hole 112 of the 11 front setting of the first metal throuth hole 102 and the second chip of front setting docks bonding, and then makes
Peripheral circuit 101, the first metal throuth hole 102, the second metal throuth hole 112 and storage array electrical connection, realize 10 He of the first chip
The electrical connection of second chip 11.
It is to be appreciated that being bonded the electrical connection for realizing the first chip 10 and the second chip 11 by metal throuth hole, it is not necessarily to lead
Bonding, therefore resistance can be reduced, effectively improve the electric property of chip.
The step has executed corresponding the schematic diagram of the section structure, and such as Fig. 3 (5) are shown respectively.
The above are a kind of specific implementations of the manufacturing method of DRAM storage chip provided by the embodiments of the present application.Pass through
In DRAM storage chip made of the specific implementation, storage array and peripheral circuit 101 are separately positioned on different chips
On, i.e., peripheral circuit 101 is arranged on the first chip 10, and storage array is arranged on the second chip 11.In this way, peripheral circuit
101 will not occupy the area of storage array place chip, therefore, it is possible to it is respectively provided with storage array on the first chip of full wafer 10,
In this way, being conducive to improve the efficiency (i.e. the ratio of storage array chip occupying area) and bit line density of storage array.
It should be noted that by the way that storage array and peripheral circuit 101 to be separately positioned on different chips, periphery electricity
Road 101 will not occupy the area of chip where storage array, in this way, be conducive to improve storage array efficiency and bit line it is close
Degree.And due to not influenced by peripheral circuit 101, individually storage array can also be optimized, for example, can be independent
To in storage array selection transistor and storage capacitance be adjusted, with realize reduce leakage current and longer time preservation number
According to.
In addition, because storage array and peripheral circuit 101 are arranged on different chips, therefore, the production of storage array
Journey will not influence the performance of peripheral circuit, and the selection of the process conditions of the production storage array can not be by peripheral circuit 101
Constraint limits, and therefore, can according to need the process conditions for freely selecting and forming high-performance storage unit, such as can root
Form high performance storage unit according to needing to select some high-temperature technologies, so, from the technological process of storage unit this
For one side, it is also beneficial to improve the performance of dram chip.
Similarly, peripheral circuit 101 is arranged on the first chip 10, can also individually be adjusted to peripheral circuit 101, because
For the heat affecting that not will receive storage unit, the optimization of peripheral circuit 101 may be implemented faster to run.In addition, realizing electricity
After connection, in storage array selection transistor have less leakage current also can effectively improve in peripheral circuit 101 input and
The speed of service of output buffer and reduce power consumption.
In addition, realizing the electrical connection of the first chip 10 and the second chip 11 in such a way that metal throuth hole is bonded, additionally it is possible to
Effectively improve the electric property of DRAM storage chip.
Above embodiment illustrates a kind of DRAM storage chips that electrical connection is realized by metal throuth hole, in addition, as this
Another embodiment of application, the first chip and the second chip can also pass through other electric connection modes, such as the side of conductive plunger
Formula realizes electrical connection.
Wherein, it is referred to by the specific implementation of conductive plunger the first chip of realization and the electrical connection of the second chip following
Embodiment.
As shown in figure 4, a kind of DRAM storage chip for realizing electrical connection by conductive plunger provided by the present application, comprising:
First chip 40 and the second chip 41；
Wherein, peripheral circuit and multiple the first conductive plungers being electrically connected with peripheral circuit are provided on the first chip 40
401；
Storage array is provided on second chip 41, wherein storage array includes multiple storage units, each storage unit
Including selection transistor and storage capacitance；In addition, being additionally provided with multiple second be electrically connected with storage unit on the second chip 41
Conductive plunger 411；
First chip 40 and the second chip 41 are realized and are electrically connected by the first conductive plunger 401 and the second conductive plunger 411.
It should be noted that in the embodiment of the present application, the structure and above-described embodiment of storage array and peripheral circuit
In storage array it is identical as the structure of peripheral circuit, for the sake of brevity, details are not described herein.Details refer to above-mentioned
The description of embodiment.
In addition, the region for being not provided with storage unit on the first chip 40 is arranged in the first conductive plunger 401, through the
Two surfaces of positive back of one chip 40, similarly, the second conductive plunger 411, which is arranged on the second chip 41, is not provided with peripheral circuit
Region, through two surfaces of positive back of the second chip 410.
In addition, for the improvement structure of more clearly prominent the embodiment of the present application, DRAM storage chip structure shown in Fig. 4
Figure is the schematic diagram of DRAM storage chip.In the schematic diagram, the conductive plunger on chip is only depicted, does not draw on chip and sets
The peripheral circuit and storage array set.
As an example, the first conductive plunger 401 can be for through through silicon via (the Through Silicon of the first chip 40
Via, TSV), the second conductive plunger 411 can be that the through silicon via through the second chip 41 is led to realize conducting function first
Polysilicon, metal or conductive polymer body etc. can be filled inside electric plunger 401 and the second conductive plunger 411, as a tool
Body example fills metallic copper in the first conductive plunger 401 and the second conductive plunger 411, since copper resistance rate is lower, in conduction
Dead resistance and parasitic capacitance can be effectively reduced in filling metallic copper in plunger, improves circuit speed.
In this embodiment, the first conductive plunger 401 can be electrically connected with peripheral circuit, and the second conduction plunger 411 can be with
It is electrically connected with storage unit.In addition, the first conductive plunger 401 is identical with the second 411 quantity of conductive plunger, when docking,
The docking one by one of one first conductive plunger 401 and one second conductive plunger 402 can be formed.
The above are another implementations of DRAM storage chip provided by the embodiments of the present application.What the implementation provided
For DRAM storage chip other than the beneficial effect with DRAM storage chip shown in FIG. 1, which passes through first
Conductive plunger 401 and the second conductive plunger 411 realize the electrical connection of the first chip 40 and the second chip 41, can also be more effectively
DRAM storage chip integration density is improved, power consumption is effectively reduced.
Another implementation of the DRAM storage chip provided based on the above embodiment, correspondingly, the application also provides
The specific implementation of the DRAM storage chip manufacturing method.It refers to Fig. 5 to Fig. 6 (3), Fig. 5 is that the embodiment of the present application mentions
The flow diagram of another DRAM storage chip manufacturing method supplied；Fig. 6 (1) to Fig. 6 (3) is mentioned according to the embodiment of the present application
A series of corresponding structural schematic diagram of another processing procedures of DRAM storage chip manufacturing method supplied.
The manufacturing method another kind specific implementation of DRAM storage chip provided by the embodiments of the present application includes following step
It is rapid:
S501 is identical as above-mentioned S201, for the sake of brevity, is not described in detail herein.
S502: multiple the first conductive plungers 401 being electrically connected with peripheral circuit are formed on the first chip 40.
In this embodiment, the first conductive plunger 401 can use through silicon via technology (TSV, Through Silicon
Via it) is formed.
Correspondingly, this step can be with specifically: can be formed by the methods of deep layer plasma etching or laser opening
Metal filling is carried out to through-hole through multiple vertical through hole of the first chip 40, then by way of plating or chemical deposition,
To form the first conductive plunger 401.As a particular example, the filling metal inside the first conductive plunger 401 can be copper,
Using metallic copper as packing material, since copper resistance rate is lower, dead resistance and parasitic capacitance can be effectively reduced, improve circuit
Speed.
After the metal filling for completing through-hole, the conductive plunger 401 of multiple the first of formation can be used for carrying out with peripheral circuit
Electrical connection.
The step has executed shown in corresponding the schematic diagram of the section structure such as Fig. 6 (1), it should be noted that in order to become apparent from
The improvement structure of the prominent the embodiment of the present application in ground, Fig. 6 (1) show the structure diagram of the first chip 40, only depict first and lead
Electric plunger 401 does not draw the internal structure of the first chip 40.
S503 is identical as above-mentioned S203, for the sake of brevity, is not described in detail herein.
S504: multiple the second conductive plungers 411 being electrically connected with storage array are formed on the second chip 41.
In this embodiment, the second conductive plunger 411 can use through silicon via technology and be formed.
Correspondingly, this step can be with specifically: can be formed by the methods of deep layer plasma etching or laser opening
Metal filling is carried out to through-hole through multiple vertical through hole of the second chip 41, then by way of plating or chemical deposition,
To form the second conductive plunger 411.As a particular example, the filling metal inside the second conductive plunger 411 can be copper,
Using metallic copper as packing material, since copper resistance rate is lower, dead resistance and parasitic capacitance can be effectively reduced, improve circuit
Speed.
After the metal filling for completing through-hole, the conductive plunger 411 of multiple the second of formation can be used for carrying out with storage array
Electrical connection.
The step has executed corresponding the schematic diagram of the section structure, and such as Fig. 6 (2) are shown respectively.Likewise, in order to more clearly
The improvement structure of prominent the embodiment of the present application, Fig. 6 (2) show the structure diagram of the second chip 41, only depict the second conduction
Plunger 411 does not draw the internal structure of the second chip 41.
It should be noted that the application is to the execution of S501-S502 and S503-S504 sequence and without limitation.In this way, making
For the example of the application, S501-S502 can be first carried out, then execute S503-S504, as another example, can also first held
Row S503-S504, then execute S501-S502.
S505: the first chip 40 and the second chip 41 are electrically connected by conductive plunger.
The step can be with specifically: is connected electrically in respectively in the needs of the first conductive plunger 401 and the second conductive plunger 411
Weld pad is formed on one end together.Then, the first chip 40 staggered relatively and the second chip 41, and make on the first chip 40
One conductive plunger 401 is aligned with the second conductive plunger 411 on the second chip 41, then passes through welding procedure for the first conductive column
Plug 401 and the second conductive plunger 411 link together, thus realize the electrical connection of the first chip 40 and the second chip 41, thus
By peripheral circuit, the first conductive plunger 411 of conductive plunger 401, second and storage array electrical connection.
It is to be appreciated that in the embodiment of the present application, conductive plunger realizes the electrical connection of the first chip 40 and the second chip 41,
Be conducive to improve the integration density of DRAM storage chip, the speed of service and reduce power consumption.
The step has executed corresponding the schematic diagram of the section structure, and such as Fig. 6 (3) are shown respectively.
The above are another specific implementations of the manufacturing method of DRAM storage chip provided by the embodiments of the present application.It is logical
The specific implementation is crossed, DRAM storage chip shown in Fig. 4 can be made.
The above are DRAM storage chip provided by the embodiments of the present application and its specific implementations of manufacturing method.Above-mentioned
In specific implementation, the electric connection mode of the first chip and the second chip be in a manner of metal throuth hole or conductive plunger as
What example was illustrated.In fact, the electric connection mode of the first chip and the second chip is not limited to above-mentioned electric connection mode, also
It can be other electric connection modes, such as: electrical lead etc..
The above is only the preferred embodiment of the application, although the application has been disclosed in the preferred embodiments as above, so
And it is not intended to limit the invention.Anyone skilled in the art is not departing from technical scheme ambit
Under, many possible changes and modifications all are made to technical scheme using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, all contents without departing from technical scheme, according to the application's
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within present techniques side
In the range of case protection.
Claims (10)
1. a kind of DRAM storage chip characterized by comprising
The first chip and the second chip of electrical connection；
Peripheral circuit is provided on first chip；
Storage array is provided on second chip, the storage array includes multiple storage units.
2. DRAM storage chip according to claim 1, which is characterized in that the first chip of electrical connection and second core
It is stepped construction that piece, which is formed by structure,.
3. DRAM storage chip according to claim 2, which is characterized in that be provided with plural number in first chip front side
A the first metal throuth hole being electrically connected with the peripheral circuit is provided in second chip front side a plurality of with the storage
Second metal throuth hole of unit electrical connection；
First metal throuth hole is docked with second metal throuth hole and is bonded together, to make first chip and described
The electrical connection of second chip.
4. according to DRAM storage chip described in right 2, which is characterized in that be provided on first chip multiple and described outer
The first conductive plunger of circuit electrical connection is enclosed, is provided with multiple second be electrically connected with the storage unit on second chip
Conductive plunger；
Described first conductive plunger and the second conductive plunger are docking together, to make first chip and described second
Chip electrical connection.
5. DRAM storage chip according to claim 4, which is characterized in that the first conductive plunger is through described the
The through silicon via of one chip and/or the second conductive plunger are the through silicon via through second chip.
6. DRAM storage chip according to claim 1-4, which is characterized in that the peripheral circuit is CMOS electricity
Road.
7. DRAM storage chip according to claim 1-6, which is characterized in that the peripheral circuit includes row solution
At least one of code device, column decoder, control circuit, input/output (i/o) buffer, state machine and Static RAM.
8. a kind of manufacturing method of DRAM storage chip characterized by comprising
Peripheral circuit is formed on the first chip, forms storage array on the second chip, the storage array includes multiple deposits
Storage unit；
First chip and second chip are electrically connected.
9. according to the method described in claim 8, it is characterized in that, the method also includes:
A plurality of the first metal throuth holes being electrically connected with the peripheral circuit are formed in the front of first chip；
A plurality of the second metal throuth holes being electrically connected with the storage unit are formed in the front of second chip；
It is described that first chip and second chip are electrically connected, it specifically includes:
First metal throuth hole is docked with second metal throuth hole and is bonded together, to make first chip and institute
State the electrical connection of the second chip.
10. according to the method described in claim 8, it is characterized in that, the method also includes:
Multiple the first conductive plungers being electrically connected with the peripheral circuit are formed on first chip, in second chip
It is upper to form multiple the second conductive plungers being electrically connected with the storage unit；
It is described that first chip and second chip are electrically connected, it specifically includes:
Described first conductive plunger and the second conductive plunger are docking together, to make first chip and described the
The electrical connection of two chips.
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Application publication date: 20190301 |