CN104124240A - Stack system integrated circuit - Google Patents

Abstract

The invention provides a stack integrated circuit system which comprises: a first chip, having a first average density of pattern and contains storage cells; second chip, with second average pattern density and contains logic circuit of the memory cell with a functional unit; and plural silicon perforation, located in one of the first chip and the second chip in electrically connected to the first chip and the second chip, wherein the logic circuit of the memory cell of the first chip and the second chip is designed to be used together to achieve a complete memory function, wherein the first average density of pattern system is higher than that of the average of second pattern density.

Description

Storehouse integrated circuit (IC) system

Technical field

The present invention relates to a kind of storehouse integrated circuit (IC) system, relate in particular to a kind of storehouse integrated circuit (IC) system with silicon perforation.

Background technology

In order to save valuable arrangement space or the efficiency of increase interconnect, a plurality of integrated circuits (IC) chip stack can be become to an IC encapsulating structure together.In order to reach this object, can use a kind of three-dimensional (3D) storehouse encapsulation technology that plural integrated circuit (IC) chip is packaged together.This kind of three-dimensional (3D) storehouse encapsulation technology uses silicon perforation (TSV) widely.Silicon perforation (TSV) is a kind of vertical conduction through hole, and it is through-silicon wafer, silicon plate, made substrate or the chip of any material completely.Now, 3D integrated circuit (3DIC) is used to many fields as internal memory storehouse, image sensing chip etc. by wide.

Although silicon perforation has many advantages, it is also for integrated circuit has brought many challenges.For example, compared to its neighbours around as transistor AND gate interconnect etc., its huge volume (than traditional transistor large upper 100 times or more) can waste many arrangement spaces.It wastes the more space, and chip can become larger.Now, all electronic installations are all at micro competitively, therefore wasting space is not the wise practice.Therefore, need can strive for as far as possible, save the space that silicon perforation is wasted.

Summary of the invention

The present invention relates to a kind of storehouse integrated circuit (IC) system, comprise: the first chip, has the first average pattern density and comprise memory cell; The second chip, has the second average pattern density and comprises logical circuit and the functional unit that this memory cell is used; And plural silicon perforation, be arranged in this first chip with the one of the second chip to be electrically connected to this first chip and this second chip, wherein this memory cell of this first chip and this logical circuit of this second chip are designed to jointly use to reach complete memory function, and wherein this first average pattern density is higher than this second average pattern density.

A kind of storehouse integrated circuit (IC) system is provided, comprises: the first chip, has memory cell; The second chip, has the first of the logical circuit that this memory cell uses; The 3rd chip, has the second portion of the logical circuit that this memory cell uses; And plural silicon perforation, be arranged in this first chip, the second chip with the one of the 3rd chip to be electrically connected to this first chip, this second chip and the 3rd chip, wherein this memory cell of this first chip, this second portion of the first of this logical circuit of this second chip and this logical circuit of the 3rd chip be designed to jointly use to reach complete memory function.

A kind of storehouse integrated circuit (IC) system is provided, comprises: the first chip, only comprises analog circuit; The second chip, only comprises digital circuit; The perforation of plural number silicon, be arranged in this first chip with the one of the second chip to be electrically connected to this first chip and this second chip, wherein this analog circuit of this first chip and this digital circuit of this second chip are designed to jointly use to reach complete function.

Accompanying drawing explanation

Fig. 1 shows according to the layout plane sketch plan of the convential memory array of prior art;

Fig. 2 shows according to the cross section sketch plan of storehouse integrated circuit (IC) system of one embodiment of the invention;

Fig. 3 shows according to one embodiment of the invention by the two chip stacks layout sketch plan of front two chips together;

Fig. 4 shows according to another embodiment of the present invention by the two chip stacks layout sketch plan of front two chips together;

Fig. 5 shows the drawing in side sectional elevation of the transistor level of integrated circuit;

Fig. 6 shows the cross section sketch plan of transistor level and the interconnect level of integrated circuit;

Fig. 7 shows according to the cross section sketch plan of storehouse integrated circuit (IC) system in another embodiment of the present invention.

Embodiment

To explain preferred embodiment of the present invention below; such as the sub-portion of assembly, assembly described in this, structure, material, configuration etc. all can be disobeyed the order of explanation or affiliated embodiment and be mixed into arbitrarily new embodiment, and these a little embodiment surely belong to protection category of the present invention.After having read the present invention; know this skill person when can be without departing from the spirit and scope of the invention; above-mentioned assembly, the sub-portion of assembly, structure, material, configuration etc. are done to a little change and retouching; therefore the present invention's scope of patent protection must be as the criterion depending on the appended claim person of defining of these claims, and these change with retouching when dropping in the present invention's claim.

Embodiments of the invention and illustrate numerously, for fear of obscuring, similarly assembly system shows it with same or analogous label.Figure is shown in and passes on concept of the present invention and spirit, therefore the shown distance in figure, size, ratio, shape, annexation .... wait and be all signal but not fact, all distance, size, ratio, shape, annexations that can reach in the same manner identical function or result .... wait and all can be considered equivalent and adopt.

Please refer to Fig. 1, it shows according to the layout plane sketch plan of the convential memory block in prior art.Central authorities at block are plural sensing amplifiers of plural memory array and contiguous memory array.Each memory array comprises hundreds of or thousands of memory cell as static random access memory born of the same parents or static random access memory born of the same parents, and each static random access memory born of the same parents or dynamic random access memory born of the same parents comprise at least one transistor.In the outer peripheral areas of memory block, be provided with logical circuit as column decoder, buffer and I/O (I/O).For a memory chip, it may comprise the memory block of hundreds of or thousands of these classes.

In single crystal grain (or chip), pattern density, live width add the size of spacing and the complexity of circuit is depended on, the generation of manufacturing process, the layout means that adopt and required usefulness in the number of plies of interconnect layer system.In having a crystal grain (or chip) in memory array and logical circuit region, the highest part of pattern density and live width add the minimum part of spacing and mostly appear in memory array.Therefore, utilize identical manufacturing process come the memory array shown in shop drawings 1 and logical circuit region often can cause in uneven thickness, critical size (CD) is inhomogeneous, the unequal problem of dopant profile, thereby cause low yield.Again, in order manufacturing, to there is the memory array that higher pattern density and less live width add spacing, must use and have compared with the technology controlling and process of high accurancy and precision and ability machinery equipment preferably, so cost to increase.In addition, memory cell is less than the required interconnect number of plies of logical circuit conventionally as static random access memory born of the same parents or the required interconnect number of plies of dynamic random access memory born of the same parents.Interconnect can be looked at as street and the highway of integrated circuit (IC), connects the assembly in integrated circuit and makes it as a whole practical function and by integrated circuit, be connected to outside; Neighbouring interconnect layer is conventionally orthogonal thereto each other.Although interconnect is very important for integrated circuit, the interconnect of too many layer can cause on the contrary some problem for example to drag the high parasitic capacitance problems of slow chip speed, affect crosstalk problem and heat dissipation problem that signal reads correctness.Therefore, need a scheme to solve the problems referred to above.

With reference now to Fig. 2,, it shows according to the cross section sketch plan of storehouse integrated circuit (IC) system of one embodiment of the invention.In Fig. 2, together with chip 1 is storehouse with chip 2 and utilize silicon perforation (TSV) 100 to be mutually electrically connected to dimpling piece/projection 200.Chip 1 and chip be loaded be designed to should together with use to reach the integrated circuit of complete memory function, that is, be only chip 1 one or chip 2 one and cannot suitably implement memory function.In the embodiment shown in Fig. 3, chip 1 can be loaded with all memory cell as static random access memory born of the same parents or dynamic random access memory born of the same parents, and chip 2 is loaded with all logical circuits as the column decoder of the row decoder of the column decoder in the row decoder in sensing amplifier, region, region, the whole district, the whole district, buffer and I/O.Again, chip 2 be not only be loaded with in order to control chip 1 and with the common logical circuit using of chip 1, and chip 2 is also loaded with functional unit that another one is complete as central processor unit (CPU), graphics processor unit (GPU), heat-sink unit or basic input/output (BIOS).In many prior arts, memory cell and its logical circuit be all arranged in identical chip another complete function list as central processor unit be to be arranged in another chip.Should note, each dynamic random access memory born of the same parents (DRAM) all comprises at least one capacitor of at least one transistor AND gate (no matter being the capacitor of irrigation canals and ditches type or stacked-type), and all comprising several transistors, each static random access memory born of the same parents (SRAM) (take 6T SRAM as example, six transistors), and in chip 1, have 1,000,000, these more than ten million a little memory cell are closely set together.

In shown another example of the present invention of Fig. 4, because sensing amplifier is more easily subject to the impact of noise compared to decoder and I/O, therefore sensing amplifier and memory cell are arranged in chip 1.Just so, it is not first and second portion that this complete functional unit in last embodiment is split into two parts.First and memory cell and sensing amplifier are arranged in chip 1, and second portion and memory cell logical circuit used is arranged in chip 2.

With reference now to Fig. 5,, it shows the drawing in side sectional elevation of the transistor level of integrated circuit.As shown in Figure 5, suppose that chip 1 and chip 2 all have the plural transistor 20 and each transistor 20 that are formed on substrate 10 and all have at least one gate electrode 22 and source/drain (S/D) 24.Integrated circuit on chip 1 has the first average pattern density and the first minimum pattern live width to add spacing (gate electrode 22 is omitted in rear extended meeting, adds spacing respectively referred to as the first average pattern density and the first minimum pattern live width) for gate electrode 22.Volume circuit on chip 2 has the second average pattern density for gate electrode 22 and the second minimum pattern live width adds spacing (gate electrode 22 is omitted in rear extended meeting, adds spacing respectively referred to as the second average pattern density and the second minimum pattern live width).The average pattern density of gate electrode 22 is defined as, and the occupied region of all gate electrodes 22 is divided by the region of whole chip.The minimum pattern live width of gate electrode 22 adds spacing and is defined as, and the minimum feature of the gate electrode that can find in whole chip adds spacing.The first average pattern density is different from the second average pattern density, and the first minimum pattern live width adds spacing and is different from the second minimum pattern live width and adds spacing.

Then please refer to Fig. 6, it shows the transistor level of integrated circuit and the cross section sketch plan of interconnect level.Fig. 6 provides substrate 10, transistor 20 and first layer metal (M1) to the simple relation between layer 6 metal (M6).As shown in Figure 6, contact is coupled to first layer metal (M1) by source/drain (S/D) 24, the first through hole (V1) is coupled to second layer metal (M2) by first layer metal (M1), the second through hole (V2) is coupled to three-layer metal (M3) by second layer metal (M2), third through-hole (V3) is coupled to the 4th layer of metal (M4) by three-layer metal (M3), fourth hole (V4) is coupled to layer 5 metal (M5) by the 4th layer of metal (M4), fifth hole (V5) is coupled to layer 6 metal (M6) by layer 5 metal (M5), therefore the number of plies of online layer is 6 according to the highest metal level (being layer 6 metal) within shown in Fig. 6.Integrated circuit on chip 1 has the interconnect layer of first number of plies, and the integrated circuit on chip 2 has the interconnect layer of second number of plies.First number of plies is different from second number of plies.

In the preferred embodiment shown in Fig. 2, the first average pattern density is higher than the second average pattern density, and it is to be less than the second minimum pattern live width to add spacing that the first minimum pattern live width adds spacing, and ground floor number system is less than second number of plies.

Although in Fig. 2, the size of chip 1 is greater than the size of chip 2, chip 1 is not so limited with the size of chip 2.For example, chip 1 can have identical size with chip 2.In the 2nd figure chips 2, be placed on chip 1 and be provided with silicon perforation 100 and dimpling piece/projection 200, but the present invention is by being limit again.Silicon perforation 100 and dimpling piece/projection 200 also can be arranged among chip 1/on, and chip 1 can be placed in chip 2 times.

With reference now to Fig. 7,, it shows according to the cross section sketch plan of storehouse integrated circuit (IC) system of another embodiment of the present invention.The embodiment system of Fig. 7 is similar to the embodiment of Fig. 2, but the embodiment of Fig. 7 many a chip 3 being arranged on chip 1, chip 3 be utilize among chip 3/on silicon perforation 100 ' be connected with chip 1 with dimpling piece/projection 200 '.Chip 1, chip 2 are loaded with and are designed to want jointly use to implement the integrated circuit of complete memory function with chip 3, are only that chip 1, chip 2 also cannot suitably be implemented due function with the one or both in chip 3.For example, chip 1 can be loaded with all memory cell as static random access memory born of the same parents or dynamic random access memory born of the same parents and sensing amplifier, chip 2 can be loaded with the logical circuit of part as region column decoder, region row decoder and buffer, and chip 3 can be loaded with remaining logical circuit as I/O, whole district's decoder and electrostatic discharge protection circuit.Integrated circuit on chip 3 has the 3rd average pattern density for gate electrode 22 and the 3rd minimum pattern live width adds spacing, and chip 3 has the interconnect layer of the 3rd number of plies.The 3rd average pattern density is to be different from the second and first average pattern density; The 3rd minimum pattern live width adds spacing and is different from the second and first minimum pattern live width and adds spacing; The 3rd number of plies is different from first and second number of plies.

In a preferred embodiment shown in Fig. 7, the first average pattern density is the highest, and the second average pattern density is that the 3rd average pattern density is minimum between the first average pattern density and the 3rd average pattern density.The rank order system that minimum pattern live width adds spacing is identical with average pattern density.As for the number of plies of interconnect layer, first number of plies should be minimum, but second number of plies and the 3rd number of plies can be identical or different.

Be similar to the embodiment of Fig. 2, the size of chip should be unrestricted.For example, chip 2 can have same size with chip 3.At Fig. 7 chips 2 and chip 3, be positioned on chip 1 and be provided with silicon perforation 100/100 ' and dimpling piece/projection 200/200 ', but the present invention is by being limit again.Silicon perforation 100/100 ' and dimpling piece/projection 200/200 ' also can be arranged among chip 1/on and chip 1 can be positioned under chip 2 and chip 3.

Or the chip 3 in Fig. 7 does not have driving component setting thereon for silicon intermediary layer.In the case, chip 1 and chip 2 are used together with both can implement complete memory function and central authorities/graphics processing function, but 3 of chips have the chip 1 of connection and 2 and be connected to extraneous interface function.Now, chip 3 can comprise silicon perforation, dimpling piece/projection, interconnect, passive component etc.Because chip 3 does not have driving component as transistor, therefore it does not have average pattern density, also do not there is minimum pattern live width and add spacing, and the number of plies of its interconnect layer is few.

In this way, the present invention can be applied to different chips from generation to generation by different technique, thereby improves the uniformity in each chip and reduce costs.Again, the present invention can be for customized its interconnect number of plies of each chip, and therefore more sensitive memory cell more can not be subject to noise jamming as static random access memory born of the same parents or dynamic random access memory born of the same parents.It is worth mentioning that, analog circuit also can have extremely different layout density from digital circuit sometimes, noise holds abundant, the interconnect number of plies, therefore the principle of the invention can be applied to the integrated circuit (IC) system that comprises analog circuit and digital circuit.By application principle of the present invention, analog circuit can be arranged to a chip and digital circuit is arranged to another chip, and two chips can utilize silicon to bore a hole to be electrically connected to and implement the complete function that cannot reach separately when a succession of chip separates.The chip with analog circuit and another chip pins with digital circuit can have different average pattern densities to gate electrode and/or different minimum pattern live widths adds spacing and/or the different interconnect numbers of plies.

Above-described embodiment is only to give an example for convenience of description, though modified arbitrarily by person of ordinary skill in the field, all can not depart from as the scope of institute's wish protection in claims.

Claims (10)

1. a storehouse integrated circuit (IC) system, comprises:

The first chip, has the first average pattern density and comprises memory cell;

The second chip, has the second average pattern density and comprises logical circuit and the functional unit that this memory cell is got rid of; And

Plural number silicon perforation, be arranged in this first chip with the one of the second chip to be electrically connected to this first chip and this second chip,

Wherein this memory cell of this first chip and this logical circuit of this second chip are designed to jointly use to reach complete memory function,

Wherein this first average pattern density is higher than this second average pattern density.

2. storehouse integrated circuit (IC) system as claimed in claim 1, is characterized in that, this memory cell is dynamic random access memory born of the same parents (DRAM) or static random access memory born of the same parents (SRAM).

3. storehouse integrated circuit (IC) system as claimed in claim 2, is characterized in that, this first chip more comprises the sensing amplifier that memory cell is used.

4. storehouse integrated circuit (IC) system as claimed in claim 3, is characterized in that, this logical circuit inclusion region row decoder, region column decoder, whole district's row decoder, whole district's column decoder, buffer and I/O.

5. storehouse integrated circuit (IC) system as claimed in claim 2, is characterized in that, this logical circuit comprises sensing amplifier, region row decoder, region column decoder, whole district's row decoder, whole district's column decoder, buffer and I/O.

6. storehouse integrated circuit (IC) system as claimed in claim 1, is characterized in that, this functional unit comprises CPU (CPU), Graphics Processing Unit (GPU), heat-sink unit or basic input/output system (BIOS).

7. storehouse integrated circuit (IC) system as claimed in claim 1, is characterized in that, this first chip has online layer within first number of plies and the second chip has within second number of plies online layer and this ground floor number system is less than this second number of plies.

8. storehouse integrated circuit (IC) system as claimed in claim 1, is characterized in that, the size of this first chip is greater than the size of this second chip.

9. a storehouse integrated circuit (IC) system, comprises:

The first chip, has memory cell;

The second chip, has the first of the logical circuit that this memory cell uses;

The 3rd chip, has the second portion of the logical circuit that this memory cell uses; And

Plural number silicon perforation, is arranged in this first chip, the second chip examines to be electrically connected to this first chip, this second chip and the 3rd chip with one of the 3rd chip,

Wherein this memory cell of this first chip, this second portion of the first of this logical circuit of this second chip and this logical circuit of the 3rd chip be designed to jointly use to reach complete memory function.

10. a storehouse integrated circuit (IC) system, comprises:

The first chip, only comprises analog circuit;

The second chip, only comprises digital circuit; And

Plural number silicon perforation, be arranged in this first chip with the one of the second chip to be electrically connected to this first chip and this second chip,

Wherein this analog circuit of this first chip and this digital circuit of this second chip are designed to jointly use to reach complete function.