KR102237739B1 - Dynamic random access memory having three-dimensional vertical cell structure - Google Patents

Abstract

A DRAM having a three-dimensional vertical cell structure has a three-dimensional structure in which memory cells are vertically stacked by repeating unit processes. The memory cells can be implemented vertically as N (N is a natural number of 2 or more) layers. In a 3D DRAM, a large annular capacitor for each layer surrounds a corresponding transistor, or a large number of small capacitors for each layer are arranged in an annular shape around a corresponding transistor, thereby effectively implementing a 3D vertical structure of the DRAM.

Description

DRAM with three-dimensional vertical cell structure {Dynamic random access memory having three-dimensional vertical cell structure}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a DRAM (dynamic random access memory) having a three-dimensional vertical cell structure.

Recently, the difficulty of micro-processing to reduce the size of DRAM is approaching its limit. In particular, the DRAM is more difficult to overcome the limitations of the process due to the capacitor included in the memory cell.

An object of the present invention for solving the above problems is to provide a DRAM in which the degree of integration is improved, the occupied area is reduced, and the memory capacity can be increased.

In order to achieve the above object, a DRAM having a three-dimensional vertical cell structure according to embodiments of the present invention has a three-dimensional structure in which memory cells are vertically stacked by repeating unit processes. The memory cells can be implemented vertically as N (N is a natural number of 2 or more) layers.

In order to achieve the above object, a DRAM (dynamic random access memory) according to embodiments of the present invention includes a plurality of cell groups repeatedly arranged in a horizontal direction, and each of the plurality of cell groups, It includes a plurality of memory cells stacked in a vertical direction. The plurality of memory cells include a plurality of transistors stacked in the vertical direction and a plurality of cell capacitors formed around each of the plurality of transistors and stacked in the vertical direction.

In one embodiment, each of the plurality of cell groups includes a central portion formed by stacking the plurality of transistors in the vertical direction and a peripheral portion surrounding the central portion in which the plurality of cell capacitors are stacked in the vertical direction. Can include.

In one embodiment, the central portion may have a cylindrical shape.

In an embodiment, each of the plurality of cell capacitors may be formed in a ring shape so as to surround each of the plurality of transistors formed in the center in an annular shape.

In one embodiment, each of the plurality of cell capacitors may include a plurality of capacitors in which each of the plurality of transistors formed in the center portion is arranged in an annular shape.

In an embodiment, each of the plurality of transistors includes two active regions disposed in the vertical direction, a substrate region disposed between the two active regions, and a ring-shaped word line surrounding the substrate region. It may include.

In an embodiment, each bit line may be electrically connected to one of the two active regions, and each of the plurality of cell capacitors may be electrically connected to the other of the two active regions.

In an embodiment, peripheral circuits stacked in the vertical direction may be further included.

In the DRAM according to the embodiments of the present invention, the area occupied by the DRAM may be reduced by stacking memory cells in a vertical direction. In other words, the DRAM according to the embodiments of the present invention may increase the number of memory cells per unit area.

In addition, in the three-dimensional DRAM according to the embodiments of the present invention, a large annular capacitor for each layer surrounds the corresponding transistor, or a large number of small capacitors for each layer are arranged in an annular shape around the corresponding transistor. Can be implemented efficiently.

1 is a diagram showing a DRAM having a two-dimensional cell structure.
2 to 5 are diagrams illustrating an example of a vertical structure of a DRAM cell.
6 is a diagram illustrating a vertical structure of a DRAM cell including an annular capacitor surrounding a transistor according to example embodiments.
7 is a diagram illustrating a vertical structure of a DRAM cell including a plurality of capacitors formed around a transistor according to example embodiments.
8 is a diagram illustrating a plurality of capacitors formed around a transistor of a DRAM cell.
9 is a diagram illustrating a cell-to-cell interface and patterning of lines according to embodiments of the present invention.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions have been exemplified for the purpose of describing the embodiments of the present invention only, and the embodiments of the present invention may be implemented in various forms. It is not to be construed as being limited to the embodiments described in.

Since the present invention can be modified in various ways and has various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific form disclosed, it should be understood to include all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as "comprise" or "have" are intended to designate that the described feature, number, step, action, component, part, or combination thereof is present, but one or more other features or numbers It is to be understood that the possibility of addition or presence of, steps, actions, components, parts, or combinations thereof is not preliminarily excluded.

Unless otherwise defined, all terms used herein including technical or scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in the present application. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions for the same elements are omitted.

1 is a diagram showing a DRAM having a two-dimensional cell structure.

As shown in FIG. 1, in general, each DRAM cell includes one transistor and one capacitor, and is formed in a two-dimensional structure on a semiconductor substrate. The cell capacitor should be reduced smoothly due to the shrinking of the horizontal microprocessing of the two-dimensional DRAM cell, but in order to satisfy the appropriate capacity of the cell capacitance such as Cb/Cs within the limited area of the memory cell, Instead of shrinking in size, you need to increase the vertical height. Due to process limitations, there is a difficulty such as tilting the vertical shape of the cell capacitor.

2 to 5 are diagrams illustrating an example of a vertical structure of a DRAM cell.

In the structures shown in FIGS. 2 and 3, a capacitor is formed on the top layer of the DRAM cell. Since each DRAM cell must include one transistor and one capacitor, in the case of FIGS. 2 and 3, any number of DRAM cells cannot be efficiently formed in the vertical direction.

In the structures of FIGS. 4 and 5, a horizontal parallel connection of capacitors is attempted through a structure in which the gate corresponding to the word line WL is horizontally removed to form a silicon on insulator (SOI), thereby limiting the limitations of FIGS. 2 and 3. It is solving horizontally. However, even in the structures of FIGS. 4 and 5, an arbitrary number of DRAM cells cannot be efficiently formed in the vertical direction.

6 is a diagram illustrating a vertical structure of a DRAM cell including an annular capacitor surrounding a transistor according to example embodiments. 7 is a diagram illustrating a vertical structure of a DRAM cell including a plurality of capacitors formed around a transistor according to example embodiments. 8 is a diagram illustrating a plurality of capacitors formed around a transistor of a DRAM cell. 9 is a diagram illustrating a cell-to-cell interface and patterning of lines according to embodiments of the present invention.

6 to 9, the DRAM according to the embodiments of the present invention has a three-dimensional vertical cell structure. That is, the DRAM according to the embodiments of the present invention has a three-dimensional structure in which memory cells are vertically stacked by repeating unit processes. The memory cells can be implemented vertically as N (N is a natural number of 2 or more) layers. 6 illustrates one group of DRAM memory cells stacked in the vertical direction, that is, in the Z direction. As shown in FIG. 8, such a plurality of cell groups may be repeatedly formed in the horizontal direction, that is, in the X direction and the Y direction.

6 and 7 illustrate one cell group.

6 and 7, a cell group includes a plurality of memory cells stacked in a vertical direction. The plurality of memory cells include a plurality of transistors stacked in the vertical direction and a plurality of cell capacitors formed around each of the plurality of transistors and stacked in the vertical direction. One transistor and one cell capacitor form one DRAM cell.

Transistors of DRAM cells stacked in a vertical direction may be stacked to form a central cylinder. The cylinder may be circular, or may be a cylinder of any shape, such as a square or a pentagon. Cell capacitors are formed by being stacked in a vertical direction at a peripheral portion surrounding the center.

Each transistor has a ring shape surrounding two active regions (N+) arranged in a vertical direction, a substrate region (P-sub) disposed between the two active regions (N+), and a substrate region (P-sub) Includes the word line WL of. The method of claim 6, wherein, as shown in FIGS. 6 and 7, for each DRAM cell, each bit line BL is electrically connected to one of two active regions N+, and two active regions are Each cell capacitor is electrically connected to the other one of the regions N+.

In one embodiment, the cell capacitor of each DRAM cell may be formed such that one or more large annular capacitors having a large capacitance are layer-by-layer wrapped around a corresponding transistor in the cylinder, as shown in FIG. 6.

In another embodiment, the capacitor of each DRAM cell is formed by densely arranged annularly so that a large number of capacitors having a small capacitance are arranged layer by layer to surround a corresponding transistor in the cylinder, as shown in FIGS. 7 and 8. I can.

In FIGS. 6 to 9, the arrangement and connection of the word line WL and the bit line BL are simplified and expressed, but various embodiments may be implemented according to the product as the arrangement and connection method of such lines.

On the other hand, peripheral circuits due to the three-dimensional vertical structure of the DRAM cell array, for example, components other than cells and cores, such as logic, circuits, input/output, decap, etc., that is, peripheral circuits can also be vertically stacked.

As described above, in the DRAM according to embodiments of the present invention, the area occupied by the DRAM may be reduced by stacking the memory cells in a vertical direction. In other words, the DRAM according to the embodiments of the present invention may increase the number of memory cells per unit area. In addition, in the three-dimensional DRAM according to the embodiments of the present invention, a large annular capacitor for each layer surrounds the corresponding transistor, or a large number of small capacitors for each layer are arranged in an annular shape around the corresponding transistor. Can be implemented efficiently.

According to the embodiments of the present invention, a three-dimensional DRAM cell structure may be usefully used in various devices and systems. In particular, embodiments of the present invention include a memory card, a solid state drive (SSD), a computer, a laptop, a cellular, a smart phone, an MP3 player, and a personal digital device. It can be more usefully applied to electronic devices such as Assistants (PDA), Portable Multimedia Player (PMP), digital TV, digital camera, and portable game console.

In the above, the present invention has been described with reference to preferred embodiments, but those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention.

Claims (8)

Includes a plurality of cell groups repeatedly arranged in a horizontal direction,
Each of the plurality of cell groups includes a plurality of memory cells stacked in a vertical direction,
The plurality of memory cells,
A plurality of transistors stacked in the vertical direction; And
A plurality of cell capacitors formed around each of the plurality of transistors and stacked in the vertical direction,
Each of the plurality of cell groups,
A central portion formed by stacking the plurality of transistors in the vertical direction; And
A DRAM (dynamic random access memory) including a peripheral portion surrounding the central portion and formed by stacking the plurality of cell capacitors in the vertical direction. delete The method of claim 1,
The central portion of the DRAM, characterized in that forming a cylinder shape. The method of claim 1,
Each of the plurality of cell capacitors,
A DRAM, characterized in that it is formed in a ring shape so as to surround each of the plurality of transistors formed in the center in a ring shape. The method of claim 1,
Each of the plurality of cell capacitors,
And a plurality of capacitors arranged in an annular shape, each of the plurality of transistors formed in the center. The method of claim 1,
Each of the plurality of transistors,
Two active regions disposed in the vertical direction;
A substrate region disposed between the two active regions; And
And a ring-shaped word line surrounding the substrate area. The method of claim 6,
Each bit line is electrically connected to one of the two active regions,
And each of the plurality of cell capacitors is electrically connected to the other one of the two active regions. The method of claim 1,
The DRAM, further comprising peripheral circuits stacked in the vertical direction.

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