TW202002415A - 一體式模製ｕｓｂ裝置 - Google Patents

一體式模製ｕｓｂ裝置 Download PDF

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TW202002415A
TW202002415A TW108105040A TW108105040A TW202002415A TW 202002415 A TW202002415 A TW 202002415A TW 108105040 A TW108105040 A TW 108105040A TW 108105040 A TW108105040 A TW 108105040A TW 202002415 A TW202002415 A TW 202002415A
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usb device
semiconductor device
usb
housing
semiconductor
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TW108105040A
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TWI727262B (zh
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坤源 鄭
普拉迪波 庫馬 萊
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美商西方數位科技公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
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    • H01R13/502—Bases; Cases composed of different pieces
    • H01R13/504—Bases; Cases composed of different pieces different pieces being moulded, cemented, welded, e.g. ultrasonic, or swaged together
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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    • H01L21/561—Batch processing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
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    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07732—Physical layout of the record carrier the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks
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Abstract

揭示一種USB裝置及其形成方法。該USB裝置包括一半導體裝置(諸如，一SIP模組)及圍繞該半導體裝置射出成型之一外殼。

Description

一體式模製USB裝置
對可攜式消費性電子產品之需求的強勁增長帶動了對高容量儲存裝置的需求。非揮發性半導體記憶體裝置(諸如快閃記憶體儲存卡)變得被廣泛使用，以滿足對於數位資訊儲存及交換日益增長的需求。此種記憶體裝置的可攜性、多功能性、及耐用設計，連同其高可靠性及大儲存容量，已使得此種記憶體裝置理想地使用在各式各樣的電子裝置中，其包括(例如)數位相機、數位音樂播放器、視訊遊戲主控臺、PDA、及手機。
同樣普遍的是用於在裝置(諸如上述該等裝置與其他組件，諸如(例如)桌上型電腦及類似者)之間傳遞信號的通用串列匯流排(universal serial bus,USB)介面。一般的USB儲存裝置包括一記憶體裝置，諸如一耦接至能夠在主機裝置的USB插槽內相配之USB連接器的系統級封裝(system in a package,SIP)。SIP模組一般包括一印刷電路板，此電路板上安裝一或多個快閃記憶體晶片、一控制器、及多個被動組件，且有時亦裝有用於指示記憶體正被存取的LED。
習知地，一USB儲存裝置係藉由將各SIP模組或其他記憶體裝置手動插入一外殼中所製造。此外殼常可包含一覆蓋記憶體裝置之背端的內部塑膠外殼及一覆蓋記憶體裝置之前端的金屬外殼。此等手動組裝步驟降低生產量並增加操作成本。
100‧‧‧SIP模組
102‧‧‧基材
104‧‧‧通孔
106‧‧‧電跡線/跡線
108‧‧‧接觸焊墊
110‧‧‧連接器引腳/引腳
120‧‧‧被動組件
130‧‧‧快閃記憶體晶粒/記憶體晶粒/晶粒
136‧‧‧控制器晶粒/晶粒
138‧‧‧打線接合
140‧‧‧模製化合物
144‧‧‧缺口
150‧‧‧USB裝置
152‧‧‧模製外殼/外殼
158‧‧‧前凸緣
160‧‧‧後壁
162‧‧‧基底
164‧‧‧頂部接合表面
166‧‧‧凹陷
170‧‧‧上模板/板
172‧‧‧下模板/板
176‧‧‧坯料
178‧‧‧塊引腳
180‧‧‧板
198‧‧‧板
200‧‧‧步驟
202‧‧‧步驟
208‧‧‧步驟
220‧‧‧步驟
224‧‧‧步驟
226‧‧‧步驟
228‧‧‧步驟
230‧‧‧步驟
232‧‧‧步驟
234‧‧‧步驟
240‧‧‧步驟
244‧‧‧步驟
250‧‧‧步驟
252‧‧‧步驟
260‧‧‧上模板
262‧‧‧下模板
264‧‧‧上蓋
266‧‧‧下蓋
圖1係根據本技術的實施例之USB裝置製程的流程圖。
圖2係根據本發明的實施例之半導體裝置製程的流程圖。
圖3係根據本技術的實施例之半導體裝置在製造期間的俯視圖。
圖4係根據本技術的實施例之半導體裝置的仰視圖。
圖5係根據本技術的實施例之半導體裝置的邊視圖。
圖6係根據本技術的實施例之半導體裝置的透視圖。
圖7係根據本技術的實施例之一包含一包封在外殼內的半導體裝置之USB裝置的透視圖。
圖8係根據本技術的實施例之一包含一包封在外殼內、以虛線顯示的半導體裝置之USB裝置的透視圖。
圖9係根據本技術的實施例之一包含一包封在外殼內的半導體裝置的USB裝置的截面邊視圖。
圖10係根據本技術的實施例之一用於包封半導體裝置之模具的分解邊視圖。
圖11係包括一經包封半導體晶粒及一坯料之一USB裝置的透視圖。
圖12係製造在一板上之複數個USB裝置的透視圖。
圖13係本技術之進一步實施例的分解透視圖，其中將一SIP模組包封在一模製頂蓋及一底蓋中以根據SD卡標準形成一半導體裝置。
現在將參照關於一體式模製USB裝置的圖式來描述實施例。該USB裝置可包括一記憶體裝置，諸如一模製至一保護外殼中的SIP模組。多個記憶體裝置可一起模製在一板中，然後單切以達到規模經濟。應當理解的是，本技術可以許多不同形式體現且不應被解讀為限於本文所提出之實施例。而是，提供這些實施例，使得本揭露將徹底且完整，且將充分地傳達本發明給所屬技術領域中具有通常知識者。實際上，本發明意圖涵蓋可包括在如隨附申請專利範圍所定義之本發明之精神及範疇內的這些實施例的替代例、修改例及均等例。此外，在下文本發明之詳細描述中，闡述許多具體細節以便提供對本發明之徹底理解。然而，所屬技術領域中具有通常知識者將顯而易見，本發明可在沒有此類具體細節的情況中予以實踐。
本文使用的用語「頂部(top)」與「底部(bottom)」、「上(upper)」與「下(lower)」、及「垂直(vertical)」與「水平(horizontal)」及其形式僅作為實例及說明之目的，且由於所指稱的項目能在位置及定向上交換，因而並未意圖限制技術的描述。另外，如 本文所使用，用語「實質上(substantially)」及/或「約(about)」代表指定的尺寸或參數可在一給定應用的可接受製造公差內變化。在一個實施例中，可接受製造公差係一給定尺寸的±.25%。
現在將參照圖1及圖2的流程圖及圖3至圖12的視圖來解釋本技術之一實施例。起初，參考圖1的流程圖，一記憶體裝置(諸如一SIP模組)可在步驟200中形成。步驟200的進一步細節顯示於圖2的流程圖及展示SIP模組100之圖3及圖4的俯視圖及仰視圖中。SIP模組100可連同一基材板上的複數個其他模組100經批次處理以達到規模經濟。模組100在該基材板上的列及行數可變化。
該基材板始於複數個基材102(同樣地，圖3及圖4展示一個此種基材)。基材102可係各種不同的晶片載體介質，包括印刷電路板(printed circuit board,PCB)、引線框架、或捲帶式自動接合(tape automated bonded,TAB)帶。其中基材102係一PCB，該基材可由具有一頂部導電層及一底部導電層之一芯材所形成。該芯材可由各種介電材料形成，諸如(例如)聚醯亞胺層壓體、包括FR4及FR5的環氧樹脂、雙馬來亞醯胺三
Figure 108105040-A0202-12-0004-14
(bismaleimide triazine,BT)、及類似者。圍繞芯材的導電層可由銅或銅合金、鍍銅或鍍銅合金、鍍銅鋼、或已知使用在基材板上的其他金屬及材料所形成。
在步驟220中，將通孔、引線、及焊墊的導電圖案形成在基材102中並通過該基材。可對基材102鑽孔以界定通孔104，該等通孔隨後以一導電金屬電鍍及/或填充。接著可形成電跡線106及接觸焊墊108的導電圖案。所示通孔、104、跡線106、及接觸焊墊108 僅係作為實例，且基材102可包括比圖式所示更多的通孔、跡線、及/或接觸焊墊，且彼等可位在與圖式所示不同的位置。基材102的頂部表面及/或底部表面上的導電圖案可藉由各種已知製程形成，包括例如各種微影蝕刻製程。
SIP模組100進一步包括一USB連接器，在實施例中，其可形成於基材102的下表面上。因此，在實施例中，導電圖案也可界定連接器引腳110，如圖4的仰視圖所示。替代地，應當理解的是，連接器引腳110可獨立於基材102而形成，再於之後安裝在基材102上。包括SIP模組100的該USB裝置可經組態以根據各種USB標準之任何者操作，其可決定引腳110的數目及位置。在進一步實施例中，引腳110可經提供於基材102的二個表面上。
再次參考圖2，接下來可在步驟224中檢查基材102。此步驟可包括一自動光學檢查(automatic optical inspection,AOI)。一旦檢查過後，可在步驟226中將一焊料遮罩施加至該基材上。在施加該焊料遮罩後，接觸焊墊及待焊接至導電圖案上的任何其他區域可在步驟238中於一已知的電鍍或薄膜沉積製程中使用例如，Ni/Au、合金42、或類似者予以電鍍。接著，基材102可在步驟230中進行操作測試。在步驟232中，可視覺檢查該基材，包括(例如)一自動視覺檢查(automated visual inspection,AVI)及一最終視覺檢查(final visual inspection,FVI)以檢查污染、刮痕、及變色。此等步驟的一或多者可經省略或以不同順序執行。
假設基材102通過檢查，接下來可在步驟234中將被動組件120固著至基材102的頂部表面，如圖3所示。可採用在已知的表面安裝及回流製程中連接接觸焊墊(未圖示)之方式將一或多個被動組件120安裝在基材102上並電耦接至導電圖案。該等被動組件120可包括，例如，一或多個電容器、電阻器、及/或電感器，但其他組件亦在設想之內。LED也可在一回流製程期間經安裝至基材並永久固定。LED可在USB快閃記憶體裝置的使用期間存取下文描述的快閃記憶體時啟動。
參考圖3的俯視圖，接下來可在步驟240中將一或多個半導體晶粒固著至基材102的頂部表面。圖3的實施例包括一快閃記憶體晶粒130及一控制器晶粒136。記憶體晶粒130可係例如快閃記憶體晶片，諸如2D NOR或NAND半導體晶粒或3D BiCS(Bit Cost Scaling，位元成本縮放)半導體晶粒，但其他類型之記憶體晶粒亦在設想之內。控制器晶片136可，例如，係ASIC。圖3顯示安裝在基材102上的一對記憶體晶粒130及一控制器晶粒。然而，記憶體晶粒的數目及控制器晶粒的位置可在進一步實施例中變化。
在晶粒130及晶粒136已安裝在基材上之後，晶粒可在步驟244中，例如，經由打線接合138電耦接至基材。應當理解的是，晶粒130及/或晶粒136可藉由其他電互連件(包括，例如，穿矽通孔)安裝至基材上。
在實施例中，在晶粒130、136耦接至基材102後，可在步驟250中將基材及晶粒封裝在模製化合物140(圖5)中以形成完 整的SIP模組100。雖然對本發明並不重要，但模製化合物140可係環氧樹脂，諸如(例如)可購自Sumito Corp.或Nitto Denko Corp.，二者皆在日本設有總部。來自其他製造商的其他模製化合物亦在設想之內。模製化合物可根據各種製程施加，包括藉由FFT(flow free thin，無流動薄)模製、轉移模製、或射出成型技術。在實施例中，經封裝的SIP模組100可具有小於1mm之厚度。
可使連接器引腳110保持未覆蓋及暴露，使得彼等可與一主機裝置中的端子相配。此外，如在圖6中所見，可將一缺口144形成在模製化合物140中。如下文所解釋，該缺口用於將SIP模組鎖定在一模製外殼內。雖然以上描述係關於一SIP模組的形成，應當理解的是，在本技術的進一步實施例中，可將除SIP模組以外的半導體裝置及資料儲存裝置包封在外殼內。
如所述的，SIP模組100可在一含有數個SIP模組100的板上製造，以實現規模經濟。在板上的SIP模組100已於步驟250中封裝之後，各別裝置可在步驟252中從板上單切下來，以形成顯示在圖5及圖6之邊視圖及透視圖中的成品SIP模組100。各模組100可藉由各種切割方法之任何者單切，包括鋸、水刀切割、雷射切割、水引導雷射切割、乾介質切割、及鑽石塗布線切割。雖然直線切割將界定大致為矩形或正方形的模組100，應當理解的是，在本發明的進一步實施例中，模組100可具有除矩形及正方形以外的形狀。
再次參考圖1，在SIP模組100在步驟200中形成之後，可在步驟202中將SIP模組100包封在一外殼中以形成一完整的 USB裝置。圖7、圖8、及圖9分別顯示一包括一包封在外殼152內之SIP模組的完整USB裝置150之透視圖、虛線透視圖、及截面圖。如圖所示，模製外殼152在複數個點接合該SIP模組，以便將SIP模組100固定在外殼152內。例如，當作為液體射出時，模製化合物將流入並填充缺口144。當模製化合物固化時，此接合將使SIP模組100與外殼150牢牢固定。另外，如在圖8及圖9之範例所見，外殼152包括前後包夾SIP模組100的前凸緣158與後壁160，及上下包夾SIP模組100的基底162與頂部接合表面164。
除了將SIP模組100鎖定在外殼內以外，後壁160提供一方便的手指握持件，使USB裝置150能輕易地插入一主機裝置USB插槽及從中移除。前凸緣158也可在USB裝置150插入一主機裝置USB插槽時保護SIP模組100免於損壞。至少一些USB標準界定形成在USB裝置之上表面及/或下表面中的一對凹陷部分。在形成外殼152時，此凹陷部分166可按適用之USB標準形成在外殼152中。
在實施例中，外殼152可圍繞SIP模組100射出成型。如圖10所示意地顯示的，可將SIP模組100設置在包含上模板170及下模板172的模具中，該上模板及下模板在密封模具時一起靠合在該SIP模組周圍。模板170及模板172可一起界定一模穴，該模穴包括呈成品外殼152形狀之輪廓及特徵。可將各種熱塑性樹脂或熱固性聚合物之任何者用於外殼152，諸如(例如)聚碳酸酯、或聚碳酸酯-丙 烯腈-丁二烯-苯乙烯聚合物(PC ABS)摻合物。在進一步實施例中可使用其他材料。
模製化合物可在壓力下以液體形式射出至包括SIP模組的模具中，使得該模製化合物填充模具內之SIP模組100周圍的所有空間。接著，該模製化合物硬化成外殼152，並可從模具中移除。雖然圖式顯示外殼152的一特定組態，應當理解的是，外殼152在進一步實施例中可具有其他外觀，同時保持本文描述之功能及特徵。
USB裝置包括位在連接器引腳上方的一空間，該空間用於在一主機裝置USB插槽中與一引腳塊相配。為了在USB裝置150中提供此空間，也可將坯料176提供在模具內的SIP模組100的表面上，如圖10及圖11所示。SIP模組100上的引腳110有可能凹陷至SIP模組100的表面中。為確保在射出成型製程期間沒有液體模製化合物遷移至引腳110上，坯料可包括與USB引腳110之圖案及形狀匹配的塊引腳178之圖案。在模製製程期間，塊引腳178設置在USB引腳110的頂部上，以保持彼等不接觸到模製化合物。一旦模製化合物硬化並將USB裝置從模具移除，可移除坯料176以在SIP模組100上方界定一中空空間。在進一步實施例中，坯料176可係模具的一部分。
再次參考圖1，一旦形成包括模製外殼152的USB裝置150，可在步驟208中以商標、印記、或其他圖形列印外殼152。在一些實施例中，可能所欲的是在外殼152的至少一些部分上具有一外部電連接器，例如用於接地及靜電放電。在此種實施例中，一金屬 或其他導電體可經施加在USB裝置150的部分上方。此類導電體可藉由薄膜沉積技術(諸如，物理氣相沉積)施加。若施加此類導電體，其可在列印外殼的步驟208之前或之後施加。
在實施例中，USB裝置150可個別製造。此種實施例藉由減少處理步驟的數目及改善處理速度及生產量而提供優於習知USB製程的改善。在本技術的進一步實施例中，USB裝置150可在多個USB裝置150的板上製造。除了減少處理步驟外，此實施例藉由提供規模經濟來提供優於習知USB製程的更大改善。
圖12顯示多個USB裝置150在板198上製造的實施例。包括板170及板172的模具可包括用於多個USB裝置150的空穴。可將多個SIP模組100置於彼等的各自空穴中，然後與外殼152一起射出成型。一旦從模具移除，可將個別USB裝置150從板180切離或以其他方式從該板分離。
在上述實施例中，SIP模組100係包封在一根據USB標準所組態的外殼內。應當理解的是，SIP模組100可包封在一根據其他標準所組態的外殼內。例如，圖13係一顯示可放置在包括上模板260及下模板262之模具中的SIP模組100的分解透視圖。模板可閉合在一起，接著可將各種熱塑性樹脂或熱固性聚合物(例如上述該等)的任何者射出至模具中。接著該射出材料可硬化以形成上蓋264及下蓋266。在此實施例中，上蓋264及下蓋266一起符合SD卡標準。在此實施例中，SIP 100可使用符合用於一SD卡中之SIP的一形 狀及數個接觸焊墊形成。應當理解的是，符合其他標準的半導體裝置可類似地藉由模製圍繞其他SIP模組的外殼形成。
總之，本技術的一實施例係關於一種USB裝置，其包括：一半導體裝置；一外殼，其圍繞該半導體裝置模製，使得該半導體裝置包封在該外殼內，該外殼包含位在該半導體裝置上方的一空間，該空間經組態以允許將該USB裝置插入一USB裝置主機插槽中。
在另一實例中，本技術係關於一種USB裝置，其包括：一包含複數個連接器引腳之半導體裝置；一圍繞該半導體裝置射出成型之外殼，該外殼在複數個點接合該半導體裝置使得該半導體裝置固定在該外殼內，該外殼包含位在該複數個連接器引腳上方的一空間，該空間經組態以允許將該USB裝置插入一USB裝置主機插槽中。
在一進一步實例中，本技術係關於一種製造USB裝置的方法，其包含：(a)將複數個半導體裝置置於一模具中；(b)將該複數個半導體裝置包封在一模製化合物中，該模製化合物包含位在該複數個半導體裝置之各者上方的一空間；及(c)將已包封的該複數個半導體裝置分開成個別的USB裝置。
在另一實例中，本技術係關於一種USB裝置，其包括：一用於儲存資料之半導體裝置構件；外殼構件，其用於包封該半導體裝置使得該半導體裝置包封在該外殼內，該外殼構件包含位在該 半導體裝置上方的一空間，該空間經組態以允許將該USB裝置插入一USB裝置主機插槽中。
已為了闡釋及描述之目的提出本發明之上述詳細描述。此非意圖窮舉或使本發明限於本文列舉之精確形式。鑑於上述教導，許多修改及變化係可行的。所描述之實施例經選取以最佳解說本發明之原理及其實務應用，以藉此使所屬技術領域中具有通常知識者最佳在各項實施例中利用本發明，並且設想適合特定用述的各種修改。意圖本發明之範疇由隨附申請專利範圍定義。
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Claims (20)

  1. 一種USB裝置，其包括：一半導體裝置；一外殼，其圍繞該半導體裝置模製，使得該半導體裝置包封在該外殼內，該外殼包含位在該半導體裝置上方的一空間，該空間經組態以允許將該USB裝置插入一USB裝置主機插槽中。
  2. 如請求項1之USB裝置，其中該外殼包括用於在一第一方向上約束該半導體裝置的一凸緣及一後壁。
  3. 如請求項2之USB裝置，其中該外殼包括用於在與該第一方向正交之一第二方向上約束該半導體裝置的一基底及支撐表面。
  4. 如請求項2之USB裝置，其中該後壁經進一步組態以供握持，用於將該USB裝置插入該USB裝置主機插槽中及將該USB裝置從該USB裝置主機插槽移除。
  5. 如請求項1之USB裝置，其中該半導體裝置包括一缺口，且其中該外殼接合在該缺口內以用於將該半導體裝置約束在該外殼內。
  6. 如請求項1之USB裝置，其中該外殼係由塑膠形成。
  7. 如請求項1之USB裝置，其中該外殼係由聚碳酸酯-丙烯腈-丁二烯-苯乙烯聚合物摻合物形成。
  8. 如請求項1之USB裝置，其進一步包含施加至該外殼之一外表面的一導電體。
  9. 一種USB裝置，其包括：一包含複數個連接器引腳之半導體裝置； 一圍繞該半導體裝置射出成型之外殼，該外殼在複數個點接合該半導體裝置使得該半導體裝置固定在該外殼內，該外殼包含位在該複數個連接器引腳上方的一空間，該空間經組態以允許將該USB裝置插入一USB裝置主機插槽中。
  10. 如請求項9之USB裝置，其中該複數個點包括用於接合該半導體裝置並在一第一方向上約束該半導體裝置的一凸緣及一後壁。
  11. 如請求項10之USB裝置，其中該複數個點包括用於接合該半導體裝置並在與該第一方向正交之一第二方向上約束該半導體裝置的一基底及支撐表面。
  12. 如請求項10之USB裝置，其中該後壁經進一步組態以供握持，用於將該USB裝置插入該USB裝置主機插槽中及將該USB裝置從該USB裝置主機插槽移除。
  13. 如請求項9之USB裝置，其中該半導體裝置包括一缺口，且其中該複數個點包含填充該缺口以將該半導體裝置約束在該外殼內之該外殼的部分。
  14. 如請求項9之USB裝置，其中該半導體裝置包含一系統級封裝。
  15. 如請求項9之USB裝置，其中該半導體裝置包含複數個記憶體晶粒。
  16. 一種製造USB裝置的方法，其包含：(a)將複數個半導體裝置置於一模具中；(b)將該複數個半導體裝置包封在一模製化合物中，該模製化合物包含位在該複數個半導體裝置之各者上方的一空間；及 (c)將已包封的該複數個半導體裝置分開成個別的USB裝置。
  17. 如請求項16之方法，其進一步包含將一導電體施加至該模製化合物之一外表面以使該等USB裝置電性接地之步驟。
  18. 如請求項16之方法，其中將該複數個半導體裝置包封在一模製化合物中的步驟(b)包含將該模製化合物圍繞該複數個半導體裝置射出至該模具中的步驟。
  19. 如請求項16之方法，其中將該複數個半導體裝置包封在一模製化合物中的步驟(b)包含在複數個點接合該半導體裝置使得該半導體裝置固定在該外殼內之步驟。
  20. 一種USB裝置，其包括：一半導體裝置構件，其用於儲存資料；外殼構件，其用於包封該半導體裝置使得該半導體裝置包封在該外殼內，該外殼構件包含位在該半導體裝置上方的一空間，該空間經組態以允許將該USB裝置插入一USB裝置主機插槽中。
TW108105040A 2018-06-22 2019-02-15 一體式模製ｕｓｂ裝置及其製造方法 TWI727262B (zh)

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