TW201947748A - Boss-shaped avalanche photodetector - Google Patents

Abstract

An avalanche photodetector is provided. The photodetector is a novel avalanche photodiode of indium aluminum arsenide (InAlAs) and is boss-shaped. An epitaxial layer is used, where the cathode electrode is located at a lower side with the avalanche layer at bottom. The strongest electric field of the avalanche layer is coated at the bottom layer to avoid surface from breakdown. The present invention mainly thickens the i-layer. Only one light-absorbing layer is used. A DBR layer is added below the N-type ohmic contact layer. At least five pairs of InGaAsP/InP or InAlGaAs/InAlAs are used for fabrication. The second groove-graded layer is etched to form the boss-shaped photodetector. Through the single-boss-shaped structure, the avalanche layer has a high electric field in the middle while the electric field at edge is low. Limitation to the electric field of the avalanche layer is achieved. At breakdown, all of the layers have far lower electric fields except the avalanche layer has a higher electric field. Thus, the present invention changes secondary holes into secondary electrons through a p-type doping process of the light-absorbing layer. Because the electrons run faster, the carriers also run faster. The junction capacitance is reduced with the surface area increased owing to the thickened depletion layer. Hence, fast response speed is obtained while sensitivity is effectively improved.

Description

Boss accumulating light detector element

The present invention relates to a convex-shaped accumulative photodetector element, in particular to a convex-shaped accumulatively collapsed photodiode, and particularly to a thickened i-essential layer using only one light-absorbing layer (p-type doped) Miscellaneous), and a DBR reflective layer is added under the N-type ohmic contact layer, and a boss shape is etched on the structure. Through this single boss structure, the electric field in the middle of the accumulation layer can be high, and the fringe electric field is low. In order to achieve the effect of the electric field limitation of the accumulating layer, and except that the accumulating layer will crash and make the electric field particularly high, the electric field of all layers will be far lower than the one that breaks down (far below break down).

In order to meet the needs of the Internet of Things (IOT) of larger virtual systems and huge amounts of bit data, traditional copper wires have long been unable to fulfill the heavy task of transmission (≥ ~ 100m), and they can only hope that the transmission bandwidth will still be The bottom-end optical fiber; considering the market size, cost, and technology that can be expected to develop at different transmission distances, the 400GbE Ethernet task force will work out four different distance target transmission interfaces, each 100 m , 500 m, 2 km, and 10 km, of which 400 Gbps at 100 m has almost been determined to continue to use a vertical cavity surface emitting laser (VCSEL @ 25 Gbps per channel in a 100GbE Ethernet network) 850 nm) direct modulation signal is transmitted in multimode fiber (MMF), but the number of lasers and fibers has to be quadrupled to achieve the goal of 400 Gbps. Above 500 m, a 1310 nm light source will be used for transmission in single-mode fiber (SMF). In the current consideration of the 400GbE Ethernet project team, the possible solution includes the signal speed of each single light source. At 50 Gbps or 100 Gbps, eight or four channels (multi-wavelength on a single fiber or single wavelength on multiple fibers) are used to reach 400 Gbps; however, when the speed of a single light source in Ethernet comes > 25 Gbps, the output optical power of the high-bandwidth optoelectronic components (including the electro-optic modulation in the transmitting module and the photoelectric conversion in the receiving module) is usually small (about 1 mW; -2 to +2 dBm) If Wavelength Division Multiplexing (WDM) technology is also used, the insertion loss inside its passive components will make the power budget become the key to limit the maximum transmission capacity of the system. As document one (M. Nada, T. Yoshimatsu, Y. Muramoto, H. Yokoyama, and H. Matsuzaki, "Design and Performance of High-Speed Avalanche Photodiodes for 100-Gb / s Systems and Beyond," IEEE / OSA Journal of Lightwave Technology, vol. 33, no. 5, pp. 984-990, March, 2015.) It is known from the cause of the insertion loss in the system that a sensitivity of about -13 dBm is required at the receiving end of the system. Generally, a receiver consisting of a photodiode of p-i-n has a sensitivity of about -10 dBm or more under a 25 Gbit / sec bandwidth operation. Figure 5 is document two (E. Ishimura, E. Yagyu, M. Nakaji, S. Ihara, K. Yoshiara, T. Aoyagi, Y. Tokuda, and T. Ishikawa, "Degradation Mode Analysis on Highly Reliable Guarding-Free Planar InAlAs Avalanche Photodiodes, "IEEE / OSA Journal of Lightwave Technology, vol. 25, pp. 3686-3693, Dec., 2007.) proposed the accumulation of collapsed photodiodes with planar indium aluminum arsenide (InAlAs) as the accumulation layer Body cross-section structure. As shown in the figure, although the high-field region 3 has a zinc diffusion region to confine the electric field, it does not have a mesa structure, which makes the electric field confinement at the edge part worse. It is easy to exceed the threshold of the collapsed electric field (> 550 kV / cm). When the multiplication layer (M-layer) is thinned, in order to achieve the required operating gain, the edge will crash. Figure 6 shows the cross-sectional structure of the collapsed photodiodes of 25 and 50 Gbit / sec developed by NTT Electronic (ie Document 1) in the past two years. Its structure (from Top to Bottom) consists of an N- N-contact layer 40, an edge-field buffer layer 41, an N-charge layer 42, an indium aluminum arsenide (InAlAs) accumulation layer (Avalanche layer) 43, a P-type charging layer 44, an undoped indium gallium arsenide (InGaAs) absorbing layer 45, a P-type indium gallium arsenide absorbing layer 46, a P-type contact layer 47, half It is composed of an insulating InP substrate 48 and an anti-reflection layer 49. As shown in the figure, in order to achieve a good electric field limitation, this structure is quite special. The indium aluminum arsenide accumulation layer 43 and the N-type contact layer 40 are placed close to the surface of the element (inverted structure). The electric field of the indium-aluminum accumulation layer 43 is mostly limited below the N-type contact layer 40. However, in order to reduce the probability of surface collapse, an extra fringe field buffer layer 41 and an N-type charging layer 42 are needed, but this may be the case. Affects the speed of the component. In addition, the structure of this p-side down structure also needs to use a P-type InP based alloy with a wider energy gap. This will cause difficulties in making ohmic contacts and change the resistance of the entire component. Big. In addition, this structure will sacrifice the electric field limitation in the P-type indium gallium arsenide absorbing layer 46, which may make the parasitic capacitance of the device larger, and also because of the stronger fringe field in the absorbing layer. And increase the difficulty of component packaging (such as reference 3: F. Nakajima, M. Nada, and T. Yoshimatsu “High-Speed Avalanche Photodiode and High-Sensitivity Receiver Optical Sub-Assembly for 100-Gb / s Ethernet,” to be published in IEEE / OSA Journal of Lightwave Technology, vol. 33, 2015.). Therefore, in order to limit the electric field, the document 2 places the accumulating layer outside and exposes it to the air, which will cause reliability problems. From the sensitivity measurement results of the components shown in the literature under 25 Gbit / sec and 50 Gbit / sec operation, it can be clearly seen that the sensitivity of 25 and 50 Gbit / sec is about -15.5 dBm and -11 dBm. Compared with the 25 and 50 GHz optical receiver modules of the pin PD based series, the increased responsivity is about ~ 4 dB and ~ 1.5 dB. From this result, it can be known that as the data rate increases, the sensitivity of the collapsed photodiode structure can be reduced accordingly. This is most likely because the accumulating layer needs to be thinned as the required operating bandwidth increases, but this causes the dark current to rise sharply and cause sensitivity degradation. In view of this, the applicant of this case has previously applied for the light detection element of the Republic of China Patent Certificate No. I595678, which uses the double mesa structure to achieve the effect of the electric field limitation of the accumulating layer; but considering that the hole speed is much slower than The electron velocity causes the holes to easily accumulate in the essential region, forming an electric field shielding effect, which causes the internal electric field to become smaller, so the carrier discharge speed becomes slower, which in turn affects the output power, which causes the element speed to become very slow. Therefore, ordinary users cannot meet the needs of users in actual use.

The main purpose of the present invention is to overcome the above problems encountered in the conventional art and provide an epitaxial layer structure with a cathode electrode underneath, so that the region with the strongest electric field in the accumulating layer is coated on the inner bottom layer of the element to avoid surface breakdown. And using a single boss structure to achieve the effect of the electric field limitation of the accumulating layer, and except that the accumulating layer will crash and make the electric field particularly high, the electric field of all layers will be far lower than the boss that collapses (far below break down) Accumulating light detector element. A secondary object of the present invention is to provide a p-type doping through a light absorbing layer to turn a secondary hole into a secondary electron and utilize the relatively fast characteristic of electron running, so that the speed of the carrier can be made faster. You can use a relatively thick empty area to reduce the junction capacitance and increase the area of the component, so that it has a fast response speed and effectively increase the sensitivity of the bump-like accumulating light detector element. Another object of the present invention is to provide a thickened i-essential layer using only one light absorbing layer and adding a DBR reflective layer under the N-type ohmic contact layer. The material of the DBR reflective layer may be indium phosphorous arsenide At least 5 pairs of gallium / indium phosphide (InGaAsP / InP) or aluminum indium gallium / indium aluminum arsenide (InAlGaAs / InAlAs) can be used to improve the effect of the device. In order to achieve the above object, the present invention is a bump-shaped accumulative photodetector element, which includes: a P-type Ohmic Contact Layer, which is a p ⁺ -type doped first semiconductor; a DBR The reflective layer is a second semiconductor composed of several pairs of InGaAsP / InP or InAlGaAs / InAlAs; a P-type light-transmitting layer (Window layer) is a p ⁺ -type doped third semiconductor and is sandwiched between the P-type Between a type ohmic contact layer and the DBR reflective layer; a first graded bandgap layer, which is a p ⁺ type doped fourth semiconductor, is sandwiched between the P type light transmitting layer and the DBR Between the reflective layers; a P-type light absorption layer (Absorption Layer), which is a graded p-type doped fifth semiconductor, sandwiched between the first grooved graded layer and the DBR reflective layer; a first The two-band groove gradient layer is an undoped sixth semiconductor and is sandwiched between the P-type light absorption layer and the DBR reflection layer; a field buffer layer is an undoped layer A seventh semiconductor, sandwiched between the second grooved gradient layer and the DBR reflective layer; a first P-type electric field control layer ( Field Control Layer) is a p-type doped eighth semiconductor and is sandwiched between the shielding buffer layer and the DBR reflective layer; a second P-type electric field control layer is a p-type doped The ninth semiconductor is sandwiched between the second grooved gradient layer and the DBR reflective layer; a spacer layer is an undoped tenth semiconductor and sandwiched between the second P-type semiconductor Between the electric field control layer and the DBR reflective layer; a multiplication layer (M-Layer), which is an undoped eleventh semiconductor, is sandwiched between the first P-type electric field control layer and the DBR Between reflective layers; an N-type electric field control layer, which is an undoped twelfth semiconductor, sandwiched between the accumulation layer and the DBR reflective layer; an i-essential layer, which is undoped A thirteenth semiconductor is sandwiched between the N-type electric field control layer and the DBR reflective layer; and an N-type ohmic contact layer is an n ⁺ -type doped fourteenth semiconductor and sandwiched Between the i-essential layer and the DBR reflective layer; the structure (from Top to Bottom) of the convex-shaped accumulating light detector element is connected by the aforementioned P-type ohmic connection Layer, P-type light-transmitting layer, first grooved gradient layer, P-type light absorption layer, second grooved gradient layer, shielding buffer layer, first P-type electric field control layer, second P-type electric field control layer, and spacer layer , Accumulating layer, N-type electric field control layer, i-essential layer, N-type ohmic contact layer, and DBR reflective layer, forming the epitaxial layer structure of the cathode (n-side (M-layer) down) electrode, and There is a platform structure between the second P-type electric field control layer and the spacer layer, and the platform structure is used to confine the electric field at the center of the element. In the above embodiments of the present invention, the epitaxial layer structure is grown on a semi-insulating or conductive semiconductor substrate. In the above embodiments of the present invention, the P-type ohmic contact layer is p ⁺ -type indium gallium arsenide (InGaAs), and the P-type light transmitting layer is p ⁺ -type indium phosphide (InP) or indium aluminum arsenide ( InAlAs), the first grooved graded layer is p ⁺ -type InGaAs, the P-type light absorption layer is graded p-type doped InGaAs, the second grooved graded layer is undoped InGaAs, and the masking buffer The layer is undoped InAlAs, the first P-type electric field control layer is p-type InAlAs, the accumulation layer is undoped InAlAs, the i-essential layer is undoped InP or InAlAs, and the The N-type ohmic contact layer is n ⁺ -type InP. In the above embodiments of the present invention, the P-type ohmic contact layer is p ⁺ -type InGaAs, the P-type light-transmitting layer is p ⁺ -type InP or InAlAs, and the first grooved gradient layer is p ⁺ -type InAlAs, The P-type light absorbing layer is a graded p-type doped InGaAs, the second grooved graded layer is undoped InAlAs, the shielding buffer layer is undoped InAlAs, and the first P-type electric field control layer is The p-type InAlAs, the accumulation layer is undoped InAlAs, the i-essential layer is undoped InP or InAlAs, and the N-type ohmic contact layer is n ⁺ -type InP. In the above embodiment of the present invention, the P-type ohmic contact layer is p ⁺ -type In _x Ga _1-x As, and the P-type light absorbing layer is In _x Ga _1-x As with graded grooves, and x is Is 0.53. In the above embodiments of the present invention, the shielding buffer layer is undoped In _x Al _1-x As, the first P-type electric field control layer is p-type In _x Al _1-x As, and the accumulation The layer is undoped In _x Al _1-x As, and x is 0.52. In the above embodiments of the present invention, the accumulation layer may also be a combination of undoped In _x Al _1-x As and In _x1Al1-x1As , and x is 0.52, and x1 is a positive number less than 0.52. In the above embodiment of the present invention, the thickness of the accumulation layer is 176 ± 20 nm. In the above embodiment of the present invention, the DBR reflective layer includes at least five pairs. In the above embodiment of the present invention, the convex-shaped accumulative light-increasing detector element may also be in a state where the DBR reflective layer is omitted.

Please refer to "Figures 1 to 4", which are schematic cross-sectional views of a preferred embodiment of the present invention, two-dimensional electric field distribution simulation of the crash simulation operation of the present invention, and one of the crash simulation operations of the present invention simulation. A schematic diagram of the one-dimensional electric field distribution and a schematic cross-sectional view of another preferred embodiment of the present invention. As shown in the figure: The present invention is a type of convex-shaped accumulating light detector element, and its structure (from Top to Bottom) is composed of a P-type ohmic contact layer 11 and a P-type light transmission layer (Window Layer) 12. A first Graded Bandgap Layer 13, a P-type Absorption Layer 14, a second Banded Gap Layer 15, a Field Buffer Layer 16, a first P Field control layer (field control layer) 17, a second P-type field control layer 18, a spacer layer (19), a multiplication layer (M-Layer) 20, an N-type electric field control layer 21. An i-essential layer 22, an N-type ohmic contact layer 23, and a DBR reflective layer 24 constitute the epitaxial layer structure 1 of the cathode (n-side (M-layer) down) electrode, and A mesa structure is provided between the second P-type electric field control layer 18 and the spacer layer 19, and the electric field is confined at the center of the device by the boss structure. The aforementioned P-type ohmic contact layer 11 is p ⁺ -type doped indium gallium arsenide (InGaAs), which is used as a P-type electrode, and the P-type ohmic contact layer 11 may further include a P-type A metal conductive layer (not shown); wherein the thickness of the P-type ohmic contact layer 11 is between 15 and 60 nm. The P-type light-transmitting layer 12 is p ⁺ -type doped indium phosphide (InP) or indium aluminum arsenide (InAlAs), and is sandwiched between the P-type ohmic contact layer 11 and the DBR reflective layer 24. ; Wherein the thickness of the P-type light-transmitting layer 12 is between 150 and 250 nm. The first grooved graded layer 13 is a multilayer graded p ⁺ -type doped InGaAs or InAlAs, and is sandwiched between the P-type light-transmitting layer 12 and the DBR reflective layer 24; The total thickness of layer 13 is between 15 nm and 25 nm. The P-type light absorption layer 14 is a graded p-type doped InGaAs, and is sandwiched between the first grooved graded layer 13 and the DBR reflection layer 24; wherein the thickness of the P-type light absorption layer 14 is The thinning is 3600 Å. The second grooved graded layer 15 is undoped InGaAs or InAlAs, and is sandwiched between the P-type light absorption layer 14 and the DBR reflective layer 24. The total thickness of the second grooved graded layer 15 is Between 10 nm and 20 nm. The shielding buffer layer 16 is undoped InAlAs, and is sandwiched between the second grooved gradient layer 15 and the DBR reflective layer 24. The thickness of the shielding buffer layer 16 is between 6.5 and 9.5 nm. between. The first P-type electric field control layer 17 is p-type doped InAlAs, and is sandwiched between the shielding buffer layer 16 and the DBR reflective layer 24. The thickness of the first P-type electric field control layer 17 is Between 30 and 50 nm. The second P-type electric field control layer 18 is p-type doped InAlAs and is sandwiched between the second grooved graded layer 15 and the DBR reflective layer 24. The second P-type electric field control layer 18 The thickness is between 30 and 50 nm. The spacer layer 19 is an undoped semiconductor and is sandwiched between the second P-type electric field control layer 18 and the DBR reflective layer 24. The thickness of the spacer layer 19 is between 130 and 190 nm. . The accumulating layer 20 is undoped InAlAs and is sandwiched between the first P-type electric field control layer 17 and the DBR reflective layer 24. The thickness of the accumulating layer 20 is 176 ± 20 nm. The N-type electric field control layer 21 is undoped InAlAs, and is sandwiched between the accumulation layer 20 and the DBR reflection layer 24. The i-essential layer 22 is undoped InP or InAlAs, and is sandwiched between the N-type electric field control layer 21 and the DBR reflective layer 24. The thickness of the i-essential layer 22 is 8000. Å. The N-type ohmic contact layer 23 is n ⁺ -type doped InP, and is sandwiched between the i-essential layer 22 and the DBR reflective layer 24 to serve as an N-type electrode. The contact layer 23 may further include an N-type metal conductive layer (not shown); wherein the thickness of the N-type ohmic contact layer 23 is between 800-1200 nm. The DBR reflective layer 24 is composed of several pairs of indium gallium arsenide / indium phosphide (InGaAsP / InP) or aluminum indium gallium arsenide / indium aluminum arsenide (InAlGaAs / InAlAs), and includes at least five pairs. The epitaxial layer structure 1 of the present invention is grown on a semi-insulating or conductive semiconductor substrate 25. The semiconductor substrate 25 can be made of a compound semiconductor, such as gallium arsenide (GaAs), gallium antimonide (GaSb), InP, or gallium nitride (GaN). ), Or it can be formed by a Group IV semiconductor such as silicon (Si). If so, a new boss-like accumulative light-increasing detector element is constituted by the above-disclosed process. The P-type ohmic contact layer 11 is a p ⁺ -type In _x Ga _1-x As, and the P-type light absorption layer 14 is a graded band In _x Ga _1-x As, and x is 0.53. The shielding buffer layer 16 is undoped In _x Al _1-x As, the first P-type electric field control layer 17 is p-type In _x Al _1-x As, and the accumulation layer 20 is undoped. Of In _x Al _1-x As (energy level = 1.45 eV), and x is 0.52. The accumulation layer 20 may also be a combination of undoped In _x Al _1-x As and In _x1Al1-x1As , and x is 0.52, and x1 is a positive number less than 0.52. The epitaxial layer structure 1 required by the boss-like accumulative photodetector element of the present invention has no limitation on the growth method, and can be any conventional epitaxial growth method and conditions. It is preferred to use molecular beam epitaxy (Molecular Beam Epitaxy, MBE, Metalorganic Chemical Vapor Deposition (MOCVD), or Hydride Vapor Phase Epitaxy (HVPE) and other epitaxial growth methods are formed on the semiconductor substrate 25. Considering the reliability, the present invention adopts the epitaxial layer structure of the cathode electrode underneath, so that the region with the strongest electric field of the accumulating layer 20 is coated on the inner bottom layer of the element to avoid surface breakdown, and is in line with the aforementioned patent (TW I595678) Compared with the second figure, the present invention thickens the i-essential layer 22, moves the other layers down, and omits the original second light absorbing layer, and the first light absorbing layer (the P-type of the invention mentioned herein) The light absorbing layer 14) is slightly thinner, and the thickness is reduced from 3800 Å to 3600 Å, which shortens the overall structure. A DBR reflective layer 24 is further added below the N-type ohmic contact layer 23. The material of this DBR reflective layer 24 may be InGaAsP / InP or InAlGaAs / InAlAs, at least 5 pairs or more, can improve the effect of the device. The advantage is that since the p-type doping through the light absorption layer turns the secondary hole into a secondary electron, and uses the relatively fast electron running characteristic, the speed of the carrier can be made faster, and a thicker one can be used. The empty area (thicken the i-essential layer) to reduce the junction capacitance and increase the component area. In addition, since the electric field at the center of the accumulating layer is high, the present invention uses a single boss structure to achieve the effect of limiting the electric field of the accumulating layer. As shown in Figure 2, this boss structure allows the edge electric field of the accumulation layer to be pushed down to 518 kv, while the edge electric field of the accumulation layer is to be suppressed, the electric field in the middle is high, and the middle is in the boss. Inside the structure, there is 1096 kv, which proves that the gradient of its electric field is very high. This is due to the formation of a boss shape through the second grooved gradient layer. It can be seen from Figure 2 that the electric field has a particularly strong limitation in the middle of the x direction, because the limitation in the middle is good, which can make the electric field at the edge smaller. From Figure 3, it can be seen that the electric field is in the y direction and the electric field is well controlled, so that these layers are only accumulating layers. The electric field here is particularly high, and the i-essential layer can be very flat, far below break down. In other words, in all layers in the y direction, except for the accumulating layer, which will crash and make the electric field particularly high, other layers will not encounter its collapse electric field, and no collapse will occur, which means that the electric field of all layers will be far below break down. In another embodiment, the convex-shaped accumulating light detector element of the present invention may be in a state where the DBR reflective layer is omitted, as shown in FIG. 4. These adopt a cathode electrode under the epitaxial layer structure 1a, and have a boss structure between the second P-type electric field control layer 18 and the spacer layer 19, so that the electric field is limited to the center of the element by the boss structure. It can be known from the above that the present invention is a novel InAlAs accumulative collapse photodiode (APD) structure, which adopts an epitaxial layer structure with a cathode (accumulation layer at the bottom) and an electrode below, so that the electric field of the accumulation layer is the strongest. The inner layer of the element is covered to avoid surface breakdown. The present invention mainly thickens the i-essential layer, uses only one light absorption layer, and adds a DBR reflective layer under the N-type ohmic contact layer. The material of this DBR reflective layer can be InGaAsP / InP or InAlGaAs / InAlAs, at least 5 pairs, and a second grooved gradient layer is used to etch a boss shape. Through this single boss structure, the electric field in the middle of the accumulation layer can be high, and the electric field at the edge is low. In order to achieve the effect of the electric field limitation of the accumulating layer, and except that the accumulating layer will collide and make the electric field particularly high, the electric field of all layers will be far below break down. Therefore, the invention can be applied to the development of high-capacity, long-distance transmission Ethernet with high speed (greater than 25 Gbit / sec) and high linearity cumulative collapse detection photodiode. To sum up, the present invention is a convex-shaped accumulating light detector element, which can effectively improve various conventional defects. The p-type impurity of the light absorbing layer turns the secondary hole into a secondary electron. Faster characteristics, so that the speed of the carrier can be made faster. A thicker empty area can be used to reduce the junction capacitance and increase the component area. It can have a fast response speed and effectively improve the sensitivity, thereby enabling the present invention. The production can be more progressive, more practical, and more in line with the needs of users. It has indeed met the requirements for invention patent applications, and has filed patent applications according to law. However, the above are only the preferred embodiments of the present invention, and the scope of implementation of the present invention cannot be limited by this; therefore, any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the invention specification of the present invention , All should still fall within the scope of the invention patent.

(Part of the invention)

１、１a‧‧‧Epitaxial layer structure

11‧‧‧P-type ohmic contact layer

12‧‧‧P-type light-transmitting layer

13‧‧‧The first grooved gradient layer

14‧‧‧P-type light absorption layer

15‧‧‧ The second grooved gradient layer

16‧‧‧ shielding buffer layer

17‧‧‧The first P-type electric field control layer

18‧‧‧Second P-type electric field control layer

19‧‧‧ spacer

20‧‧‧accumulation layer

21‧‧‧N-type electric field control layer

22‧‧‧i-essential layer

23‧‧‧N-type ohmic contact layer

24‧‧‧ DBR reflective layer

25‧‧‧Semiconductor substrate

(Conventional part)

‧‧‧High electric field area

40‧‧‧N-type contact layer

41‧‧‧ fringe field buffer layer

42‧‧‧N-type charging layer

43‧‧‧Accumulated Indium Aluminum Arsenide

44‧‧‧P-type charging layer

45‧‧‧ undoped indium gallium arsenide absorbing layer

46‧‧‧P-type indium gallium arsenide absorbing layer

47‧‧‧P-type contact layer

48‧‧‧Semi-Insulated InP Substrate

49‧‧‧anti-reflective layer

FIG. 1 is a schematic cross-sectional view of a preferred embodiment of the present invention. FIG. 2 is a schematic diagram of a two-dimensional electric field distribution during a crash operation simulated by the present invention. FIG. 3 is a schematic diagram of one-dimensional electric field distribution during a crash operation according to the present invention. Figure 4 is a schematic cross-sectional view of another preferred embodiment of the present invention. Figure 5 is a schematic cross-sectional view of the conventional InAlAs APD structure. Figure 6 is a schematic cross-sectional view of another conventional InAlAs APD structure.

Claims (10)

A bump-shaped accumulating light detector element includes: a P-type Ohmic Contact Layer, which is a p ⁺ -type doped first semiconductor; a DBR reflective layer, which is composed of several pairs of phosphorus and arsenic A second semiconductor composed of InGaAs / InP or InAlGaAs / InAlAs; a P-type window layer, which is p ⁺ - Type doped third semiconductor, sandwiched between the P-type ohmic contact layer and the DBR reflective layer; a first Graded Bandgap Layer, which is a p ⁺ type doped fourth semiconductor And sandwiched between the P-type light-transmitting layer and the DBR reflective layer; a P-type light absorption layer (Absorption Layer), which is a graded p-type doped fifth semiconductor, and sandwiched between the first semiconductor A grooved graded layer and the DBR reflective layer; a second grooved graded layer, which is an undoped sixth semiconductor, sandwiched between the P-type light absorbing layer and the DBR reflecting layer; a shielding The field buffer layer is a non-doped seventh semiconductor and is sandwiched between the second grooved gradient layer and the DBR reflective layer. A first P-type electric field control layer (Field Control Layer), which is a p-type doped eighth semiconductor, sandwiched between the shielding buffer layer and the DBR reflective layer; a second P-type electric field control Layer, which is a p-type doped ninth semiconductor, and is sandwiched between the second grooved graded layer and the DBR reflective layer; a spacer layer, which is an undoped tenth semiconductor And sandwiched between the second P-type electric field control layer and the DBR reflective layer; a multiplication layer (M-Layer), which is an undoped eleventh semiconductor, sandwiched between A first P-type electric field control layer and the DBR reflective layer; an N-type electric field control layer, which is an undoped twelfth semiconductor, sandwiched between the accumulation layer and the DBR reflective layer; The i-essential layer is an undoped thirteenth semiconductor and is sandwiched between the N-type electric field control layer and the DBR reflective layer; and an N-type ohmic contact layer is n ⁺ -type doped The fourteenth semiconductor is sandwiched between the i-essential layer and the DBR reflective layer; the structure of the convex-shaped accumulating light detector element (from Top to Bottom) is composed of the aforementioned P-type ohmic contact layer, P-type light-transmitting layer, first grooved gradient layer, P-type light absorption layer, second grooved gradient layer, shielding buffer layer, and first P-type electric field control layer , The second P-type electric field control layer, the spacer layer, the accumulation layer, the N-type electric field control layer, the i-essential layer, the N-type ohmic contact layer, and the DBR reflective layer, and become a cathode (n-side (M-layer) down) The epitaxial layer structure of the electrode is below, and there is a mesa structure between the second P-type electric field control layer and the spacer layer, and the electric field is confined at the center of the element by the boss structure. . According to the bump-shaped accumulative photodetector element described in item 1 of the scope of the patent application, the epitaxial layer structure is grown on a semi-insulating or conductive semiconductor substrate. According to the convex-shaped accumulative photodetector element according to item 1 of the scope of patent application, wherein the P-type ohmic contact layer is p ⁺ -type indium gallium arsenide (InGaAs), and the P-type light-transmitting layer is p ⁺ -Type indium phosphide (InP) or indium aluminum arsenide (InAlAs), the first grooved graded layer is p ⁺ -type InGaAs, the p-type light absorption layer is graded p-type doped InGaAs, the second The grooved graded layer is undoped InGaAs, the shielding buffer layer is undoped InAlAs, the first P-type electric field control layer is p-type InAlAs, the accumulation layer is undoped InAlAs, the i -The intrinsic layer is undoped InP or InAlAs, and the N-type ohmic contact layer is n ⁺ -type InP. According to the convex-shaped accumulative photodetector element according to item 1 of the scope of patent application, wherein the P-type ohmic contact layer is p ⁺ -type InGaAs, and the P-type light-transmitting layer is p ⁺ -type InP or InAlAs, The first grooved graded layer is p ⁺ -type InAlAs, the P-type light absorption layer is graded p-type doped InGaAs, the second grooved graded layer is undoped InAlAs, and the shielding buffer layer is not Doped InAlAs, the first P-type electric field control layer is p-type InAlAs, the accumulation layer is undoped InAlAs, the i-essential layer is undoped InP or InAlAs, and the N-type ohm The contact layer is n ⁺ -type InP. The mesa-shaped accumulative photodetector element according to item 3 or 4 of the scope of patent application, wherein the P-type ohmic contact layer is a p ⁺ -type In _x Ga _1-x As and the P-type light absorption layer In _x Ga _1-x As is a graded groove, and x is 0.53. According to the convex-shaped accumulative photodetector element according to item 3 or 4 of the scope of patent application, wherein the shielding buffer layer is undoped In _x Al _1-x As, and the first P-type electric field control layer is The p-type In _x Al _1-x As and the accumulation layer are undoped In _x Al _1-x As, and x is 0.52. According to the bump-shaped accumulative photodetector element according to item 6 of the scope of the patent application, the accumulating layer may also be a combination of undoped In _x Al _1-x As and In _x1Al1-x1As , and x Is 0.52, and x1 is a positive number less than 0.52. According to the convex-shaped accumulative light-detecting element described in item 1 of the scope of patent application, the thickness of the accumulating layer is 176 ± 20 nm. According to the convex-shaped accumulative photodetector element according to item 1 of the scope of patent application, the DBR reflective layer includes at least five pairs. According to the convex-shaped accumulative light-increasing detector element described in item 1 of the scope of the patent application, the convex-shaped accumulative light-emitting detector element may also be in a state where the DBR reflective layer is omitted.