JP7511793B1 - Semiconductor photodetector, optical line terminal, multilevel intensity modulation transmitter/receiver, digital coherent receiver, optical fiber radio system, SPAD sensor system, and lidar device - Google Patents

Abstract

The semiconductor light receiving element (110) of the present disclosure comprises an InP substrate (1), an n-type semiconductor layer (2a) formed on the InP substrate (1), an electron transit layer (3) formed on the n-type semiconductor layer (2a) and having a digital alloy structure, an n-type electric field relaxation layer (12) formed on the electron transit layer (3), a multiplication layer (13) formed on the n-type electric field relaxation layer (12), a p-type electric field relaxation layer (14) formed on the multiplication layer (13), and a light absorption layer (5) formed on the p-type electric field relaxation layer (14).

Description

The present disclosure relates to semiconductor photodetectors, optical line termination devices, multilevel intensity modulation transceivers, digital coherent receivers, optical fiber radio systems, SPAD sensor systems, and lidar devices.

Along with the progress of digital transformation that utilizes digital information, there has been remarkable development of communication networks that communicate digital information with each other and data centers that store and process data. Optical communication is used for communication networks and communication within data centers. In recent years, optical communication has made remarkable progress in increasing speed and capacity. With the development of optical communication, photodiodes (PD) and avalanche photodiodes (APD), which provide high receiving sensitivity, are required as optical communication receivers.

Passive Optical Networks (PONs) are the primary method used in access networks that connect optical communication subscribers. PON systems started with G(E)-PON systems that transmit signals at 1-2 Gbps, and are expected to see an increase in 10G-EPON and XG-PON systems that transmit signals at 10 Gbps. Furthermore, the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) is considering the 50G-PON system, a next-generation high-speed PON system, and it is expected that 50 Gbps-class transmissions will also be put to practical use in access networks in the future.

The APD, a semiconductor light receiving element used in PON systems, has an element structure consisting of a light absorption layer (InGaAs), an electric field relaxation layer (InP or InAlAs), and a multiplication layer (InP or InAlAs). A high electric field of about 800 kV/cm is applied to the multiplication layer to multiply, or ionize, the electrons and holes generated in the light absorption layer. The electric field relaxation layer functions to weaken the electric field so that the high electric field of the multiplication layer is not applied to the light absorption layer. Incidentally, the ionization rate of electrons is expressed as α, and the ionization rate of holes as β.

In an APD, the greater the ratio of the ionization rates of electrons and holes, the smaller the excess noise generated during multiplication and the higher the receiving sensitivity. Furthermore, the greater the ratio of the ionization rates of electrons and holes, the shorter the multiplication time in the multiplication layer, resulting in a wider bandwidth.

The ionization rate ratio k of electrons and holes is defined as k = β/α. When electrons are injected into the multiplication layer, the smaller the ionization rate ratio k, the better the performance of the APD. Compound semiconductor materials such as InAlAs or InP are used for the multiplication layer of APDs for optical communications.

When InAlAs is selected as the material for the multiplication layer, the difference between the ionization rates of electrons and holes is greater than in InP. In InP, the ionization rate of holes is greater than that of electrons, and the ionization rate of holes is about twice that of electrons. On the other hand, when InAlAs is selected as the material for the multiplication layer, the ionization rate of electrons is greater than that of holes, and the ionization rate of electrons is about five times that of holes. Therefore, since the reception sensitivity is higher when InAlAs is used as the multiplication layer, InAlAs is more suitable than InP as the material for the multiplication layer of an APD.

As mentioned above, in a PON system, a wide response band and high reception sensitivity are required for the APD, which is a semiconductor light receiving element. However, unlike a PD, an APD has a problem that the time required for multiplication, that is, the multiplication time, becomes longer as the multiplication factor increases, resulting in a decrease in the bandwidth at high multiplication factors. Although an APD with a multiplication layer made of InAlAs, which is used in optical communications, has a wider bandwidth than APDs made of other semiconductor materials, the bandwidth remains at about 20 GHz when the multiplication factor is 6 or more. In other words, there is a problem that the bandwidth of 37.5 GHz or more required for a 50G-PON system is difficult to achieve when conventional APDs are used.

Japanese Patent Application Laid-Open No. 11-008403

Hiroshi Ito, Satoshi Kodama, Yoshifumi Muramoto, Tomofumi Furuta, Tadao Nagatsuma, Tadao Ishibashi"High-Speed and High-Output InP-InGaAs Untraveling-Carrier Photodiodes"IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 10. No. 4, pp. 709-727 (2004) Jiyuan Zheng et al. al, "Digital Alloy InAlAs Avalanche Photodiodes", JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 36, No. 17, SEPTEMBER 1, pp. 3580-3585, 2018 P. J. Hambleton, B. K. Ng, S. A. Plimmer, J. P. R. David, and G. J. Rees, "The Effects of Nonlocal Impact Ionization on the Speed of Avalanche Photos," IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, No. 2, pp. 347, FEBRUARY (2003)

As mentioned above, PDs and APDs, which are semiconductor light receiving elements used in optical communications, are required to operate over an even wider bandwidth. Patent Document 1 describes an APD that uses a superlattice, but the superlattice is applied to the multiplication layer and electric field relaxation layer, not the electron transport layer, and furthermore, the thickness of each layer is 5 nm to 10 nm, so it acts as a quantum well that reflects the band gap of each layer. If the thickness of each layer in the stack exceeds several nm, energy unevenness that reflects the band gap of each layer is created, which hinders the transport of carriers and reduces the transport speed.

In 50G-PON systems, the response bands of the semiconductor light-emitting elements and semiconductor light-receiving elements, the optical output of the semiconductor light-emitting elements, and the receiving sensitivity of the semiconductor light-receiving elements are insufficient. For this reason, it is being considered to provide a digital bandwidth compensation circuit using a digital signal processor (DSP) after the APD in the optical network unit (ONU), i.e., the receiving device on the subscriber side.

In addition, in the optical line terminal (OLT), i.e., the receiving device on the station side, a semiconductor optical amplifier (SOA) is required to compensate for the lack of receiving sensitivity of the semiconductor light receiving element, and an SOA must be integrated into the electro-absorption modulated laser diode (EML) on the transmitting side of the ONU to increase the optical output. However, DSPs and SOAs consume very large amounts of power, which increases costs, and there are concerns that the replacement of existing PON systems with 50G-PON systems will not progress.

In existing PON systems other than the next-generation high-speed PON system, it has been considered to increase the number of branches of the optical signal output from the OLT in order to reduce costs. However, even in this case, it is necessary to integrate an SOA in the EML on the transmitting side of the OLT and ONU to increase the optical output, which causes problems such as increased power consumption of the transmitter and increased costs.

As described above, in order to compensate for the limitations in receiving sensitivity and response bandwidth of semiconductor photodetectors, transceivers have been designed that incorporate expensive, power-hungry DSPs and SOAs into the ONU and OLT, but this creates problems such as increased power consumption and costs.

This disclosure has been made to solve the problems described above, and aims to obtain a semiconductor photodetector that operates over a wide bandwidth.

The semiconductor light receiving element according to the present disclosure comprises:
An InP substrate;
an n-type semiconductor layer formed on the InP substrate;
an i-type electron transit layer having a digital alloy structure formed on the n-type semiconductor layer;
an n-type electric field relaxation layer formed on the i-type electron transport layer;
an i-type multiplication layer formed on the n-type electric field buffer layer;
a p-type electric field buffer layer formed on the i-type multiplication layer;
a light absorbing layer formed on the p-type electric field buffer layer;
Equipped with.

The optical line terminal according to the present disclosure comprises:
The semiconductor light receiving element described above,
an optical multiplexer/demultiplexer that inputs an optical signal to the semiconductor light receiving element;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
a clock data recovery circuit connected to the amplifier circuit and configured to recover clock data from the amplified electrical signal;
A forward error correction circuit is connected to the clock data recovery circuit and corrects an error in the clock data.

A multi-level intensity modulation transmitting/receiving device according to the present disclosure comprises:
The semiconductor light receiving element described above for receiving an optical signal intensity-modulated into multiple values;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
an analog/digital conversion circuit connected to the amplifier circuit and converting the amplified electrical signal into a digital signal;
A digital signal processing circuit is connected to the analog/digital conversion circuit and processes the digital signal.

The radio-over-fiber system according to the present disclosure comprises:
a light source that emits an analog modulated optical signal;
The semiconductor light receiving element described above for receiving the analog-modulated optical signal;
a transmission path for transmitting an analog electrical signal output from the semiconductor light receiving element to an antenna;
and an antenna connected to the transmission line for emitting the analog electrical signal as a radio wave signal.

A digital coherent receiving device according to the present disclosure includes:
The semiconductor light receiving element described above,
a polarization splitter that splits the polarization of the intensity- and phase-modulated polarization multiplexed optical signal;
a 90-degree hybrid that splits and combines the optical signals output from the polarization splitter;
and a digital signal processing circuit connected to the 90-degree hybrid device for processing a digital signal.

The SPAD (Single Photon Avalanche Diode) sensor system according to the present disclosure comprises:
A SPAD sensor constituted by the semiconductor light receiving element described above;
a quenching circuit for repeatedly applying a voltage equal to or greater than a breakdown voltage and a voltage equal to or less than the breakdown voltage to the SPAD sensor;
and an optoelectronic measurement circuit that measures the electrical signal output from the SPAD sensor.

The LIDAR device according to the present disclosure comprises:
A light source that emits light in a pulsed manner;
the semiconductor light receiving element described above for receiving light emitted from the light source and reflected by an object;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
and a distance measuring circuit that calculates a distance based on the electrical signal amplified by the amplifier circuit.

According to the semiconductor light receiving element disclosed herein, at least the electron transit layer is constructed with a digital alloy structure, thereby achieving the effect of obtaining a semiconductor light receiving element that operates over a wide bandwidth.

The optical line termination device, multilevel intensity modulation transceiver device, digital coherent receiver device, optical fiber radio system, SPAD sensor system, and LIDAR device disclosed herein use the semiconductor photodetector element disclosed herein as the semiconductor photodetector element, thereby achieving the effect of obtaining devices and systems with excellent performance.

1 is a cross-sectional view showing an element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a first embodiment. 1 is a cross-sectional view showing an element structure of an edge-illuminated PD, which is an example of a semiconductor light-receiving element according to a first embodiment. FIG. 2 is a diagram showing the relationship between the lattice constant of each constituent material and the amount of strain based on InP. 11 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a second embodiment. FIG. 11 is a cross-sectional view showing the element structure of an edge-illuminated APD, which is an example of a semiconductor light-receiving element according to a second embodiment. FIG. FIG. 13 is a diagram showing the electric field dependence of the electron dead space in an InAlAs multiplication layer. 7A to 7C are diagrams showing the ionization rates of electrons and holes. 13 is a graph showing the dependence of the ionization rate ratio and the tunnel current on the thickness of the multiplication layer. FIG. 9A to 9D are diagrams showing the ionization rates in the multiplication layer and the electric field relaxation layer, with FIG. 9A showing the ionization rate in the case of a random alloy structure multiplication layer, FIG. 9B showing the ionization rate in the case of a digital alloy structure multiplication layer, FIG. 9C showing the ionization rate in the case of a partially disordered digital alloy structure multiplication layer, and FIG. 9D showing the ionization rate in the case of a combination of a thick electric field relaxation layer and a digital alloy structure multiplication layer. 11 is a cross-sectional view showing the element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a third embodiment. 11 is a cross-sectional view showing the element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a third embodiment. 11 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a fourth embodiment. 11 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a fourth embodiment. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a fifth embodiment. FIG. 13 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a sixth embodiment. FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a seventh embodiment. FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a seventh embodiment. FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to an eighth embodiment. FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to an eighth embodiment. FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a ninth embodiment. FIG. 13 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a tenth embodiment. FIG. 13 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to an eleventh embodiment. FIG. 23 is a cross-sectional view showing the element structure of a front-illuminated PD, which is an example of a semiconductor light-receiving element according to a twelfth embodiment. FIG. 23 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a thirteenth embodiment. FIG. A configuration diagram showing an optical line terminal (OLT) of a 50G-PON system relating to embodiment 14. A configuration diagram showing an optical network unit (ONU) of a 50G-PON system relating to embodiment 14. FIG. 1 is a configuration diagram showing an optical line terminal (OLT) of a 50G-PON system as a comparative example. A diagram showing the configuration of an optical line terminal (OLT) of a 50G-PON system relating to embodiment 14. A diagram showing the configuration of an optical network unit (ONU) of a 50G-PON system relating to embodiment 14. FIG. 23 is a diagram illustrating the configuration of a multilevel intensity modulation transmitting/receiving device according to a fifteenth embodiment. 31A and 31B are diagrams showing received waveforms of a multi-level intensity modulation transmitting/receiving device according to embodiment 15. 32A and 32B are diagrams for explaining the operation of a PD when a high optical input is applied. FIG. 1 is a diagram illustrating the operation of an APD when a high optical input is applied; FIG. 2 is a diagram showing the residence times of electrons and holes for each material constituting the multiplication layer. FIG. 23 is a diagram illustrating a configuration of a radio-on-fiber system according to a sixteenth embodiment of the present invention. FIG. 1 illustrates a configuration of a radio-on-fiber system as a comparative example. A diagram showing the configuration of a digital coherent receiving device related to embodiment 17. FIG. 38A is a diagram showing waveforms of a digital coherent receiving device which is a comparative example, and FIG. 38B is a diagram showing waveforms of a digital coherent receiving device according to embodiment 17. FIG. 23 is a diagram showing the configuration of a SAPD sensor system according to an eighteenth embodiment. FIG. 40A is a diagram showing the multiplication characteristics of a SAPD sensor system which is a comparative example, and FIG. 40B is a diagram showing the multiplication characteristics of a SAPD sensor system according to embodiment 18. FIG. 13 is a diagram showing the calculated difference between the quenching electric field and the Geiger mode electric field for each multiplication layer configuration. A diagram showing the configuration of a LIDAR device related to embodiment 19. FIG. 43A is a diagram showing a received waveform of an APD of a LIDAR device which is a comparative example, and FIG. 43B is a diagram showing a received waveform of an APD of a LIDAR device according to embodiment 19.

Embodiment 1.
<Features of the semiconductor photodetector (PD) according to the first embodiment>
Before describing the specific structure of the semiconductor light receiving element according to the first embodiment, a digital alloy structure electron transit layer, which is a structural feature of the semiconductor light receiving element according to the first embodiment, will be described below. Note that the semiconductor light receiving element according to the first embodiment is a PD, but both will be described together, including an APD, which is a semiconductor light receiving element described in the second embodiment and thereafter.

The 3 dB bandwidth fc_PD of the PD is given by the following equation (1), where frc is the bandwidth limitation due to the RC time constant, and ftr is the bandwidth limited by the time it takes for carriers to travel through the depletion layer.

fc_PD=1/((1/frc) ² +(1/ftr) ² ) ^0.5 (1)

The 3 dB bandwidth fc_APD of the APD further includes the multiplication time. If the band limit due to the multiplication time is fm, then the bandwidth fc_APD is given by the following equation (2).

fc_APD = 1/((1/frc) ² + (1/ftr) ² + (1/fm) ² ) ^0.5 (2)

When the multiplication factor of an APD is small or the ionization rate ratio k is close to zero, the bandwidth is mainly limited by the RC time constant and the carrier transit time, and the value approaches equation (1). Therefore, here we will consider the case of a PD, that is, based on equation (1).

Since the RC time constant is inversely proportional to the depletion layer thickness and the transit time is directly proportional to the depletion layer thickness, equation (1) has a maximum value. In other words, fc_PD has a maximum bandwidth when frc=ftr. Substituting frc=ftr into equation (1), equation (1) is expressed as the following equation (3).

fc=ftr/√2 (3)

The 3 dB bandwidth ftr determined by the running time is expressed by the following equation (4).

ftr=3.5Vav/(2πWt) (4)

In formula (4), Vav is the average saturated transit velocity of electrons and holes, and Wt is the total depletion layer thickness. When the average saturated transit velocities of electrons and holes are Ve and Vh, respectively, Vav is expressed by the following formula (5).

2/(Vav) ⁴ =1/(Ve) ⁴ +1/(Vh) ⁴ (5)

In the InGaAs layer, when the electric field is weak (several tens of kV/cm or less), the traveling speed of electrons and holes is proportional to the electric field, but when an electric field of several tens of kV/cm or more is applied to the electrons and holes, they reach a saturation speed and become constant. The average saturation speeds of electrons and holes in the InGaAs layer are Ve = 6.5 x ¹⁰⁶ cm/s and Vh = 4.8 x ¹⁰⁶ cm/s, respectively, so Vav = 5.35 x ¹⁰⁶ cm/s. For example, if the thickness W of the depletion layer is set to Wt = 500 nm and substituted into formula (4), ftr = 59.6 GHz is obtained, and if ftr = 59.6 GHz is further substituted into formula (3), the bandwidth fc is 42.2 GHz.

To increase the bandwidth fc of the PD, as can be seen from formula (3), the time it takes for the electrons and holes to pass through the depletion layer can be shortened by increasing the travel speed of the electrons and holes. The electron speed Ve is greater than the hole speed Vh. For example, when the electrons travel in the depletion layer at Ve=6.5×10 ⁶ cm/s and Vh=4.8×10 ⁶ cm/s, the electrons can travel 1.35 times (=Ve/Vh) the distance in the same time. In other words, since the electrons can travel 1350 nm in the time it takes the holes to travel 1000 nm, even if a 350 nm electron travel layer (only electrons travel because it is the n side) is provided on the n side of the light absorption layer of the PD, the time it takes for the electrons and holes to travel through the depletion layer does not increase.

On the other hand, the thickness W of the depletion layer is increased by the thickness of the electron transport layer, i.e., 350 nm, so the RC time constant decreases, and as a result, the bandwidth of the PD can be increased. This is the role of the electron transport layer. For example, as described in Non-Patent Document 1, by providing an electron transport layer (referred to as a carrier collection layer in Non-Patent Document 1) in the PD, it is possible to increase the speed and also to pass a large photocurrent.

In this way, the electron transit layer is effective in broadening the bandwidth of semiconductor photodetectors, and if the transit speed of electrons and holes in the electron transit layer can be further increased, even wider bandwidth PDs and APDs can be realized.

Furthermore, while analyzing the multiplication characteristics of an APD with an InAlAs digital alloy structure (also called atomic layer superlattice, ALSL: Atomic Layer Super Lattice, Non-Patent Document 2) in which two-atom InAs layers and two-atom AlAs layers are repeatedly stacked, the inventors found that the distance that carriers travel through the multiplication layer until they are ionized is longer than that of a normal InAlAs layer (random alloy structure). Here, the distance that carriers travel through the multiplication layer until they are ionized is called the dead space. Figure 6 shows the dead space of an InAlAs digital alloy structure multiplication layer and an InAlAs random alloy structure multiplication layer. Note that Figure 6 will be described in detail later.

If the electron dead space length is De, then in the case of an InAlAs random alloy structure, De is approximately 40 nm, as shown in Figure 6. Compared to the InAlAs random alloy structure, we found that in the case of an InAlAs digital alloy structure, De is approximately 80 nm.

As shown in Figure 8, the ionization rate ratio k of electrons and holes drops sharply due to the dead space effect when the multiplication layer is thinned. The reason for the drop in the ionization rate ratio k is thought to be that, if the dead space length of holes is Dh, then the multiplication layer thickness becomes thinner than Dh, and holes cannot be multiplied.

The inventors found that in the case of an InAlAs digital alloy structure, the ionization rate ratio k is lower than in the case of an InAlAs random alloy structure, even if the multiplication layer is thicker. As shown in Figure 8, in the case of InAlAs with a random alloy structure, Dh is about 80 nm, whereas in the case of an InAlAs digital alloy structure, Dh is about 170 nm.

In the dead space, the energy of the traveling carriers is not consumed by ionization, so the speed increases. For example, Non-Patent Document 3 shows that the effective carrier speed in a multiplication layer with a layer thickness of 200 nm increases by 169%. This is because the effect of the dead space in the layer thickness of 200 nm becomes large when the layer thickness is about 200 nm. In other words, the traveling speed increases as the dead space increases. Therefore, by using an InAlAs digital alloy structure with a longer dead space for the electron travel layer instead of the conventional InAlAs random alloy structure, the traveling speed in the electron travel layer increases, and the time it takes to travel in the depletion layer can be shortened.

In addition, if the travel speed of holes can be increased, a hole travel layer can also be introduced. In other words, by using an InAlAs digital alloy structure with a long dead space as the hole travel layer instead of the conventional InAlAs random alloy structure, the travel speed in the hole travel layer can be increased and the time it takes to travel in the depletion layer can be shortened.

<Element structure of semiconductor photodetector (PD) according to the first embodiment>
Fig. 1 is a cross-sectional view showing the element structure of a front-illuminated PD which is an example of a semiconductor light-receiving element 100 according to the first embodiment. Also, Fig. 2 is a cross-sectional view showing the element structure of an edge-illuminated PD which is an example of a semiconductor light-receiving element 100a according to the first embodiment.

The front-illuminated PD, which is an example of the semiconductor light-receiving element 100 according to the first embodiment, includes an n-type InP substrate 1, an n-type InP buffer layer 2 having a carrier concentration of 1 to 5×10 ¹⁸ cm ^-3 and a layer thickness of 0.1 to ^1.0 μm, which are successively formed on the n-type InP substrate 1, an InAlAs electron transit layer ³ having a digital alloy structure in which an i-type AlAs layer (e.g., a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (e.g., a layer thickness of two atomic layers, about 0.6 nm) having a carrier concentration of 1×10 17 cm -3 or less and a layer thickness of 50 nm to 1000 nm are alternately laminated a plurality of times (hereinafter referred to as an i-type InAlAs digital alloy structure electron transit layer 3), an i-type InAlGaAs graded layer 4 having a carrier concentration of 5×10 17 cm -3 or less and a layer thickness of 5 to ⁵⁰ nm, and an i-type InAlGaAs graded layer 5 having a carrier concentration of 1×10 ¹⁷ cm ^-3 or less and a layer thickness of 5 to 50 nm. ^-3 or less and a layer thickness of 50 nm to 3.0 μm; i-type InAlGaAs/InAlAs graded layer 6 having a carrier concentration of 5 × 10 ¹⁷ cm ^-3 or less and a layer thickness of 5 to 50 nm; p-type InP window layer 7 having a carrier concentration of 5 × 10 ¹⁷ cm ^-3 or more and a layer thickness of 0.1 to 3.0 μm; p-type InGaAs contact layer 8; an n-type electrode 31 formed on the back surface side of the n-type InP substrate 1; and a p-type electrode 32 formed on the p-type InGaAs contact layer 8.

A p-type InAlAs window layer may be used instead of the p-type InP window layer 7. The n-type InP buffer layer 2 is also called an n-type semiconductor layer.

The semiconductor light receiving element 110 of embodiment 1 shown in Figure 2 has a layer structure similar to that of the semiconductor light receiving element 100, but further includes an Fe-doped semi-insulating InP buried layer 20 formed at least on the end surface onto which the incident light 90 is incident.

Silicon (Si) is optimal as the n-type dopant for the n-type InP buffer layer 2. This is to prevent n-type impurities from diffusing from the n-type InP buffer layer 2 into the i-type InAlAs digital alloy structure electron transit layer 3, causing the digital alloy structure to become disordered. Here, disordering refers to the phenomenon in which the compositions of the layers of the digital alloy structure mix together, resulting in a random alloy structure with an average composition.

As described above, the i-type InAlAs digital alloy structure electron transit layer 3 is composed of semiconductor layers in which an AlAs layer (layer thickness: 2 atomic layers, approximately 0.6 nm) and an InAs layer (layer thickness: 2 atomic layers, approximately 0.6 nm) are alternately stacked in this order. However, the thicknesses of the AlAs layer and the InAs layer may be in the range of 2 atomic layers or more and 6 atomic layers or less, respectively. The reason for 6 atomic layers or less is that it is desirable for the stacked structure of the AlAs layer and the InAs layer not to function as a quantum well structure. In other words, the digital alloy structure is composed of two types of semiconductor layers, each made of a different semiconductor material, alternately stacked in a period of 2 atomic layers to 6 atomic layers.

Furthermore, the number of atomic layers of each layer of the i-type InAlAs digital alloy structure electron transit layer 3 is preferably 2 to 4 atomic layers, with 2 atomic layers being optimal. The reason for this is that the thinner the atomic layer thickness of each layer, the greater the effect of reducing the ionization rate ratio k due to the digital alloy structure. In addition, when considering not only the performance as a semiconductor light receiving element but also productivity, a layer thickness of 4 to 6 atomic layers is also suitable, which reduces the number of shutter switching times during crystal growth by molecular beam epitaxy (MBE). In view of the above factors, it can be said that the number of atomic layers of each layer of the i-type InAlAs digital alloy structure electron transit layer 3 is in the preferred range of 2 to 6 atomic layer periods. Similarly, from the viewpoint of productivity, it is not necessary for the entire electron transit layer to have an InAlAs digital alloy structure, but a part of the electron transit layer may have an InAlAs digital alloy structure, and the remaining part may have an InAlAs random alloy structure.

The thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is in the range of 50 nm to 1000 nm. For example, if the thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is 500 nm, the AlAs layer (2 atomic layers) / InAs layer (2 atomic layers) is repeated 417 times. From FIG. 8, the dead space effect is significantly manifested at a layer thickness of 200 nm or less, so the layer thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is most preferably in the range of 50 nm to 200 nm. In addition, if the layer thickness is 400 nm or less, the electron transit speed is fast at a distance of 200 nm, which is 50% or more of the layer thickness, so a large dead space effect can be obtained even in the layer thickness range of 50 nm to 400 nm.

Considering the affinity with the InP that constitutes the n-type InP buffer layer 2, it is preferable to make the layer thickness of only the first AlAs layer of the i-type InAlAs digital alloy structure electron transit layer 3 three atomic layers or more thick. Alternatively, the i-type InAlAs digital alloy structure electron transit layer 3 may be laminated by alternately forming InAs layers and AlAs layers in that order.

The conductivity type of the InAlAs digital alloy electron transport layer is, for example, i-type, and the carrier concentration is, for example, 1×10 ¹⁷ cm ⁻³ or less. However, the conductivity type of the InAlAs digital alloy electron transport layer may be p-type or n-type, and the carrier concentration is, for example, 5×10 ¹⁷ cm ⁻³ or less.

In addition to the electron transit layer composed of an InAlAs digital alloy structure, an InAlGaAs digital alloy structure in which InAlyGa(1-y)As (layer thickness 2 to 6 atomic layers, Al composition ratio Y) and InAlzGa(1-z)As (layer thickness 2 to 6 atomic layers, Al composition ratio Z) are alternately laminated, as shown in Figure 3, which shows the relationship between the lattice constant of each constituent material and the amount of strain based on InP, can also be applied as the electron transit layer of the present disclosure. Furthermore, a digital alloy structure made of InAlAsSb, a material system to which antimony (Sb) is added, can also be applied as the electron transit layer of the present disclosure.

The i-type InAlGaAs graded layer 4 and the i-type InAlGaAs/InAlAs graded layer 6 are layers in which the band gap is gradually changed by changing the composition of InAlGaAs, and each layer thickness is within the range of 5 to 50 nm. The composition of InAlGaAs may be changed stepwise, and the band gap is intermediate between that of an InP layer and an InGaAs layer. The carrier concentration is 5×10 ¹⁷ cm ^-3 or less, and if the carrier concentration is low, it may be p-type or n-type. The i-type InAlGaAs graded layer 4 and the i-type InAlGaAs/InAlAs graded layer 6 are not necessarily required and may be omitted.

In one example of the element structure of the semiconductor photodetector 100 shown in Figure 1, an i-type InAlGaAs/InAlAs graded layer 6 is formed by alternately stacking two types of i-type InAlGaAs layers with different compositions multiple times on an i-type InGaAs light absorption layer 5.

<Method of Manufacturing Semiconductor Light-Receiving Element According to First Embodiment>
A front-illuminated PD, which is an example of the semiconductor light-receiving element 100 according to the first embodiment, can be realized by using metal organic vapor phase epitaxy (MOVPE) or MBE on an n-type InP substrate 1. A method for manufacturing the semiconductor light-receiving element 100 according to the first embodiment will be described below.

An n-type InP buffer layer 2 having a thickness of 0.1 to 1 μm and a carrier concentration of 1 to 5×10 ¹⁸ cm ⁻³ is crystal-grown on an n-type InP substrate 1 by MOVPE or MBE.

An i-type InAlAs digital alloy structure electron transit layer 3 having a carrier concentration of 1×10 ¹⁷ cm ^-3 or less and a layer thickness of 50 nm to 1000 nm is crystal-grown on the n-type InP buffer layer 2. That is, an AlAs layer (having a layer thickness of two atomic layers, approximately 0.6 nm) and an InAs layer (having a layer thickness of two atomic layers, approximately 0.6 nm) are crystal-grown alternately in this order from above the n-type InP buffer layer 2, thereby forming the i-type InAlAs digital alloy structure electron transit layer 3.

On the i-type InAlAs digital alloy structure electron transit layer 3, the i-type InAlGaAs graded layer 4 having a thickness of 5 nm to 50 nm and a carrier concentration of 5×10 ¹⁷ cm ⁻³ or less is crystal-grown.

On the i-type InAlGaAs graded layer 4, an i-type InGaAs light absorption layer 5 having a thickness of 50 nm or more and 3 μm or less, an i-type InAlGaAs/InAlAs graded layer 6, a p-type InP window layer 7 having a thickness of 0.1 μm or more and 3 μm or less, and a p-type InGaAs contact layer 8 are successively grown by crystal growth.

After the crystal growth is completed, a p-type electrode 32 is formed on the surface of the p-type InGaAs contact layer 8, and an n-type electrode 31 is formed on the back surface of the n-type InP substrate 1. The p-type electrode 32 of the PD is made of metal materials such as Ti and Au. A voltage is applied to the PD in the reverse direction, and the operating voltage is 0V to 10V.

In the case of the surface-illuminated PD shown in Figure 1, incident light 90 is incident perpendicularly to the i-type InGaAs light absorption layer 5. The diameter of the light receiving part of the PD is circular, or the size of the long side of the light receiving part of the PD is rectangular, is in the range of 5 μm to 1 mm. The incident surface of the PD is coated with an anti-reflective coating (not shown).

In the case of the end-illuminated PD shown in Figure 2, incident light 90 is incident from a direction parallel to the i-type InGaAs light absorption layer 5. From the viewpoint of reliability, the end face is covered with an insulating film, an organic film, or a semiconductor layer. In the end-illuminated PD shown in Figure 2, an Fe-doped semi-insulating InP buried layer 20 is formed on the end face. The layer thickness of the Fe-doped semi-insulating InP buried layer 20 is in the range of 100 nm to 5 μm in the incident direction.

<Function of Semiconductor Photodetector (PD) According to First Embodiment>
The effect on a semiconductor photodetector (PD) according to the first embodiment will be described. The thickness of the electron transit layer used in a PD capable of high-speed operation of 25 Gbps or more is often about 200 nm. If the thickness of the light absorption layer is 500 nm, the introduction of the electron transit layer can reduce the pn junction capacitance to 5/7 (=500 nm/(500 nm+200 nm)).

On the other hand, by introducing an electron transit layer into the PD, the electron transit distance increases by 7/5 times. As shown in formula (1), the bandwidth of the PD is affected by both the bandwidth frc due to the capacitance and the bandwidth ftr due to the carrier transit time, so part of the bandwidth improvement effect due to the reduction in the pn junction capacitance is offset.

However, by applying an i-type InAlAs digital alloy structure electron transit layer 3 with a long dead space length, the speed of electrons in the electron transit layer increases, shortening the transit time and improving the bandwidth limit ftr. As a result, the bandwidth of the PD is further improved. In the following description of devices, systems, etc., a PD having an InAlAs digital alloy structure electron transit layer according to the present disclosure will be referred to as the DA-PD of the present disclosure.

<Effects of First Embodiment>
As described above, the semiconductor light receiving element according to the first embodiment has an i-type InAlAs digital alloy structure electron transit layer, which provides an effect of providing a semiconductor light receiving element that operates over a wide band.

Embodiment 2.
<Features of the semiconductor photodetector (APD) according to the second embodiment>
Before describing the specific structure of the semiconductor light receiving element according to the second embodiment, a digital alloy structure multiplication layer, which is a structural feature of the semiconductor light receiving element according to the second embodiment, will be described below.

If a wideband APD of 37.5 GHz or more can be realized, a next-generation high-speed PON system can be realized without using a DSP or an SOA. In the case of a PD, which is relatively easy to make into a wideband APD, the response bandwidth is as follows:
(1) RC time constant (R is the element resistance, C is the element capacitance)
(2) Carrier transit time (the time it takes for an electron or hole to travel through the depletion layer)
In APD, the
(3) It is also limited by the multiplication time (the time it takes for electrons and holes to multiply in a chain reaction in the multiplication layer, which increases in proportion to the multiplication factor).

Although a PD can realize the above-mentioned 37.5 GHz band, an APD requires a multiplication time, so if the multiplication factor is increased, it becomes difficult to realize the desired band. The multiplication time TM is expressed by the following equations (6) to (8).

Multiplication time TM = multiplication factor M/GB product (6)

GB product = 1 / (2πNkτav) (7)

In other words,

Multiplication time TM = 2πNkMτav (8)

It becomes.

Here, GB product is the product of the multiplication factor and the bandwidth, k is the ionization rate ratio, N is a coefficient that is loosely dependent on the ionization rate ratio k, and τav is the average time it takes for electrons and holes to travel through the multiplication layer. Therefore, by reducing the ionization rate ratio k, it is possible to shorten the multiplication time TM. In particular, to realize a high-speed PON system, it is necessary to make the multiplication time TM approach zero, that is, to make the ionization rate ratio k approach zero.

In order to make the ionization rate ratio k zero, various compound semiconductors have been proposed as materials for the multiplication layer. In addition, in order to reduce the ionization rate ratio k, a digital alloy structure has been proposed in which semiconductor layers of different compositions are alternately stacked in a cycle of 1 to 6 atomic layers. However, it is difficult to make the ionization rate ratio k zero even with the digital alloy structure unless the structure is optimized. The digital alloy structure is described in Non-Patent Document 2.

Therefore, in order to reduce the ionization rate ratio k of the digital alloy structure, the inventors fabricated an APD with a digital alloy structure multiplication layer using a multiplication layer in which two-atom InAs layers and two-atom AlAs layers are alternately stacked, and as a result of analyzing the multiplication characteristics, they discovered that the distance that carriers travel through the multiplication layer until they are ionized is longer than that of an APD with an InAlAs multiplication layer made of normal bulk crystal, that is, an InAlAs random alloy structure multiplication layer. The distance that carriers travel through the multiplication layer until they are ionized is called the dead space.

The length of the dead space (hereinafter referred to as the dead space length) is longer for holes than for electrons, so in the case of an InAlAs random alloy structure made of a normal bulk crystal, if the thickness of the multiplication layer is thinned to a level of several tens of nm, the ionization rate ratio k decreases because the holes cannot be ionized. However, when the thickness of the multiplication layer is thinned to a level of several tens of nm, a new problem occurs in that a high electric field must be applied to the multiplication layer to obtain the desired multiplication factor, and leakage currents such as tunnel currents increase. In other words, an increase in tunnel current increases the noise generated by the APD. On the other hand, the inventors' analysis discovered that the ionization rate ratio k = 0 in the digital alloy structure, even if the multiplication layer has a thickness of 100 nm or more, because the dead space is unusually large in the digital alloy structure compared to the random alloy structure.

That is, the inventors have found for the first time that it is possible to make the ionization rate ratio k = 0 while suppressing the tunnel current by constructing the multiplication layer of the APD with a digital alloy structure. Specifically, it was found that in the multiplication layer made of the digital alloy structure of the present disclosure, the ionization rate ratio k drops sharply at a layer thickness of 170 nm or less, and in particular, the dead space effect improves dramatically when the layer thickness of the multiplication layer is in the range of 60 to 130 nm. In other words, the inventors have demonstrated that the ionization rate ratio k = 0, which was impossible to achieve with a multiplication layer made of a random alloy structure or a multiplication layer made of a thick digital alloy structure, can be achieved by applying the multiplication layer made of the digital alloy structure of the present disclosure. At present, no research institute has reported that the thinning of the multiplication layer of an APD having a digital alloy structure has a higher effect of reducing the ionization rate ratio k than the thinning of the multiplication layer of an APD made of a conventional material.

<Element structure of semiconductor photodetector (APD) according to the second embodiment>
Fig. 4 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 110 according to the second embodiment. Also, Fig. 5 is a cross-sectional view showing the element structure of an edge-illuminated APD, which is an example of the semiconductor light receiving element 110a according to the second embodiment.

The semiconductor light receiving element 110 according to the second embodiment includes an n-type InP substrate 1, an n-type InAlAs buffer layer 2a having a carrier concentration of 1 to 5× ¹⁰ cm ⁻³ and a thickness of 0.1 to ^1.0 μm, which are successively formed on the n-type InP substrate 1, an InAlAs electron transit layer ³ having a digital alloy structure in which an i-type AlAs layer (e.g., a layer thickness of two atomic layers, approximately 0.6 nm) and an i-type InAs layer (e.g., a layer thickness of two atomic layers, approximately 0.6 nm) having a carrier concentration of 1×10 cm−3 or less and a layer thickness of 50 to 1000 nm are alternately laminated a plurality of times, an n-type InAlAs electric field relaxation layer 12 having a carrier concentration of 1× ¹⁰ to 5× ¹⁰ cm ⁻³ and a layer thickness of 10 to 70 nm, and an n-type InAlAs buffer layer 2b having a carrier concentration of 1×10 cm−3 or less and a layer thickness of 50 to ¹⁰⁰⁰ nm. a p-type InP electric field relaxation layer 14 having a carrier concentration of 1×10 ¹⁶ to 5×10 ¹⁸ cm ^-3 and a thickness of 10 to 70 nm; an i-type InGaAs light absorption layer 5 having a carrier concentration of ¹ ×10 ¹⁷ cm ^-3 or less and a thickness of 50 nm to 3.0 μm; an i-type InAlGaAs/InAlAs graded layer 6 having a carrier concentration of 5×10 ¹⁷ cm ^-3 or less and a thickness of 5 to ⁵⁰ nm; The p-type InP window layer 7 has a thickness of 0.1 to 3.0 μm and a conductivity type of ⁻³ or more, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back surface side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8.

A p-type InAlAs window layer may be used instead of the p-type InP window layer 7. The n-type InAlAs buffer layer 2a is also called an n-type semiconductor layer.

The semiconductor light receiving element 110a of embodiment 2 shown in Figure 5 has a layer structure similar to that of the semiconductor light receiving element 110, but further includes an Fe-doped semi-insulating InP buried layer 20 formed at least on the end surface onto which the incident light 90 is incident.

Silicon (Si) is optimal as the n-type dopant for the n-type InAlAs buffer layer 2a. The n-type InAlAs buffer layer 2a may have either a random alloy structure or a digital alloy structure.

As described above, the i-type InAlAs digital alloy structure electron transit layer 3 is composed of semiconductor layers in which AlAs layers (layer thickness: 2 atomic layers, approximately 0.6 nm) and InAs layers (layer thickness: 2 atomic layers, approximately 0.6 nm) are alternately stacked in this order. However, it is sufficient that the thicknesses of the AlAs layers and InAs layers are in the range of 2 atomic layers or more and 6 atomic layers or less, respectively. The reason for 6 atomic layers or less is that it is desirable for the stacked structure of the AlAs layers and InAs layers not to function as a quantum well structure.

Furthermore, the number of atomic layers of each layer of the i-type InAlAs digital alloy structure electron transit layer 3 is preferably 2 to 4 atomic layers, with 2 atomic layers being optimal. The reason for this is that the thinner the atomic layer thickness of each layer, the greater the effect of reducing the ionization rate ratio k due to the digital alloy structure. In addition, when considering not only the performance as a semiconductor light receiving element but also productivity, a layer thickness of 4 to 6 atomic layers is also optimal, as this reduces the number of shutter switching times during crystal growth by MBE. In consideration of the above factors, it can be said that the number of atomic layers of each layer of the i-type InAlAs digital alloy structure electron transit layer 3 is preferably in the range of 2 to 6 atomic layer periods.

The thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is in the range of 50 nm to 1000 nm. For example, if the thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is 500 nm, the AlAs layer (2 atomic layers) / InAs layer (2 atomic layers) is repeated 417 times. As shown in FIG. 8, the dead space effect is significantly manifested at a layer thickness of 200 nm or less, so the layer thickness of the i-type InAlAs digital alloy structure electron transit layer 3 is most preferably in the range of 50 nm to 200 nm. In addition, if the layer thickness is 400 nm or less, the electron transit speed is fast at a distance of 200 nm, which is 50% or more of the layer thickness, so a large dead space effect can be obtained even in the range of 50 nm to 400 nm.

Considering the affinity with InAlAs constituting the n-type InAlAs buffer layer 2a, it is preferable to make the layer thickness of only the first AlAs layer of the i-type InAlAs digital alloy structure electron transit layer 3 three atomic layers or more thick. Alternatively, the i-type InAlAs digital alloy structure electron transit layer 3 may be formed by alternately stacking InAs layers and AlAs layers in that order.

The conductivity type of the i-type InAlAs digital alloy structure electron transit layer 3 is i-type, and the carrier concentration is, for example, 1×10 ¹⁷ cm ^-3 or less. However, the conductivity type of the i-type InAlAs digital alloy structure electron transit layer 3 may be p-type or n-type, in which the carrier concentration is 5×10 ¹⁷ cm ^-3 or less.

In addition to the electron transit layer composed of an InAlAs digital alloy structure, an InAlGaAs digital alloy structure in which InAlyGa(1-y)As (layer thickness of 2 to 6 atomic layers, Al composition ratio Y) and InAlzGa(1-z)As (layer thickness of 2 to 6 atomic layers, Al composition ratio Z) are alternately stacked can also be applied as the electron transit layer of the present disclosure. Furthermore, a digital alloy structure made of InAlAsSb, a material system to which antimony (Sb) is added, can also be applied as the electron transit layer of the present disclosure.

The n-type electric field relaxation layer does not necessarily have to be InAlAs, and may be an n-type InP or n-type InAlAs digital alloy structure. The n-type InAlAs electric field relaxation layer 12 is provided to prevent an excessive electric field from being applied to the i-type InAlAs multiplication layer 13, causing multiplication. In addition, the n-type InAlAs electric field relaxation layer 12 has the function of adjusting the electric field so that the traveling speed is maximized, since if too much electric field is applied to the i-type InAlAs multiplication layer 13, the speed of the electrons begins to decrease, that is, an overshoot phenomenon of the traveling speed occurs.

The i-type InAlGaAs/InAlAs graded layer 6 is a layer in which the band gap is gradually changed by changing the composition of InAlGaAs, and each layer thickness is within the range of 5 to 50 nm. The composition of InAlGaAs may be changed stepwise, and the band gap is intermediate between that of an InP layer and an InGaAs layer. The carrier concentration is 5×10 ¹⁷ cm ^-3 or less, and if the carrier concentration is low, it may be p-type or n-type. The i-type InAlGaAs/InAlAs graded layer 6 is not necessarily required and may be omitted.

A layer having an intermediate band gap such as InAlGaAs or InGaAsP and a thickness of 0.1 μm or less may be provided between the p-type InP electric field relaxation layer 14 and the i-type InGaAs light absorption layer 5. This is because it is possible to prevent the accumulation of electrons and holes at the heterojunction interface.

In one example of the element structure of the semiconductor light receiving element 110 shown in Figure 4, an i-type InAlGaAs/InAlAs graded layer 6 is formed by alternately stacking two types of i-type InAlGaAs layers with different compositions multiple times on an i-type InGaAs light absorption layer 5.

Ti and Au are used for the p-type electrode 32 of the APD, which is an example of a semiconductor light receiving element according to the second embodiment. A voltage is applied in the reverse direction to the APD, and the operating voltage is 10V to 100V. The electric field of the i-type InAlAs multiplication layer 13 when the APD is operating is 500kV/cm to 900kV/cm. The electric field of the i-type InGaAs light absorption layer 5 is set to 300kV/cm or less. The multiplication factor is used at 3 to 30, but is 100 or more when operating in Geiger mode.

<Function of Semiconductor Photodetector (APD) According to Second Embodiment>
The effect on the semiconductor photodiode (APD) according to the second embodiment will be described.
The APD according to the second embodiment, like the PD according to the first embodiment, employs an i-type InAlAs digital alloy structure electron transit layer 3 with a long dead space length, thereby increasing the speed of electrons in the electron transit layer, shortening the transit time, and improving the bandwidth limit ftr. As a result, an effect is achieved in which the bandwidth of the APD is further improved.

<Effects of the Second Embodiment>
As described above, the semiconductor light receiving element according to the second embodiment has an i-type InAlAs digital alloy structure electron transit layer, which provides an effect of providing a semiconductor light receiving element having high reception sensitivity and operating over a wide band.

A modified example of embodiment 2.
A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the second embodiment, and an edge-illuminated APD, which is another example, will be described below.
The semiconductor light receiving element according to the modified example of the second embodiment is structurally different in that the i-type InAlAs multiplication layer 13 of the semiconductor light receiving element according to the second embodiment, i.e., the InAlAs multiplication layer having a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.

One example of the structure of an i-type InAlAs digital alloy structure multiplication layer is a digital alloy structure in which i-type AlAs layers (for example, a layer thickness of two atomic layers, approximately 0.6 nm) and i-type InAs layers (for example, a layer thickness of two atomic layers, approximately 0.6 nm) are alternately stacked multiple times.

The thickness of the i-type InAlAs digital alloy structure multiplication layer is in the range of 40 nm to 1000 nm. However, in order to increase the dead space effect in the i-type InAlAs digital alloy structure multiplication layer, the thickness of the i-type InAlAs digital alloy structure multiplication layer may be in the range of 40 nm to 170 nm. Furthermore, considering the typical degree of variation in layer thickness during the manufacture of the semiconductor light receiving element 100 of 20%, the thickness of the i-type InAlAs digital alloy structure multiplication layer is more preferably in the range of 50 nm to 140 nm.

<Function of Semiconductor Photodetector (APD) According to Modification of Second Preferred Embodiment>
The operation of the APD, which is an example of a semiconductor light receiving element according to a modification of the second embodiment, will be described below.
The inventors have found that the use of a digital alloy structure multiplication layer, as in the APD according to the modified example of the second embodiment, enhances the dead space effect, that is, the effect of reducing the ionization rate ratio k. FIG. 6 is a diagram showing the electric field dependence of the electron dead space in an InAlAs multiplication layer. As a result of analyzing the electron multiplication characteristics in a digital alloy structure multiplication layer, the inventors have clarified that, as shown in the graph of FIG. 6, the InAlAs digital alloy structure multiplication layer of the present disclosure has a longer dead space than the conventional InAlAs random alloy structure multiplication layer.

7A to 7C are graphs showing the ionization rates of electrons and holes, respectively. FIG. 7A shows the ionization rate in the case of electron ionization, FIG. 7B shows the ionization rate in the case of hole ionization, and FIG. 7C shows the ionization rate when the multiplication layer is thinned. In a conventional InAlAs random alloy structure multiplication layer, as shown in the graph of FIG. 6, the dead space length is about 45 nm, so the thickness of the multiplication layer needs to be thinned to about 1.5 times the dead space (about 70 nm). However, when the multiplication layer is thinned to 70 nm, the electric field of the multiplication layer becomes high, and the noise increases with a sudden increase in the tunnel current, making it difficult to obtain an APD with good reception sensitivity.

On the other hand, in the InAlAs digital alloy structure multiplication layer of the APD according to the modified example of embodiment 2, as shown in the graph of Figure 6, when the reciprocal of the applied electric field is 1.47 x ^10-6 cm/V, the dead space length is approximately 85 nm, so even if the thickness of the multiplication layer is approximately 1.5 times that of the dead space (approximately 130 nm), it is possible to make the ionization rate ratio k approach zero. Therefore, the effect of the tunnel current is small in the APD according to the modified example of embodiment 2.

Furthermore, in the InAlAs digital alloy structure multiplication layer, the dead space is highly dependent on the applied electric field, and when the reciprocal of the applied electric field is 1.27×10 ⁻⁶ cm/V, the dead space length is approximately 50 nm, as shown in the graph of Fig. 6, so the multiplication layer needs to be thinned to 75 nm. In other words, the thickness of the InAlAs digital alloy structure multiplication layer can be made thicker than the thickness of the InAlAs random alloy structure multiplication layer.

Fig. 8 is a diagram showing the dependence of the ionization rate ratio and the tunnel current on the thickness of the multiplication layer. The inventors fabricated APDs having an InAlAs digital alloy structure multiplication layer and an InAlAs random alloy structure multiplication layer, respectively, measured the ionization rate ratio k, and further plotted the results in Fig. 8 together with the measurement results of References 1 and 2 described in Fig. 8. References 1 and 2 in Fig. 8 are as follows:
(1) Reference 1
Yuan Yuan, et al. "Temperature dependence of the ionization coefficients of InAlAs and AlGaAs digital alloys" pp. 794, Vol. 6, No. 8/August 2018/Photonics Research
(2) Reference 2
Wenyang Wang, et al. "Characteristics of thin InAlAs digital alloy avalanche photographs" pp. 3841, Vol. 46, No. 16/15 August 2021/Optics Letters

As shown in FIG. 8, in the InAlAs random alloy structure multiplication layer, the effect of reducing the ionization rate ratio k by the dead space does not appear unless the thickness of the multiplication layer is 80 nm or less. On the other hand, if the thickness of the multiplication layer is made thinner than 80 nm, the tunnel current increases rapidly and a tunnel breakdown occurs. When the thickness of the multiplication layer is around 60 nm, the reduction of the ionization rate ratio k and the limitation of the tunnel current are barely compatible, but the margin of the layer thickness is only a few nm, making it extremely difficult to stably manufacture APDs. In addition, the ionization rate ratio k is also large at 0.12. In other words, in the conventional InAlAs random alloy structure multiplication layer, it is difficult to apply the effect of reducing the ionization rate ratio k by making the layer thinner to APDs.

On the other hand, in the InAlAs digital alloy structure multiplication layer of the present disclosure, as discovered by the inventors, the dead space is large, and therefore, as the multiplication layer is made thinner, the ionization rate ratio k starts to decrease to 0.1 or less at a layer thickness of 170 nm, as shown in Figure 8. Here, the ionization rate ratio k is determined from the measured value of the multiplication noise, and is the minimum value of the ionization rate ratio in the range of multiplication factors 1 to 10. For the same ionization rate ratio k, the layer thickness of the InAlAs digital alloy structure multiplication layer is more than twice as large as that of the InAlAs random alloy structure multiplication layer.

As shown in the graph in Figure 8, in an APD with a pn junction diameter of 20 μm, if the thickness of the multiplication layer at which the tunnel current is 1 μA is limited to 40 nm, then a layer thickness in the range of 40 nm to 170 nm is the optimal range for an InAlAs digital alloy structure multiplication layer, and layer thicknesses within this range can be fabricated with sufficient reproducibility.

The thickness of the InAlAs digital alloy structure multiplication layer at which the dead space effect is sufficient to reduce the ionization rate ratio k is considered to be approximately twice the dead space length when the reciprocal of the applied electric field is 1.47 x 10 ^-6 cm/V. Considering that the dead space length is 85 nm as shown in Figure 8, therefore, 170 nm, which is twice the dead space length, is a suitable upper limit for the thickness of the InAlAs digital alloy structure multiplication layer.

In addition, in order to control the ionization rate ratio k to 0.05 or less in the InAlAs digital alloy structure multiplication layer, the thickness of the multiplication layer is preferably 150 nm or less, as shown in the graph of Figure 6. Furthermore, in order to achieve a tunnel current of 1 μA or less and an ionization rate ratio k of almost zero, the optimal thickness of the multiplication layer is in the range of 60 nm to 130 nm. If the margin during the fabrication of the APD is 10 nm, the thickness of the multiplication layer is preferably set in the range of 70 nm to 120 nm.

As shown in Figure 6, the length of the dead space is preferably 50 nm to 90 nm. The ratio of the length of the dead space to the thickness of the multiplication layer is preferably 29% or more, calculated by dividing the minimum dead space length of 50 nm by the maximum thickness of the multiplication layer of 170 nm. As the ratio increases, the ionization rate ratio k becomes smaller, but it cannot exceed 100%. This is because multiplication does not occur when the ionization rate ratio k exceeds 100%. Therefore, in principle, the ratio of the length of the dead space to the thickness of the multiplication layer is preferably 29% or more and less than 100%. Furthermore, since the thickness of the multiplication layer in this prototype was 120 nm, the optimal range confirmed experimentally is 42% (= 50 nm/120 nm) to 75% (= 90 nm/120 nm).

The inventors considered why an ionization rate ratio k = 0 could not be achieved with a conventional InAlAs random alloy structure multiplication layer, but an ionization rate ratio k = 0 could be achieved with the InAlAs digital alloy structure multiplication layer disclosed herein.

If the dead space length of electrons is De and the dead space length of holes is Dh, the conditions for achieving an ionization rate ratio k = 0 are expressed by the following formulas (9) and (10). Note that formula (9) represents the condition for the difference in the dead space lengths, and formula (10) represents the condition for the tunnel current.

Dhe = Dh - De > 0 (9)

Dh>Tmin (10)

Here, Dhe is the difference between the dead space lengths of holes and electrons. Tmin is the minimum thickness of the multiplication layer at which the tunnel current becomes small enough that it does not affect noise, and the thicker the multiplication layer, the more the tunnel current decreases. As shown in Figure 7C, when the thickness of the multiplication layer becomes equal to or smaller than the dead space length of holes, holes are no longer multiplied and the ionization rate ratio k = 0, so the condition for the difference in dead space length is set as shown in the above formula (9).

6 and 8, in the case of an InAlAs random alloy structure multiplication layer, the values at which the ionization rate ratio k starts to decrease as the multiplication layer is made thinner are De about 40 nm and Dh about 80 nm. Since the pn junction diameter is 20 μm in diameter and the tunnel current is 100 nA or less, the minimum layer thickness Tmin = 90 nm, and the InAlAs random alloy structure does not satisfy the tunnel current conditions, it is impossible to achieve an ionization rate ratio k = 0.

On the other hand, in the case of an InAlAs digital alloy structure multiplication layer, the ionization rate ratio k starts to decrease as the multiplication layer is made thinner at values De of about 80 nm and Dh of about 170 nm. When the pn junction diameter is 20 μm in diameter and the tunnel current is 100 nA or less, the minimum layer thickness Tmin = 90 nm, so there is a multiplication layer thickness that satisfies the condition of ionization rate ratio k = 0. Note that the minimum layer thickness Tmin is the same for the InAlAs digital alloy structure multiplication layer and the InAlAs random alloy structure multiplication layer because the band gaps of the two do not change.

Specifically, in the case of a random alloy structure, De is about 40 nm and Dh is about 80 nm. In contrast, the inventors found that in the case of a digital alloy structure, De is about 80 nm and Dh is about 170 nm.

In the InAlAs digital alloy multiplication layer, the difference in lattice constant between the InAs (lattice constant = 0.606 nm) and AlAs (lattice constant = 0.566 nm) that make up the superlattice is very large at 6.55%. For this reason, the dopants in the electric field relaxation layer, that is, the impurities, may diffuse into the InAlAs digital alloy multiplication layer during the manufacturing process, causing disorder within the multiplication layer.

9A to 9D are diagrams showing the ionization rate in the multiplication layer and the electric field relaxation layer, where FIG. 9A shows the ionization rate in the case of the InAlAs random alloy structure multiplication layer, FIG. 9B shows the ionization rate in the case of the InAlAs digital alloy structure multiplication layer, FIG. 9C shows the ionization rate in the case of the partially disordered InAlAs digital alloy structure multiplication layer, and FIG. 9D shows the ionization rate in the case of combining a thick electric field relaxation layer and an InAlAs digital alloy structure multiplication layer. Compared to the InAlAs random alloy structure multiplication layer shown in FIG. 9A, the dead space length of the InAlAs digital alloy structure multiplication layer shown in FIG. 9B is long, but due to dopant diffusion from the electric field relaxation layer, the dead space length is short in the partially disordered InAlAs digital alloy structure multiplication layer, as shown in FIG. 9C.

In order to avoid the influence of disorder in the InAlAs digital alloy structure multiplication layer, the selection of the material and dopant of the electric field relaxation layer and the doping concentration are important. The impurity diffusion equation is expressed by the following formula (11).

dN/dt=D( ^d2N / ^d2x )−F (11)

In formula (11), N is the impurity concentration, t is time, D is the diffusion constant, x is the position, and F is the external force acting on the diffusion. Examples of materials for the electric field relaxation layer include InP, InAlAs random alloy structure, and InAlAs digital alloy structure. Examples of p-type dopants for the electric field relaxation layer include Be and Zn. Considering the p-type dopant, a combination of a Be-doped p-type InP electric field relaxation layer and an InAlAs digital alloy structure multiplication layer is preferable. This is because Be has a small diffusion constant D and also forms a potential barrier between the InAlAs digital alloy structure multiplication layer. The potential barrier corresponds to F in formula (11).

In order to prevent the variation in the amount of electric field relaxation, that is, the product of the layer thickness and the carrier concentration, from increasing when the thickness of the electric field relaxation layer varies, the carrier concentration of the electric field relaxation layer is preferably 2×10 ¹⁸ cm ^-3 or less. When InAlAs is used as the material for the electric field relaxation layer, Zn doping is optimal, and the carrier concentration is optimally 2×10 ^{18 cm -3 or less. Note that if the impurity concentration is higher than 2×10 18 cm -3 ,} the amount of inactive impurities increases and diffusion is likely to occur, so the carrier concentration must be 5×10 ¹⁸ cm ^-3 or less.

The electric field relaxation amount ΔE is expressed by the following formula (12).

ΔE=W·q·N/ε (12)

When the electric field relaxation amount ΔE is constant, if the carrier concentration of the electric field relaxation layer is increased, the thickness of the electric field relaxation layer must be reduced in inverse proportion to the carrier concentration, where W is the thickness of the electric field relaxation layer, q is the elementary charge, N is the carrier concentration of the electric field relaxation layer, and ε is the dielectric constant.

When the carrier concentration N of the electric field buffer layer is about 5×10 ¹⁸ cm ^-3 , the thickness of the electric field buffer layer is about 10 nm. In order to prevent the shortening of the dead space length due to impurity diffusion into the multiplication layer, the carrier concentration of the electric field buffer layer is controlled to be 5×10 ¹⁸ cm ^-3 or less. In addition, the electric field buffer layer needs to have a thickness of 10 nm or more.

On the other hand, as shown in Figure 9D, when the electric field buffer layer becomes thicker than 1.5 times the dead space length of the electric field buffer layer, multiplication occurs in the electric field buffer layer. As shown in Figure 6, in the random alloy structure, the dead space length is 45 nm or less, so the layer thickness of the random alloy structure electric field buffer layer needs to be 70 nm or less. On the other hand, in the InAlAs digital alloy structure, the dead space length is 85 nm or less, so the layer thickness of the digital alloy electric field buffer layer needs to be 130 nm or less.

Note that the dead space lengths shown in Figures 9A to 9D have the following relationship: dead space (Figure 9A) < dead space (Figure 9D) < dead space (Figure 9C) < dead space (Figure 9B).

<Effects of the semiconductor photodetector (APD) according to the modification of the second embodiment>
First, a first effect of the semiconductor light receiving element according to the modification of the second embodiment will be quantitatively described below.
The 3 dB bandwidth fc of a conventional APD is expressed by the above-mentioned formula (2), where the bandwidth limit due to the RC time constant is frc, the bandwidth limited by the carrier transit time is ftr, and the bandwidth limit due to the multiplication time is fm.

On the other hand, the 3 dB bandwidth f c of the APD having the InAlAs digital alloy structure multiplication layer according to the first embodiment is limited only by the RC time constant and the carrier transit time according to equations (6), (7), and (8) because the ionization rate ratio k is close to zero, and therefore can be expressed by the following equation (13).

fc_APD=1/((1/frc) ² +(1/ftr) ² ) ^0.5 (13)

In formula (13), the transit time ftr of a carrier includes the transit time through the light absorption layer plus the transit time through the multiplication layer.

Since the RC time constant is inversely proportional to the sum of the thickness of the light absorbing layer and the thickness of the multiplication layer, while the transit time is directly proportional, Equation (13) has a maximum value. That is, the maximum bandwidth occurs when frc=ftr. Substituting frc=ftr, Equation (13) is expressed by the above-mentioned Equation (3).
The 3 dB bandwidth ftr determined by the transit time is expressed by the above-mentioned formula (4).

In formula (4), Vav is the average saturation transit velocity of electrons and holes, and Wt is the total thickness of the light absorption layer and the multiplication layer. For example, in the case of InGaAs, Vav is 5.35×10 ⁶ cm/s. If the thickness of the multiplication layer is 100 nm and the thickness of the light absorption layer is 400 nm, then Wt=500 nm.

Substituting Vav=5.35×10 ⁶ cm/s and Wt=500 nm into formula (4) gives ftr=59.6 GHz. Substituting these values into formula (3) gives the 3 dB bandwidth of the APD having the InAlAs digital alloy multiplication layer according to the modified example of the second embodiment, which is 42.2 GHz. Therefore, it is clear from the above considerations that the APD having the InAlAs digital alloy multiplication layer according to the modified example of the second embodiment can meet the bandwidth of 37.5 GHz required for a 50G-PON system. In the following description of the device, system, etc., the APD having the InAlAs digital alloy electron transit layer and the InAlAs digital alloy multiplication layer according to the present disclosure is referred to as the DA-APD according to the present disclosure.

<Effects of the Modification of the Second Embodiment>
As described above, the semiconductor photodetector according to the modified example of the second embodiment further includes a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and thus has the effect of providing a semiconductor photodetector that operates over a wide bandwidth and has excellent low noise characteristics.

Embodiment 3.
Fig. 10 is a cross-sectional view showing the element structure of a front-illuminated PD which is an example of the semiconductor light receiving element 120 according to the embodiment 3. Fig. 11 is a cross-sectional view showing the element structure of a front-illuminated PD which is an example of the semiconductor light receiving element 120a according to the embodiment 3.

<Element structure of semiconductor photodetector (PD) according to the third embodiment>
The semiconductor light receiving element 120 according to the third embodiment shown in FIG. 10 includes an n-type InP substrate 1, an n-type InP buffer layer 2 having a carrier concentration of 1 to 5×10 ¹⁸ cm ^-3 and a layer thickness of 0.1 to ^1.0 μm, which are successively formed on the n-type InP substrate 1, an i-type InAlAs digital alloy structure electron transit layer ³ having a digital alloy structure in which an i-type AlAs layer (e.g., a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (e.g., a layer thickness of two atomic layers, about 0.6 nm) having a carrier concentration of 1×10 17 cm -3 or less and a layer thickness of 50 to 1000 nm are alternately laminated a plurality of times, an i-type InAlGaAs graded layer 4 having a carrier concentration of 5×10 ¹⁷ cm ^-3 or less and a layer thickness of 5 to 50 nm, and an i-type InAlGaAs graded layer 5 having a carrier concentration of 1×10 ¹⁷ cm -3 or less and a layer thickness of 5 to 50 nm. ^-3 or less and a layer thickness of 50 nm to 3.0 μm, an i-type InAlGaAs/InAlAs graded layer 6 having a carrier concentration of 5×10 ¹⁷ cm ^-3 or less and a layer thickness of 5 to 50 nm, an n-type InP window layer 11 having a carrier concentration of 5×10 ¹⁷ cm ^-3 or less and a layer thickness of 0.1 to 3.0 μm, a p-type diffusion region 15 provided in the n-type InP window layer 11, a p-type InGaAs contact layer 8 provided on the p-type diffusion region 15, an n-type electrode 31 formed on the back side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InP buffer layer 2 is also called an n-type semiconductor layer.

The semiconductor light receiving element 120a of embodiment 3 shown in Figure 11 has the same configuration as the semiconductor light receiving element 120 of embodiment 3, except that an Fe-doped semi-insulating InP substrate 1a is used as the substrate and an n-type electrode 31a is formed on the surface side of the n-type InP conductive layer 2b.

The semiconductor photodetectors 120 and 120a according to the third embodiment differ from the semiconductor photodetectors 100 and 100a according to the first embodiment in that the n-type InP constituting the n-type InP window layer 11 is undoped (i-type) or has a low carrier concentration, and in that a p-type diffusion region 15 is provided in the n-type InP window layer 11. The n-type InP window layer 11 of the semiconductor photodetectors 120 and 120a has a thickness of 0.1 μm or more and 3 μm or less, and a carrier concentration of 5×10 ¹⁷ cm ^-3 or less. The n-type InP window layer 11 may be made of InAlAs instead of InP, or may have a laminated structure of InP and InAlAs.

The p-type diffusion region 15 is formed by partially selectively diffusing a p-type dopant such as Zn in a solid or gas phase. The carrier concentration of the p-type diffusion region 15 is 5×10 ¹⁷ cm ⁻³ or more. The tip of the p-type diffusion region 15 may be located at a depth up to the middle of the n-type InP window layer 11, at a depth reaching the i-type InAlGaAs/InAlAs graded layer 6, or at a depth reaching the i-type InGaAs light absorption layer 5. In the device structure shown in FIG. 10 and FIG. 11, the p-type diffusion region 15 has a depth reaching the i-type InGaAs light absorption layer 5. A p-type InGaAs contact layer 8 is provided on the p-type diffusion region 15.

By performing Zn diffusion halfway through the i-type InGaAs light absorption layer 5, it is also possible to make a part of the i-type InGaAs light absorption layer 5 (the p-type electrode side) a p-type layer. The p-type layered part has a uni-traveling carrier (UTC) structure. In the UTC structure, only electrons that can move at high speed are supplied to the depletion layer (i-type InGaAs) among the electron-hole pairs generated by light absorption by the p-type layer (p-type InGaAs) in the i-type InGaAs light absorption layer 5, enabling high-speed response of the PD. However, if the thickness of the p-type layer in the i-type InGaAs light absorption layer 5 is increased, the efficiency decreases because the electrons generated in the p-type layer recombine. Note that the p-type InGaAs part in the i-type InGaAs light absorption layer 5 may be formed during epitaxial crystal growth instead of being made into a p-type layer as described above.

In the front-illuminated PD, which is an example of the semiconductor light receiving element 120 shown in FIG. 10, an n-type electrode 31 is provided on the back side. On the other hand, in the front-illuminated PD, which is an example of the semiconductor light receiving element 120a shown in FIG. 11, an n-type electrode 31a is provided on the front side. That is, in the semiconductor light receiving element 120a, an n-type InP conductive layer 2b is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the semiconductor layers above the n-type InP conductive layer 2b are partially removed, and then an n-type electrode 31a is formed on the n-type InP conductive layer 2b. The semiconductor light receiving element 120a may use a p-type InP substrate or an n-type InP substrate instead of the Fe-doped semi-insulating InP substrate 1a.

<Function of Semiconductor Photodetector (PD) According to Third Embodiment>
In a mesa structure such as a front-illuminated PD, which is an example of the semiconductor light-receiving element 100 according to the first embodiment shown in Fig. 1, the side portion of the multiplication layer to which an electric field is applied is exposed to the outside and is therefore prone to deterioration. In particular, when an InAlAs digital alloy structure is used as the electron transit layer, high strain is applied to each layer constituting the i-type InAlAs digital alloy structure electron transit layer 3, so that dislocation defects and disorder are likely to occur from the exposed portion toward the inside, which may result in a problem of deterioration of the semiconductor light-receiving element.

As a result, in the case of an electron transit layer in which an InAlAs digital alloy structure is thinned, as in the semiconductor light receiving elements 100 and 100a according to embodiment 1, the lifetime of the semiconductor light receiving element may be shortened due to dark current generated in the side portions compared to the conventional InAlAs random alloy structure.

On the other hand, when a p-type diffusion region 15 is provided as in the semiconductor light receiving elements 120 and 120a shown in Figures 10 and 11, the portion of the i-type InAlAs digital alloy structure electron transit layer 3 to which an electric field is applied, i.e., the portion directly below the p-type diffusion region 15, is not exposed to the outside of the crystal layer, thereby preventing deterioration and disorder in the i-type InAlAs digital alloy structure electron transit layer 3 in which each layer is highly distorted.

<Effects of Third Embodiment>
As described above, according to the semiconductor light-receiving element of the third embodiment, even though Zn diffusion is performed to form a p-type diffusion region during the formation of the element structure, it is possible to prevent disordering of the electron transit layer of the InAlAs digital alloy structure, and therefore it is possible to obtain a semiconductor light-receiving element that is highly reliable and operates over a wide bandwidth.

Embodiment 4.
Fig. 12 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 130 according to the fourth embodiment. Also, Fig. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 130a according to the fourth embodiment.

<Element structure of semiconductor photodetector (APD) according to the fourth embodiment>
The semiconductor light receiving element 130 according to the fourth embodiment includes an n-type InP substrate 1, an n-type InAlAs buffer layer 2a having a carrier concentration of 1 to 5× ¹⁰ cm ⁻³ and a thickness of 0.1 to ^1.0 μm, which are successively formed on the n-type InP substrate 1, an i-type InAlAs digital alloy structure electron transit layer ³ having a digital alloy structure in which an i-type AlAs layer (e.g., two atomic layers, about 0.6 nm thick) and an i-type InAs layer (e.g., two atomic layers, about 0.6 nm thick) having a carrier concentration of 1×10 cm−3 or less and a thickness of 50 to 1000 nm are alternately laminated a plurality of times, an n-type InAlAs electric field relaxation layer 12 having a carrier concentration of 1× ¹⁰ to 5× ¹⁰ cm ^{−3 and a thickness of 10 to 70 nm, and an n-type InAlAs buffer layer 2b having a carrier concentration of 1×10 cm−3} or less and a thickness of 50 to ¹⁰⁰⁰ nm. a p-type InP electric field relaxation layer 14 having a carrier concentration of 1×10 ¹⁶ to 5×10 ¹⁸ cm ^-3 and a thickness of 10 to 70 nm; an i-type InGaAs light absorption layer 5 having a carrier concentration of ¹ ×10 ¹⁷ cm ^-3 or less and a thickness of 50 nm to 3.0 μm; an i-type InAlGaAs/InAlAs graded layer 6 having a carrier concentration of 5×10 ¹⁷ cm ^-3 or less and a thickness of 5 to ⁵⁰ nm; The InAlAs buffer layer 2a is composed of an n-type InP window layer 11 having a thickness of 0.1 to 3.0 μm and a refractive index of ⁻³ or less, a p-type diffusion region 15 provided in the n-type InP window layer 11, a p-type InGaAs contact layer 8 provided on the p-type diffusion region 15, an n-type electrode 31 formed on the back surface side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The InAlAs buffer layer 2a is also called an n-type semiconductor layer.

The semiconductor light receiving element 130a of embodiment 4 shown in Figure 13 has the same configuration as the semiconductor light receiving element 130 of embodiment 4, except that an Fe-doped semi-insulating InP substrate 1a is used as the substrate and an n-type electrode 31a is formed on the surface side of the n-type InP conductive layer 2b.

The semiconductor photodetectors 130 and 130a according to the fourth embodiment differ from the semiconductor photodetectors 110 and 110a according to the second embodiment in that the n-type InP constituting the n-type InP window layer 11 is undoped (i-type) or has a low carrier concentration, and in that a p-type diffusion region 15 is provided in the n-type InP window layer 11. The n-type InP window layer 11 of the semiconductor photodetectors 120 and 130 has a layer thickness of 0.1 μm or more and 3 μm or less, and a carrier concentration of 5×10 ¹⁷ cm ^-3 or less. The n-type InP window layer 11 may be made of InAlAs instead of InP, or may have a laminated structure of InP and InAlAs.

The p-type diffusion region 15 is formed by partially selectively diffusing a p-type dopant such as Zn in a solid or gas phase. The carrier concentration of the p-type diffusion region 15 is 5×10 ¹⁷ cm ⁻³ or more. The tip of the p-type diffusion region 15 may be located at a depth up to the middle of the n-type InP window layer 11, at a depth reaching the i-type InAlGaAs/InAlAs graded layer 6, or at a depth reaching the i-type InGaAs light absorption layer 5. In the device structure shown in FIG. 12 and FIG. 13, the p-type diffusion region 15 has a depth reaching the i-type InAlGaAs/InAlAs graded layer 6. A p-type InGaAs contact layer 8 is provided on the p-type diffusion region 15.

In the front-illuminated APD, which is an example of the semiconductor light receiving element 130 shown in FIG. 12, an n-type electrode 31 is provided on the back side. On the other hand, in the front-illuminated APD, which is an example of the semiconductor light receiving element 130a shown in FIG. 13, an n-type electrode 31a is provided on the front side. That is, in the semiconductor light receiving element 130a, an n-type InP conductive layer 2b is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the semiconductor layers above the n-type InP conductive layer 2b are partially removed, and then an n-type electrode 31a is formed on the n-type InP conductive layer 2b. In the semiconductor light receiving element 130a, a p-type InP substrate or an n-type InP substrate may be used instead of the Fe-doped semi-insulating InP substrate 1a.

<Function of Semiconductor Photodetector (APD) According to Fourth Embodiment>
In a mesa structure such as a front-illuminated APD, which is an example of the semiconductor light-receiving element 110 according to the second embodiment shown in Fig. 3, the side portion of the multiplication layer to which an electric field is applied is exposed to the outside and is therefore prone to deterioration. In particular, when an InAlAs digital alloy structure is used as the electron transit layer, high strain is applied to each layer of the i-type InAlAs digital alloy structure electron transit layer 3, so that dislocation defects and disorder are likely to occur from the exposed portion toward the inside, which may result in a problem of deterioration of the semiconductor light-receiving element.

As a result, in the case of an electron transit layer in which an InAlAs digital alloy structure is thinned, as in the semiconductor light receiving elements 110 and 110a of embodiment 2, the lifetime of the semiconductor light receiving element may be shortened due to dark current generated in the side portion compared to the conventional InAlAs random alloy structure.

On the other hand, when a p-type diffusion region 15 is provided as in the semiconductor light receiving elements 130 and 130a shown in Figures 12 and 13, the portion of the i-type InAlAs digital alloy structure electron transit layer 3 to which an electric field is applied, i.e., the portion directly below the p-type diffusion region 15, is not exposed to the outside of the crystal layer, thereby preventing deterioration and disorder in the i-type InAlAs digital alloy structure electron transit layer 3 in which each layer is highly distorted.

<Effects of Fourth Embodiment>
As described above, according to the semiconductor photodetector of the fourth embodiment, even though Zn diffusion is performed to form a p-type diffusion region during device structure formation, disordering of the electron transit layer of the InAlAs digital alloy structure can be prevented, and therefore, an effect is achieved in which a semiconductor photodetector having high reliability, wideband operation, and excellent low noise characteristics can be obtained.

A modified example of embodiment 4.
A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the fourth embodiment, will be described below.

The semiconductor light receiving element according to the modified example of the fourth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving elements 130 and 130a according to the fourth embodiment, i.e., the InAlAs multiplication layer having a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.

The layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of embodiment 2, and therefore will not be described here.

<Function of Semiconductor Photodetector (APD) According to Modification of Fourth Embodiment>
In the semiconductor light receiving element according to the modification of the fourth embodiment, even if a high-temperature heat treatment is performed to diffuse Zn in the diffusion step for forming the p-type diffusion region 15, the i-type InAlAs digital alloy structure multiplication layer can be prevented from becoming disordered, so that the dead space length does not become shorter as shown in Fig. 9C, for example, and it becomes possible to maintain a long dead space length as shown in Fig. 9B. As a result, it becomes possible to maintain the ionization rate ratio k at approximately zero, despite the Zn diffusion being performed in the manufacturing process.

<Effects of the Modification of the Fourth Embodiment>
As described above, the semiconductor photodetector according to the modified example of the fourth embodiment further has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and thus has the effect of providing a semiconductor photodetector that is highly reliable, operates over a wide bandwidth, and has excellent low noise characteristics.

Embodiment 5.
FIG. 14 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 140 according to the fifth embodiment.

<Element structure of semiconductor photodetector (APD) according to the fifth embodiment>
The front-illuminated APD, which is an example of the semiconductor photodetector 140 according to the fifth embodiment, is characterized in that, in addition to the element structure of the front-illuminated APD, which is an example of the semiconductor photodetector 130 according to the fourth embodiment, a separation groove 17 is provided along the outer periphery of the p-type diffusion region 15 formed in the n-type InP window layer 11.

The depth of the separation groove 17 is preferably in the range of 2 μm to 5 μm. The opening width of the separation groove 17 is preferably in the range of 0.5 μm to 100 μm. The bottom of the separation groove 17 reaches at least the i-type InAlAs digital alloy structure electron transit layer 3. Note that FIG. 14 shows an example in which the bottom of the separation groove 17 reaches halfway through the n-type InAlAs buffer layer 2a. The method of forming the separation groove 17 may be either dry etching or wet etching. However, it is preferable to add wet etching to remove the damaged layer caused by the dry etching after dry etching, which has excellent depth control.

The inside of the separation groove 17 and the surface of the n-type InP window layer 11 are protected by a surface protective film 18 made of an insulating film made of an oxide film such as SiN or _SiO2 . The surface protective film 18 also serves as an anti-reflective coating for the light receiving section. The thickness of the surface protective film 18 is preferably within a range of 50 nm to 5000 nm. The surface protective film 18 may also be an organic film such as benzocyclobutene (BCB).

<Function of Semiconductor Photodetector (APD) According to Fifth Embodiment>
When the electron transit layer has an InAlAs digital alloy structure, each layer of the InAlAs digital alloy structure is highly strained, so that the InAlAs digital alloy structure is easily disordered when stress is applied from the outside. Therefore, as in the semiconductor light receiving element 140 according to the fifth embodiment, by providing the separation groove 17 along the outer periphery of the p-type diffusion region 15, the stress that affects the entire wafer during the manufacturing process can be alleviated. Even in the state of individual semiconductor light receiving elements 140, the stress is alleviated by the presence of the separation groove 17, so that the stress concentration in the light receiving part at the center of the semiconductor light receiving element 140 can be alleviated. Furthermore, since the i-type InAlAs digital alloy structure electron transit layer 3 is exposed in the separation groove 17, it is desirable that the above-mentioned surface protection film 18 covers the surface of the separation groove 17. Note that a high electric field is not applied to the separation groove 17, so that it does not become a starting point of deterioration.

When a p-type diffusion region 15 is provided as in the semiconductor light receiving element 140 shown in Figure 14, the portion of the i-type InAlAs digital alloy structure electron transit layer 3 to which an electric field is applied, i.e., the portion directly below the p-type diffusion region 15, is not exposed to the outside of the crystal layer, thereby preventing deterioration in the i-type InAlAs digital alloy structure electron transit layer 3 in which each layer is highly strained.

Furthermore, because the stress is relieved by the separation groove 17 even when the semiconductor light receiving element 140 is in operation, no disorder occurs even if the semiconductor light receiving element 140 is used for a long period of time. In other words, the semiconductor light receiving element 140 of the fifth embodiment can achieve high reliability by operating in a wide band for a long period of time and maintaining low noise.

<Effects of the Fifth Embodiment>
As described above, according to the semiconductor photodetector of the fifth embodiment, even though Zn diffusion is performed to form the p-type diffusion region 15 during the formation of the device structure, it is possible to prevent disordering of the InAlAs digital alloy structure running layer, and furthermore, the presence of the separation groove can relieve stress, thereby providing an advantageous effect of providing a semiconductor photodetector that is highly reliable, operates over a wide bandwidth, and has excellent low noise characteristics.

A modified example of embodiment 5.
A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the fifth embodiment, will be described below.

The semiconductor light receiving element according to the modified example of the fifth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving element 140 according to the fifth embodiment, i.e., the InAlAs multiplication layer having a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.

The layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of embodiment 2, and therefore will not be described here.

<Function of Semiconductor Photodetector (APD) According to Modification of Fifth Embodiment>
In the semiconductor light receiving element according to the modification of the fifth embodiment, even if a high-temperature heat treatment is performed to diffuse Zn in the diffusion step for forming the p-type diffusion region 15, the InAlAs digital alloy structure multiplication layer can be prevented from becoming disordered, so that the dead space length does not become shorter as shown in Fig. 9C, for example, and it becomes possible to maintain a long dead space length as shown in Fig. 9B. As a result, it becomes possible to maintain the ionization rate ratio k at approximately zero, despite the Zn diffusion being performed in the manufacturing process.

<Effects of the Modification of the Fifth Embodiment>
As described above, the semiconductor photodetector according to the modified example of the fifth embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and can prevent disordering of the InAlAs digital alloy electron transit layer and the InAlAs digital alloy structure multiplication layer despite the Zn diffusion for forming a p-type diffusion region during the formation of the device structure. Furthermore, the presence of the separation groove can relieve stress, so that a semiconductor photodetector can be obtained which is more reliable, operates over a wide bandwidth, and has excellent low noise characteristics.

Embodiment 6.
FIG. 15 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 140a according to the sixth embodiment.

<Element structure of semiconductor photodetector (APD) according to the sixth embodiment>
While the front-illuminated APD, which is an example of the semiconductor light-receiving element 140 according to the fifth embodiment, receives light from the front side, the back-illuminated APD, which is an example of the semiconductor light-receiving element 140a according to the sixth embodiment, is characterized in that it has an element structure in which a part of the n-type electrode 31b on the back side is removed to provide an opening 33, and light is incident on the n-type InP substrate 1 through an anti-reflective coating film 35 formed so as to cover the opening 33. That is, the opening 33, which is an incident region of the incident light 90 and is covered with the anti-reflective coating film 35, is provided on the back side of the n-type InP substrate 1 facing the p-type electrode 32. In addition, the center part of the p-type InGaAs contact layer 8 is partially removed, and a surface protective film 18 made of an insulating film made of an oxide film such as SiN or SiO ₂ is formed on the exposed p-type diffusion region 15, and the surface protective film 18 is further covered with the p-type electrode 32, thereby increasing the reflectance of light from the p-type electrode 32.

In addition, since the area of the p-type diffusion region 15 can be made smaller in a back-illuminated APD such as the semiconductor light receiving element 140a than in a front-illuminated APD such as the semiconductor light receiving element 140, it is possible to further reduce the stress generated during p-type diffusion, thereby further preventing disordering of the i-type InAlAs digital alloy structure electron transit layer 3. As a result, even though Zn diffusion is performed during the formation of the element structure, disordering of the i-type InAlAs digital alloy structure electron transit layer 3 can be prevented, and the stress can be further reduced by the separation groove 17, resulting in the effect of obtaining a semiconductor light receiving element that is highly reliable, operates over a wide band, and has excellent low noise characteristics.

<Effects of Sixth Embodiment>
As described above, according to the semiconductor light receiving element of the sixth embodiment, since the element structure is a back-illuminated APD, the area of the p-type diffusion region can be made smaller than that of a front-illuminated APD, and the stress can be further alleviated by the separation groove, so that a semiconductor light receiving element having high reliability, wideband operation, and excellent low noise characteristics can be obtained. Also, as described above, since the reflectance of light from the p-type electrode 32 is increased, light that is not absorbed by the i-type InGaAs light absorbing layer 5 and transmitted therethrough is reflected by the p-type electrode 32 and returns to the i-type InGaAs light absorbing layer 5 again, so that the sensitivity is increased. As a result, the i-type InGaAs light absorbing layer 5 can be made thinner, so that the transit time of electrons and holes can be shortened, and by combining with the i-type InAlAs digital alloy structure electron transit layer 3, a semiconductor light receiving element capable of further widening the bandwidth can be obtained.

A modified example of embodiment 6.
A back-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the sixth embodiment, will be described below.

The semiconductor light receiving element according to the modified example of the sixth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the back-illuminated APD, which is an example of the semiconductor light receiving element 140 according to the sixth embodiment, i.e., the InAlAs multiplication layer having a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.

The layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of embodiment 2, and therefore will not be described here.

<Function of Semiconductor Photodetector (APD) According to Modification of Sixth Preferred Embodiment>
In the back-illuminated APD, which is an example of a semiconductor photodetector according to the modification of the sixth embodiment, like the semiconductor photodetector according to the modification of the fifth embodiment, even if a high-temperature heat treatment is performed to diffuse Zn in the diffusion step for forming the p-type diffusion region 15, disordering of the InAlAs digital alloy structure multiplication layer can be prevented. Therefore, for example, the dead space length does not become shorter as shown in FIG. 9C, and it is possible to maintain a long dead space length as shown in FIG. 9B.

<Effects of the Modification of the Sixth Embodiment>
As described above, according to the semiconductor photodetector according to the modification of the sixth embodiment, since the device structure is a back-illuminated APD, the area of the p-type diffusion region can be made smaller than that of a front-illuminated APD, and the device has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range. Even though Zn diffusion is performed to form the p-type diffusion region when the device structure is formed, disordering of the InAlAs digital alloy electron transit layer and the InAlAs digital alloy structure multiplication layer can be prevented, and further, stress can be alleviated by the presence of the separation groove. Therefore, a semiconductor photodetector having higher reliability, wider bandwidth operation, and excellent low noise characteristics can be obtained.

Embodiment 7.
Fig. 16 is a cross-sectional view showing the element structure of a front-illuminated PD which is an example of the semiconductor light receiving element 150 according to the seventh embodiment. Also, Fig. 17 is a cross-sectional view showing the element structure of a front-illuminated PD which is an example of the semiconductor light receiving element 150a according to the seventh embodiment.

<Element structure of semiconductor photodetector (PD) according to seventh embodiment>
The semiconductor light receiving element 150 according to the seventh embodiment has the same configuration as the semiconductor light receiving element 100 according to the first embodiment from the n-type InP substrate 1 to the i-type InAlGaAs/InAlAs graded layer 6, and therefore the description thereof will be omitted.

The semiconductor photodetector 150 according to the seventh embodiment shown in FIG. 16 is composed of a structure ranging from an n-type InP substrate 1 to an i-type InAlGaAs/InAlAs graded layer 6, an n-type InP window layer 11 having a layer thickness of 0.1 to 3.0 μm, a p-type InAlAs conductive layer 25, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8.

The semiconductor light receiving element 150a of embodiment 7 shown in Figure 17 has the same configuration as the semiconductor light receiving element 150 of embodiment 7, except that an Fe-doped semi-insulating InP substrate 1a is used as the substrate and an n-type electrode 31a is formed on the front side of the n-type InP conductive layer 2b.

The semiconductor light receiving element 150, 150a according to the seventh embodiment differs from the semiconductor light receiving element 100 according to the first embodiment in that the p-type InAlAs conductive layer 25 formed on the n-type InP window layer 11 is formed in a mesa shape, and a p-type InGaAs contact layer 8 and a p-type electrode 32 are provided on the p-type InAlAs conductive layer 25. The n-type InP window layer 11 may have a thickness of 50 nm or more, but a thickness of 200 nm or less is preferable in order not to lengthen the carrier travel time. The conductivity type of the n-type InP window layer 11 may be undoped instead of n-type. In the case of n-type, the carrier concentration is preferably 5.0×10 ¹⁷ cm ^-3 or less.

The method of manufacturing the semiconductor light receiving element 150, 150a according to the seventh embodiment is characterized in that a p-type InAlAs conductive layer 25 is crystal-grown on an n-type InP window layer 11 by MOVPE or MBE, and then a p-type InGaAs contact layer 8 is crystal-grown, and then the p-type InAlAs conductive layer 25 is removed, leaving behind the light receiving portion.

The thickness of the p-type InAlAs conductive layer 25 is preferably 100 nm or more and 3000 nm or less. The carrier concentration of the p-type InAlAs conductive layer 25 is preferably high, that is, 5.0×10 ¹⁷ cm ^-3 or more, in order to reduce the element resistance. The p-type InAlAs conductive layer 25 may be a laminated structure of p-type InP, p-type InGaAs, p-type InGaAsP, or p-type InAlGaAs instead of p-type InAlAs.

Also, while the semiconductor light receiving element 150 shown in Fig. 16 has an n-type electrode 31 on the back side, the semiconductor light receiving element 150a shown in Fig. 17 has an n-type electrode 31a on the front side. In other words, in the semiconductor light receiving element 150a, an n-type InP conductive layer 2b is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the layers above the n-type InP conductive layer 2b are partially removed, and then an n-type electrode 31a is formed on the n-type InP conductive layer 2b. Instead of the Fe-doped semi-insulating InP substrate 1a, a p-type InP substrate or an n-type InP substrate may be used.

<Function of Semiconductor Photodetector (PD) According to Seventh Embodiment>
The operation of the semiconductor light receiving elements 150 and 150a according to the seventh embodiment will be described below.
When forming the p-type InAlAs conductive layer 25 to which a voltage is applied, the p-type diffusion process involving a heat treatment at a high temperature of 400° C. or more is not performed, as compared with the semiconductor light receiving element 120 according to the third embodiment shown in FIG. 10, and therefore the disordering of the i-type InAlAs digital alloy structure electron transit layer 3 can be prevented. This makes it possible to maintain a high carrier transit speed in the i-type InAlAs digital alloy structure electron transit layer 3. On the other hand, as in the third embodiment, the light absorption layer region directly below the light receiving part to which a high electric field is applied is separated from the side part of the element, so that the semiconductor light receiving element can be highly reliable. Therefore, it is possible to achieve both high sensitivity and high reliability of the semiconductor light receiving element. In other words, a semiconductor light receiving element, that is, a PD, with excellent reliability can be obtained.

<Effects of the Seventh Embodiment>
As described above, according to the semiconductor photodetector of the seventh embodiment, as in the semiconductor photodetector of the third embodiment, the electron transit layer is separated from the side portion of the element, and therefore high reliability can be obtained, and therefore a semiconductor photodetector that is highly reliable and operates over a wide bandwidth can be obtained.

Embodiment 8.
Fig. 18 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 160 according to the eighth embodiment. Also, Fig. 19 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 160a according to the eighth embodiment.

<Element structure of semiconductor photodetector (APD) according to embodiment 8>
The semiconductor light receiving element 160 according to the eighth embodiment has the same configuration as the semiconductor light receiving element 110 according to the second embodiment from the n-type InP substrate 1 to the i-type InAlGaAs/InAlAs graded layer 6, and therefore the description thereof will be omitted.

The semiconductor photodetector 160 according to the eighth embodiment shown in FIG. 18 is composed of a structure ranging from an n-type InP substrate 1 to an i-type InAlGaAs/InAlAs graded layer 6, an n-type InP window layer 11 having a thickness of 0.1 to 3.0 μm, a p-type InAlAs conductive layer 25, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8.

The semiconductor light receiving element 160a of embodiment 8 shown in Figure 19 has the same configuration as the semiconductor light receiving element 160 of embodiment 8, except that an Fe-doped semi-insulating InP substrate 1a is used as the substrate and an n-type electrode 31a is formed on the front side of the n-type InP conductive layer 2b.

The semiconductor light receiving element 160, 160a according to the eighth embodiment differs from the semiconductor light receiving element 110 according to the second embodiment in that the p-type InAlAs conductive layer 25 formed on the n-type InP window layer 11 is formed in a mesa shape, and a p-type InGaAs contact layer 8 and a p-type electrode 32 are provided on the p-type InAlAs conductive layer 25. The n-type InP window layer 11 may have a thickness of 50 nm or more, but a thickness of 200 nm or less is preferable in order not to lengthen the carrier travel time. The conductivity type of the n-type InP window layer 11 may be undoped instead of n-type. In the case of n-type, the carrier concentration is preferably 5.0×10 ¹⁷ cm ^-3 or less.

The method of manufacturing the semiconductor light receiving element 160, 160a according to the eighth embodiment is characterized in that a p-type InAlAs conductive layer 25 is crystal-grown on an n-type InP window layer 11 by MOVPE or MBE, and then a p-type InGaAs contact layer 8 is crystal-grown, and then the p-type InAlAs conductive layer 25 is removed, leaving the light receiving portion.

The thickness of the p-type InAlAs conductive layer 25 is preferably 100 nm or more and 3000 nm or less. The carrier concentration of the p-type InAlAs conductive layer 25 is preferably high, that is, 5.0×10 ¹⁷ cm ^-3 or more, in order to reduce the element resistance. The p-type InAlAs conductive layer 25 may be a laminated structure of p-type InP, p-type InGaAs, p-type InGaAsP, or p-type InAlGaAs instead of p-type InAlAs.

Also, while the semiconductor light receiving element 160 shown in Fig. 18 has an n-type electrode 31 on the back side, the semiconductor light receiving element 160a shown in Fig. 19 has an n-type electrode 31a on the front side. That is, in the semiconductor light receiving element 160a, an n-type InP conductive layer 2b is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the layers above the n-type InP conductive layer 2b are partially removed, and then an n-type electrode 31a is formed on the n-type InP conductive layer 2b. Instead of the Fe-doped semi-insulating InP substrate 1a, a p-type InP substrate or an n-type InP substrate may be used.

<Function of Semiconductor Photodetector (APD) According to Eighth Embodiment>
The operation of the semiconductor light receiving elements 160 and 160a according to the eighth embodiment will be described below.
When forming the p-type InAlAs conductive layer 25 to which a voltage is applied, the p-type diffusion process involving a heat treatment at a high temperature of 400° C. or more is not performed, as compared with the semiconductor light receiving element 130 according to the fourth embodiment shown in FIG. 12, and therefore the disordering of the i-type InAlAs digital alloy structure electron transit layer 3 can be prevented. This makes it possible to maintain a high carrier transit speed in the i-type InAlAs digital alloy structure electron transit layer 3. On the other hand, as in the fourth embodiment, the light absorption layer region directly below the light receiving part to which a high electric field is applied is separated from the side part of the element, so that the semiconductor light receiving element can be highly reliable. Therefore, it is possible to achieve both high sensitivity and high reliability of the semiconductor light receiving element. In other words, a semiconductor light receiving element with excellent reliability, that is, an APD, can be obtained.

<Effects of the Eighth Embodiment>
As described above, according to the semiconductor photodetector of the eighth embodiment, like the semiconductor photodetector of the fourth embodiment, the electron transit layer is separated from the side portion of the element, and therefore, an effect is achieved in that a semiconductor photodetector having high reliability, wideband operation, and excellent low noise characteristics is obtained.

A modified example of embodiment 8.
A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the eighth embodiment, will be described below.

The semiconductor light receiving element according to the modified example of the eighth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving element 160, 160a according to the eighth embodiment, i.e., the InAlAs multiplication layer having a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.

The layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of embodiment 2, and therefore will not be described here.

<Function of Semiconductor Photodetector (APD) According to Modification of Eighth Embodiment>
A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modified example of embodiment 8, can maintain a long dead space length as shown in FIG. 9B, for example, without shortening the dead space length as shown in FIG. 9C, similarly to the semiconductor light-receiving element according to the modified example of embodiment 2.

<Effects of the Modification of the Eighth Embodiment>
As described above, the semiconductor photodetector according to the modified example of the eighth embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and therefore has the effect of providing a semiconductor photodetector which is more reliable, operates over a wide bandwidth, and has excellent low noise characteristics.

Embodiment 9.
FIG. 20 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 170 according to the ninth embodiment.

<Element structure of semiconductor photodetector (APD) according to the ninth embodiment>
The front-illuminated APD, which is an example of the semiconductor light-receiving element 170 according to the ninth embodiment, is characterized in that a separation groove 17 is further provided along the outer periphery of the p-type InAlAs conductive layer 25 in addition to the element structure of the front-illuminated APD, which is an example of the semiconductor light-receiving element 160 according to the eighth embodiment.

The depth of the separation groove 17 is preferably in the range of 2 μm to 5 μm. The opening width of the separation groove 17 is preferably in the range of 0.5 μm to 100 μm. The bottom of the separation groove 17 reaches at least the i-type InAlAs digital alloy structure electron transit layer 3. Note that FIG. 20 shows an example in which the bottom of the separation groove 17 reaches halfway through the n-type InAlAs buffer layer 2a. The method of forming the separation groove 17 may be either dry etching or wet etching. However, it is preferable to add wet etching to remove the damaged layer caused by the dry etching after dry etching, which has excellent depth control.

The inside of the separation groove 17 and the surface of the n-type InP window layer 11 are protected by a surface protective film 18 made of an insulating film made of an oxide film such as SiN or _SiO2 . The surface protective film 18 also serves as an anti-reflective coating for the light receiving section. The thickness of the surface protective film 18 is preferably within a range of 50 nm to 5000 nm. The surface protective film 18 may also be an organic film such as BCB.

<Function of Semiconductor Photodetector (APD) According to Ninth Embodiment>
When the InAlAs digital alloy structure is used as the electron transit layer, each layer of the InAlAs digital alloy structure is highly strained, so that when stress is applied from the outside, disordering is likely to occur. Therefore, as in the semiconductor light receiving element 170 according to the ninth embodiment, by providing the separation groove 17 along the outer periphery of the p-type InAlAs conductive layer 25, the stress that affects the entire wafer during the manufacturing process can be alleviated. Even in the state of individual semiconductor light receiving elements 170, the stress is alleviated by the presence of the separation groove 17, so that the stress concentration in the light receiving part at the center of the semiconductor light receiving element 170 can be alleviated. In addition, since the i-type InAlAs digital alloy structure electron transit layer 3 is exposed in the separation groove 17, it is desirable that the above-mentioned surface protection film 18 covers the surface of the separation groove 17. Note that a high electric field is not applied to the separation groove 17, so that it does not become a starting point of deterioration.

<Effects of the 9th embodiment>
As described above, according to the semiconductor photodetector of the ninth embodiment, the separation groove can relieve stress due to heat treatment and the like in the manufacturing process, and disordering of the digital alloy structure electron transit layer can be prevented. This makes it possible to maintain the ionization rate ratio k at approximately zero, and provides the effect of providing a semiconductor photodetector that is highly reliable, operates over a wide bandwidth, and has excellent low noise characteristics.

A modified example of embodiment 9.
A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the ninth embodiment, will be described below.

The semiconductor light receiving element according to the modified example of the ninth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving element 170 according to the ninth embodiment, i.e., the InAlAs multiplication layer having a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.

The layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of embodiment 2, and therefore will not be described here.

<Function of Semiconductor Photodetector (APD) According to Modification of Ninth Embodiment>
In the semiconductor light receiving element according to the modification of the ninth embodiment, it is not necessary to form the p-type diffusion region 15, that is, there is no high-temperature heat treatment required for Zn diffusion in the formation of the p-type diffusion region 15, so that the InAlAs digital alloy structure multiplication layer can be prevented from becoming disordered, and it is possible to maintain the long dead space length as shown in Fig. 9B without shortening the dead space length as shown in Fig. 9C. As a result, it is possible to maintain the ionization rate ratio k at approximately zero.

<Effects of the Modification of the Ninth Embodiment>
As described above, the semiconductor photodetector according to the modified example of the ninth embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and since high-temperature heat treatment is not required, disordering of the InAlAs digital alloy electron transit layer and the InAlAs digital alloy structure multiplication layer can be prevented. Furthermore, the presence of the separation groove can relieve stress, so that an advantageous effect is achieved in that a semiconductor photodetector can be obtained which is more reliable, operates over a wide bandwidth, and has excellent low-noise characteristics.

Embodiment 10.
FIG. 21 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 170a according to the tenth embodiment.

<Element structure of semiconductor photodetector (APD) according to the tenth embodiment>
While the front-illuminated APD, which is an example of the semiconductor light-receiving element 170 according to the ninth embodiment, receives light from the front side as shown in Fig. 20, the back-illuminated APD, which is an example of the semiconductor light-receiving element 170a according to the tenth embodiment, is characterized in that it has an element structure in which a part of the n-type electrode 31b on the back side is removed to provide an opening 33, and light is made incident on the n-type InP substrate 1 through an anti-reflective coating film 35 formed so as to cover the opening 33, as shown in Fig. 21. That is, the opening 33, which is an incident region of the incident light 90 and is covered with the anti-reflective coating film 35, is provided on the back side of the n-type InP substrate 1 facing the p-type electrode 32. In addition, the center part of the p-type InGaAs contact layer 8 is partially removed, and the surface protective film 18 made of an insulating film made of an oxide film such as SiN or SiO ₂ is formed on the exposed p-type InAlAs conductive layer 25, and the surface protective film 18 is further covered with the p-type electrode 32, thereby increasing the reflectance of light from the p-type electrode 32.

The back-illuminated APD, which is an example of the semiconductor photodetector 170a according to embodiment 10, can reduce stress due to heat treatment and the like in the manufacturing process by using a separation groove, similar to the semiconductor photodetector 170 according to embodiment 9, thereby preventing disordering of the InAlAs digital alloy structure multiplication layer.

In addition, since the area of the p-type InAlAs conductive layer 25 can be made smaller in a back-illuminated APD such as the semiconductor light receiving element 170a than in a front-illuminated APD, it is possible to further reduce the stress caused by heat treatment in the manufacturing process, and therefore the disordering of the i-type InAlAs digital alloy structure electron transit layer 3 can be further prevented. As a result, even though a heat treatment process is performed during the formation of the element structure, the disordering of the i-type InAlAs digital alloy structure electron transit layer 3 can be prevented, so that a semiconductor light receiving element with high reliability, wideband operation, and excellent low noise characteristics can be obtained. In addition, as described above, since the reflectance of light from the p-type electrode 32 is increased, light that is not absorbed by the i-type InGaAs light absorption layer 5 and transmitted is reflected by the p-type electrode 32 and returns to the i-type InGaAs light absorption layer 5 again, thereby increasing the sensitivity. As a result, the i-type InGaAs light absorption layer 5 can be made thinner, thereby shortening the transit time of electrons and holes. By combining this with the i-type InAlAs digital alloy structure electron transit layer 3, a semiconductor light receiving element capable of further broadening the bandwidth can be obtained.

In addition, in a back-illuminated APD such as the semiconductor light receiving element 170a, the area of the p-type InAlAs conductive layer 25 formed in a mesa shape can be reduced compared to that of a front-illuminated APD, so the effect of stress from the mesa portion of the p-type InAlAs conductive layer 25 is reduced, and the i-type InAlAs digital alloy structure electron transit layer 3 does not become disordered. In addition, since the stress is relaxed even during operation of the semiconductor light receiving element 170a, the i-type InAlAs digital alloy structure electron transit layer 3 does not become disordered even after a long period of time. In other words, the semiconductor light receiving element 170a according to the tenth embodiment can operate in a wide band for a long period of time and maintain low noise.

<Effects of the Tenth Embodiment>
As described above, in the semiconductor light-receiving element of the tenth embodiment, the area of the p-type conductive layer can be made small, and therefore the stress generated in the heat treatment process can be further reduced, thereby further preventing disordering of the i-type InAlAs digital alloy structure electron transit layer. In addition, the separation groove can further reduce the stress, resulting in an advantageous effect of providing a semiconductor light-receiving element that is highly reliable, operates over a wide bandwidth, and has excellent low-noise characteristics.

A modified example of embodiment 10.
A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the tenth embodiment, will be described below.

The semiconductor light receiving element according to the modified example of the tenth embodiment is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving element 170a according to the tenth embodiment, i.e., the InAlAs multiplication layer having a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.

The layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of embodiment 2, and therefore will not be described here.

<Function of Semiconductor Photodetector (APD) According to Modification of Tenth Embodiment>
In the semiconductor light receiving element according to the modification of the tenth embodiment, it is not necessary to form the p-type diffusion region 15, that is, there is no need for high-temperature heat treatment required for Zn diffusion in the formation of the p-type diffusion region 15, so that the InAlAs digital alloy structure multiplication layer can be prevented from becoming disordered, and it is possible to maintain a long dead space length as shown in Fig. 9B without shortening the dead space length as shown in Fig. 9C. As a result, it is possible to maintain the ionization rate ratio k at approximately zero.

<Effects of the Modification of the Tenth Embodiment>
As described above, the semiconductor photodetector according to the modified example of the tenth embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and since high-temperature heat treatment is not required, disordering of the InAlAs digital alloy electron transit layer and the InAlAs digital alloy structure multiplication layer can be prevented. Furthermore, the presence of the separation groove can relieve stress, so that an advantageous effect is achieved in that a semiconductor photodetector can be obtained which is more reliable, operates over a wide bandwidth, and has excellent low-noise characteristics.

Embodiment 11.
22 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 180 according to the eleventh embodiment.

<Element structure of semiconductor photodetector (APD) according to embodiment 11>
The semiconductor light receiving element 180 according to the eleventh embodiment comprises an Fe-doped semi-insulating InP substrate 1a, and, successively formed on the Fe-doped semi-insulating InP substrate 1a, a p-type InAlGaAs contact layer 40 having a carrier concentration of 1 to 5× ¹⁰ cm ⁻³ and a layer thickness of 0.1 to 1 μm, a p-type InP conductive layer 41 having a carrier concentration of 1 to 5× ¹⁰ cm ⁻³ and a layer thickness of 0.1 to 1 μm, a p-type or low carrier concentration (5×10 ¹⁷ cm ⁻³ or less) n-type or i-type InAlGaAs/InAlAs graded layer 42, an i-type InGaAs light absorption layer 43 having a carrier concentration of 5×10 ¹⁷ cm ⁻³ or less and a layer thickness of 0.1 to 2.0 μm, and an n-type InAlGaAs/InAlAs layer 44 having a carrier concentration of 1×10 ¹⁷ cm ⁻³ to 5×10 ¹⁸ cm a p-type InP electric field relaxation layer 44 having a thickness of 10 to 100 nm, an i-type InAlAs multiplication layer 45, an n-type InAlAs electric field adjustment layer 46 having a thickness of 10 to 50 nm, an ⁱ -type InAlAs digital alloy structure electron transit layer 47 having a carrier concentration of 1×10 ¹⁷ cm ^-3 or less and a thickness of 50 to 1000 nm, the i-type AlAs layer (e.g., a thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (e.g., a thickness of two atomic layers, about 0.6 nm) being alternately laminated a plurality of times, the n-type InAlAs electric field adjustment layer 48 having a carrier concentration of 1×10 ¹⁶ to 5×10 ¹⁸ cm ^-3 and a thickness of 0.1 to 2 μm, and an n-type InAlAs field adjustment layer 49 having a carrier concentration of 1×10 ¹⁶ to 5×10 ¹⁸ cm -3 and a thickness of 0.1 to 2 μm. ^-3 and a thickness of 0.1 to 2 μm, an n-type InGaAs contact layer 50 having a carrier concentration of 5×10 ¹⁷ to 8×10 ¹⁸ cm ^-3 and a thickness of 0.1 to 2 μm, an n-type electrode 51 formed on the n-type InGaAs contact layer 50, a p-type electrode 52 formed on the p-type InAlGaAs contact layer 40, a metal film 53 formed on the back surface side of the Fe-doped semi-insulating InP substrate 1a, and an anti-reflective coating film 35 provided in an opening 33 of the metal film 53. The p-type InAlGaAs contact layer 40 and the p-type InP conductive layer 41 are also called p-type semiconductor layers. In addition, the central portion of the n-type InGaAs contact layer 50 is partially removed, and a surface protective film 18 made of an insulating film made of an oxide film such as SiN or _SiO2 is formed on the exposed n-type InAlAs conductive layer 49, and this is further covered with an n-type electrode 51, thereby increasing the reflectance of light from the n-type electrode 51.

<Method of Manufacturing Semiconductor Photodiode (APD) According to Eleventh Embodiment>
A method for manufacturing the semiconductor light receiving element 180 according to the eleventh embodiment will be described below.
Using MOVPE or MBE, a p-type InAlGaAs contact layer 40 having a carrier concentration of 1 to 5×10 ¹⁸ cm ^-3 is crystal-grown to a thickness of 0.1 to 1 μm on an Fe-doped semi-insulating InP substrate 1a. An n-type InP substrate may be used instead of the Fe-doped semi-insulating InP substrate 1a. Also, the p-type InAlGaAs contact layer 40 may be made of p-type InP, p-type InGaAsP, or p-type InGaAs instead of p-type InAlGaAs.

A p-type InP conductive layer 41 having a carrier concentration of 1 to 5×10 ¹⁸ cm ⁻³ and a thickness of 0.1 to 1 μm is grown by crystal growth on the p-type InAlGaAs contact layer 40. Here, the p-type InP conductive layer 41 may be p-type InGaAsP or p-type InAlGaAs instead of p-type InP.

Next, an i-type, n-type or p-type InAlAs layer with a small barrier against holes may be provided on the p-type InP conductive layer 41. Furthermore, after the p-type or low carrier concentration (5×10 ¹⁷ cm ^-3 or less) n-type or i-type InAlGaAs/InAlAs graded layer 42 is crystal-grown, the i-type InGaAs light absorbing layer 43 is crystal-grown to a thickness of 0.1 to 2 μm. The i-type InGaAs light absorbing layer 43 may be an n-type or p-type with a low carrier concentration (5×10 ¹⁷ cm ^-3 or less) instead of an i-type. Here, either or both of the p-type InP conductive layer 41 and the n-type InAlGaAs/InAlAs graded layer 42 are not necessarily required.

Next, the p-type InP electric field buffer layer 44 having a carrier concentration of 1×10 ¹⁷ to 5×10 ¹⁸ cm ^-3 is crystal-grown to a thickness of 10 to 100 nm. Examples of p-type dopants for the p-type InP electric field buffer layer 44 include Be, Zn, and C. The p-type InP electric field buffer layer 44 does not necessarily have to be p-type InP, and may be p-type InAlAs or a p-type InAlAs digital alloy structure.

In addition, an InAlGaAs/InAlAs graded layer having a thickness of 10 to 100 nm, such as InAlGaAs or InGaAsP, which has an intermediate band gap value, may be provided between the i-type InGaAs light absorption layer 43 and the p-type InP electric field relaxation layer 44.

An i-type InAlAs multiplication layer 45 and an n-type InAlAs field adjustment layer 46 are crystal-grown as multiplication layers on the p-type InP field relaxation layer 44. The n-type InAlAs field adjustment layer 46 is provided to prevent the electron travel speed from being saturated or the electrons from being multiplied due to an excessive electric field being applied to the i-type InAlAs digital alloy structure electron travel layer 47.

On the n-type InAlAs field adjustment layer 46, an i-type InAlAs digital alloy structure electron transit layer 47 is crystal-grown as an electron transit layer. The i-type InAlAs digital alloy structure electron transit layer 47 is composed of semiconductor layers in which an AlAs layer (layer thickness: 2 atomic layers, approximately 0.6 nm) and an InAs layer (layer thickness: 2 atomic layers, approximately 0.6 nm) are alternately stacked in this order from the Fe-doped semi-insulating InP substrate 1a side. The i-type InAlAs digital alloy structure electron transit layer 47 may be formed in the order of an InAs layer and an AlAs layer.

The number of atomic layers of each layer of the i-type InAlAs digital alloy structure electron transit layer 47 is preferably 2 to 4 atomic layers, with 2 atomic layers being optimal. The reason for this is that the thinner the atomic layer thickness of each layer is, the greater the effect of reducing the ionization rate ratio k due to the digital alloy structure.

The thickness of the i-type InAlAs digital alloy structure electron transit layer 47 is in the range of 50 nm to 1000 nm. For example, if the thickness of the i-type InAlAs digital alloy structure electron transit layer 47 is 500 nm, the AlAs layer (2 atomic layers) / InAs layer (2 atomic layers) is repeated 417 times. From FIG. 8, the dead space effect is significantly manifested at a layer thickness of 200 nm or less, so the layer thickness of the i-type InAlAs digital alloy structure electron transit layer 47 is most preferably in the range of 50 nm to 200 nm. In addition, if the layer thickness is 400 nm or less, the electron transit speed is fast at a distance of 200 nm, which is 50% or more of the layer thickness, so a large dead space effect can be obtained even in the layer thickness range of 50 nm to 400 nm.

The InAlAs digital alloy structure electron transit layer 47 may be of an i-type conductivity with a carrier concentration of 1×10 ¹⁷ cm ⁻³ or less, but may also be of a p-type or n-type conductivity with a carrier concentration of 5×10 ¹⁸ cm ⁻³ or less.

Next, the n-type InAlAs field adjustment layer 48 is crystal-grown to a thickness of 0.1 to 2 μm. Here, the n-type InAlAs field adjustment layer 48 also functions as a window layer, but is not necessarily required. The n-type InAlAs field adjustment layer 48 is a layer that adjusts the electric field at the outermost surface, and the carrier concentration is preferably in the range of 1×10 ¹⁶ to 5×10 ¹⁸ cm ^-3 . Weakening the electric field at the outermost surface has the effect of suppressing local breakdown and improving reliability.

An n-type InAlAs conductive layer 49 is grown as an n-type conductive layer, and an n-type InGaAs contact layer 50 is grown as an n-type contact layer, on the n-type InAlAs field adjustment layer 48. The n-type InAlAs conductive layer 49 and the n-type InGaAs contact layer 50 each have a thickness of 0.1 to 2 μm and a carrier ^{concentration} of 5× ^{10 cm} to 8× ¹⁰ cm.

After the crystal growth of the n-type InGaAs contact layer 50, the n-type InAlAs conductive layer 49 and the n-type InGaAs contact layer 50 are etched into a mesa shape to form a first mesa. Then, the second mesa is formed by etching the p-type InAlGaAs contact layer 40 so as to include the first mesa outside the first mesa. The second mesa does not need to reach the p-type InAlGaAs contact layer 40 as long as the i-type InGaAs light absorption layer 43 is electrically isolated. It is preferable that the distance between the first mesa and the second mesa is 1 μm or more. The first mesa may be formed after the second mesa is formed.

The p-type electrode 52 is formed on the p-type InAlGaAs contact layer 40, and the n-type electrode 51 is formed on the n-type InGaAs contact layer 50. Since the ohmic resistance of an n-type semiconductor is one order of magnitude smaller than that of a p-type semiconductor, it is not necessarily necessary to use the n-type InGaAs contact layer 50 having a small band gap, and n-type InP, n-type InGaAlAs, or n-type InGaAsP may also be used. Alternatively, a direct contact may be made with the n-type InAlAs conductive layer 49.
Through the above steps, the semiconductor light receiving element 180 according to the eleventh embodiment is completed.

<Functions and Effects of Semiconductor Photodetector (APD) According to Eleventh Embodiment>
The semiconductor light receiving element 180 of the eleventh embodiment is characterized in that the conductivity type of the semiconductor light receiving element 170a of the tenth embodiment is inverted from n type to p type and from p type to n type, and the conductivity type of the upper surface side is made n type.

A first function and effect of the semiconductor light receiving element 180 according to the eleventh embodiment will be described below.
If the i-type InAlAs digital alloy structure electron transit layer 47 is held at high temperature for a long time during epitaxial crystal growth, it may become disordered and become an InAlAs random alloy structure. In the semiconductor light receiving element 180 according to the eleventh embodiment, the total layer thickness of each semiconductor layer above the i-type InAlAs digital alloy structure electron transit layer 47 is about one-third thinner than that of the semiconductor light receiving element 170a according to the tenth embodiment. That is, in the semiconductor light receiving element 180 according to the eleventh embodiment, the crystal growth time required for epitaxially growing each remaining semiconductor layer after the i-type InAlAs digital alloy structure electron transit layer 47 is crystal grown is about one-third shorter than that of the semiconductor light receiving element 190 according to the seventh embodiment, so that the i-type InAlAs digital alloy structure electron transit layer 47 is less likely to become disordered.

A second function and effect of the semiconductor light receiving element 180 according to the eleventh embodiment will be described below.
The upper electrode of the semiconductor light receiving element, that is, the electrode on the front side, is a p-type electrode 32 in the back-illuminated APD shown in Fig. 21, and an n-type electrode 51 in the back-illuminated APD shown in Fig. 22. To increase the speed, it is necessary to reduce the electrode area of the front side electrode and reduce the electric capacitance. However, when the electrode area of the upper electrode is reduced, the contact resistance between the electrode and the semiconductor layer increases, which causes a problem that the RC time constant increases and the response band becomes narrower.

In the semiconductor light receiving element 180 according to the eleventh embodiment, the upper electrode, that is, the n-type electrode 51, is in contact with the n-type semiconductor, so that the ohmic resistance is reduced to one tenth of that of the contact between the p-type electrode and the p-type semiconductor. Therefore, the area of the n-type electrode 51 can be reduced, so that the stress from the electrode is reduced and disorder is less likely to occur in the i-type InAlAs digital alloy structure electron transit layer 47. In the above description, the case of an APD has been described as an example of the semiconductor light receiving element 180 according to the eleventh embodiment, but in the PD, for example, the semiconductor light receiving element 150 according to the seventh embodiment may have an element structure in which the conductivity type is inverted from n-type to p-type and from p-type to n-type.

<Effects of Eleventh Embodiment>
As described above, according to the semiconductor light receiving element of the eleventh embodiment, the crystal growth time required for epitaxially growing the remaining semiconductor layers after the InAlAs digital alloy structure electron transit layer is crystal grown is about one third shorter than that of the semiconductor light receiving element of the tenth embodiment, and therefore the InAlAs digital alloy structure electron transit layer is less likely to become disordered, and therefore a semiconductor light receiving element having high reliability, wideband operation, and excellent low noise characteristics can be obtained. In addition, as described above, the reflectance of light from the n-type electrode 51 is increased, so that light that is not absorbed by the i-type InGaAs light absorbing layer 43 and transmitted through the layer is reflected by the n-type electrode 51 and returns to the i-type InGaAs light absorbing layer 43, thereby increasing the sensitivity. As a result, the i-type InGaAs light absorbing layer 43 can be made thinner, so that the transit time of electrons and holes can be shortened, and by combining the i-type InAlAs digital alloy structure electron transit layer 47, a semiconductor light receiving element capable of further widening the bandwidth can be obtained.

A modified example of embodiment 11.
A front-illuminated APD and a back-illuminated APD, which are examples of semiconductor light-receiving elements according to a modification of the eleventh embodiment, will be described below.

The semiconductor light receiving element according to the modified example of embodiment 11 is structurally different in that the i-type InAlAs multiplication layer 45 in the front-illuminated APD and back-illuminated APD, which are examples of the semiconductor light receiving element 180 according to embodiment 11, i.e., the InAlAs multiplication layer with a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.

The layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of embodiment 2, and therefore will not be described here.

<Function of Semiconductor Light-Receiving Element According to Modification of Eleventh Embodiment>
In the semiconductor photodetector (APD) according to the modified example of the eleventh embodiment, the crystal growth time required for epitaxially growing the remaining semiconductor layers after the i-type InAlAs digital alloy structure multiplication layer is grown is approximately one-third shorter than that of the semiconductor photodetector 190 according to the seventh embodiment, and therefore disordering of the i-type InAlAs digital alloy structure multiplication layer is less likely to occur.

<Effects of the Modification of the Eleventh Embodiment>
As described above, the semiconductor photodetector according to the modification of the eleventh embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and the crystal growth time required for epitaxially growing the remaining semiconductor layers after the i-type InAlAs digital alloy structure multiplication layer is grown is shorter than that of an element structure having an opposite conductivity type. This prevents the InAlAs digital alloy electron transit layer and the InAlAs digital alloy structure multiplication layer from becoming disordered, thereby providing an effect of providing a semiconductor photodetector which is more reliable, operates over a wide bandwidth, and has excellent low noise characteristics.

Embodiment 12.
23 is a cross-sectional view showing the element structure of a front-illuminated type PD, which is an example of a semiconductor light-receiving element 190 according to the twelfth embodiment.

<Features of element structure (PD) of semiconductor light receiving element according to embodiment 12>
The semiconductor light receiving element 190 according to the twelfth embodiment is structurally different from the semiconductor light receiving element 100 according to the first embodiment in that an electron transit layer is provided on the p-type electrode 32 side, i.e., on the light receiving portion side, of the i-type InGaAs light absorbing layer 5. That is, from the n-type InP substrate 1 side, the i-type InGaAs light absorbing layer 5, the i-type InAlGaAs/InAlAs graded layer 6, and the i-type InAlAs digital alloy structure electron transit layer 3a are formed in this order.

The layer thickness and carrier concentration of each layer of the semiconductor light receiving element 190 in embodiment 12 are the same as those in embodiment 1, so description is omitted.

As shown in Figure 8, in the case of an InAlAs random alloy structure, the hole dead space length Dh is about 80 nm, whereas in the case of an InAlAs digital alloy structure, the hole dead space length Dh is about 170 nm. In other words, since the hole dead space length is about twice as long as the electron dead space length, holes can travel quickly with a layer thickness of 200 nm or less. Therefore, by providing an i-type InAlAs digital alloy structure hole travel layer, a broadband PD can be achieved.

<Effects of the twelfth embodiment>
As described above, the semiconductor light receiving element according to the twelfth embodiment has an InAlAs digital alloy electron transit layer, and therefore has the effect of providing a semiconductor light receiving element that operates over a wide band.

Embodiment 13.
24 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 200 according to the thirteenth embodiment.

<Features of element structure (APD) of semiconductor light receiving element according to the thirteenth embodiment>
The semiconductor light receiving element 200 according to the thirteenth embodiment is structurally different from the semiconductor light receiving element 110 according to the second embodiment in that an electron transit layer is provided on the p-type electrode 32 side, i.e., on the light receiving portion side, of the i-type InGaAs light absorbing layer 5. That is, from the n-type InP substrate 1 side, the i-type InGaAs light absorbing layer 5, the i-type InAlGaAs/InAlAs graded layer 6, and the i-type InAlAs digital alloy structure electron transit layer 3a are formed in this order.

The layer thickness and carrier concentration of each layer of the semiconductor light receiving element 200 in embodiment 13 are the same as those in embodiment 2, so description is omitted.

As shown in Figure 8, in the case of an InAlAs random alloy structure, the hole dead space length Dh is approximately 80 nm, whereas in the case of an InAlAs digital alloy structure, the hole dead space length Dh is approximately 170 nm. In other words, since the hole dead space length is about twice as long as the electron dead space length, holes can travel quickly with a layer thickness of 200 nm or less. Therefore, by inserting an i-type InAlAs digital alloy structure hole travel layer, it is possible to achieve a broadband APD.

<Effects of Thirteenth Embodiment>
As described above, the semiconductor light receiving element according to the thirteenth embodiment has an InAlAs digital alloy electron transit layer, which makes it possible to obtain a semiconductor light receiving element that operates over a wide band and has excellent low noise characteristics.

A modified example of embodiment 13.
A front-illuminated APD, which is an example of a semiconductor light-receiving element according to a modification of the thirteenth embodiment, will be described below.

The semiconductor light receiving element according to the modified example of embodiment 13 is structurally different in that the i-type InAlAs multiplication layer 13 in the front-illuminated APD, which is an example of the semiconductor light receiving element 200 according to embodiment 13, i.e., the InAlAs multiplication layer with a random alloy structure, is replaced with an i-type InAlAs digital alloy structure multiplication layer.

The layer structure and thickness of the i-type InAlAs digital alloy structure multiplication layer are similar to those of the i-type InAlAs digital alloy structure multiplication layer of the semiconductor light receiving element according to the modified example of embodiment 2, and therefore will not be described here.

<Function of Semiconductor Photodetector (APD) According to Modification of Thirteenth Embodiment>
In the semiconductor light receiving element according to the modification of the thirteenth embodiment, since an InAlAs digital alloy structure multiplication layer is adopted, it becomes possible to maintain a long dead space length as shown in Fig. 9B. As a result, it becomes possible to maintain the ionization rate ratio k at approximately zero.

<Effects of the Modification of the Thirteenth Embodiment>
As described above, the semiconductor photodetector according to the modified example of embodiment 13 has a digital alloy structure multiplication layer whose layer thickness is controlled within a preset range, and thus has the effect of providing a semiconductor photodetector that is highly reliable, operates over a wide bandwidth, and has excellent low noise characteristics.

Embodiment 14.
25 is a configuration diagram showing an optical line terminal (OLT) 260 of a 50G-PON system according to embodiment 14. The optical line terminal 260 includes an FEC 261 (Forward Error Correction: FEC), a driver amplifier 262, a light source 263, a WDM 264 (Wavelength Division Multiplexing: WDM), a CDR 265 (Clock Data Recovery: CDR) which is a clock and data recovery circuit, a limiting amplifier 266, a burst TIA 267, and a DA-APD 268 of the present disclosure. Note that the DA-PD of the present disclosure may be applied instead of the DA-APD 268 of the present disclosure.

The APD of the present disclosure refers to an APD in which the electron transit layer has an InAlAs digital alloy structure, as described in each of the above-mentioned embodiments, or an APD in which both the electron transit layer and the multiplication layer have an InAlAs digital alloy structure. Furthermore, the PD of the present disclosure refers to a PD in which the electron transit layer has an InAlAs digital alloy structure, as described in each of the above-mentioned embodiments.

26 is a configuration diagram showing an optical line terminal (ONU) 270 of a 50G-PON system according to embodiment 14. The optical line terminal 270 includes a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of the present disclosure, a TIA 276, a limiting amplifier 277, and a CDR 278.

Figure 27 is a configuration diagram showing an optical line terminal (OLT) 250a of a 50G-PON system as a comparative example. The optical line terminal 250a as a comparative example includes a forward error correction circuit FEC251 (Forward Error Correction: FEC), a driver amplifier 252, a light source 253, an optical multiplexer/demultiplexer WDM254 (Wavelength Division Multiplexing: WDM), a digital signal processing circuit DSP255, an analog-to-digital converter ADC256 (Analog-to-digital converter: ADC), a burst TIA257 (Trans Impedance Amplifier), and a conventional APD258.

As shown in the optical line terminal 250a of the 50G-PON system, which is a comparative example shown in Figure 27, the 50G-PON system, which is a comparative example, required digital bandwidth compensation, i.e., a DSP 255. On the other hand, in a 50G-PON system using the DA-APD of the present disclosure, digital bandwidth compensation is not required. In other words, by using the DA-APD of the present disclosure, that is, an APD having at least an InAlAs digital alloy structure electron transit layer, it is possible to reduce the electrical capacitance without deteriorating the bandwidth.

In order to increase the number of branches in a PON system and to eliminate the need for an SOA, it is necessary to improve the signal-to-noise ratio of the receiver and increase the receiving sensitivity. For example, if an optical demultiplexer is added to increase the number of branches from the current level, the amount of light will be halved, so the signal-to-noise ratio must be improved by at least 3 dB. The signal-to-noise ratio of a receiver using an APD is expressed by the following equation (14).

S/N ratio = ^Iph2 · ^M2 / (2q(Iph+Id) ^M2 ·F·B
+4Kb T Ft B/Rt) (14)

In equation (14), Iph is the photocurrent of the APD, M is the multiplication factor, q is the unit charge, Id is the dark current to be multiplied, F is the excess noise factor of the APD, B is the bandwidth, Kb is the Boltzmann constant, T is the absolute temperature, Ft is the noise figure of the amplifier, and Rt is the input resistance. The term on the left of the denominator represents the shot noise of the APD, and the term on the right of the denominator represents the thermal noise of the amplifier.

In order to simplify equation (14), it is assumed that Id is sufficiently smaller than Iph, and that the APD shot noise term and the amplifier thermal noise term are equal when the multiplication factor is set to maximize the SNR. If the amplifier thermal noise term is replaced with the APD shot noise term, the SNR can be expressed by the following equation (15).

SNR = Iph / (4q F B) (15)

Moreover, the excess noise factor F is given by the following equation (16).

F = M(1 - (1 - k) x ((M - 1) ² / M ² )) (16)

In the case of a conventional InAlAs random alloy structure multiplication layer, as mentioned above, it is difficult to thin the layer (to about 70 nm) to the point where the dead space effect appears due to the influence of the tunnel current, so there are no examples of its application to APDs. For this reason, the ionization rate ratio k for an unthinned InAlAs multiplication layer is set to 0.2 and the system is designed. When the ionization rate ratio k = 0.2 and the multiplication factor is 12 times, the excess noise factor F = 3.9.

On the other hand, in the 50G-PON system according to embodiment 14, an APD with an InAlAs digital alloy structure as a multiplication layer, that is, the DA-APD of the present disclosure, is applied as a semiconductor light receiving element. In the case of the InAlAs digital alloy structure multiplication layer of the present disclosure, the dead space effect works even with a layer thickness of 100 nm or more, so it can be applied to APDs. In this case, the ionization rate ratio k = 0, and when the multiplication factor is 12 times, the excess noise factor F = 1.9. Therefore, the excess noise is about half that of a conventional APD. As a result, the DA-APD of the present disclosure is applied, and the signal-to-noise ratio is improved by 3 dB.

Generally, in a 50G-PON system, inserting one stage of a 2-way splitter to increase the number of branches increases the loss by 3 dB. Therefore, by applying the DA-APD disclosed herein as a semiconductor photodetector, it becomes possible to insert one more stage of splitter into a 50G-PON system.

Figure 28 is a diagram showing the configuration of an optical line terminal (OLT) of a 50G-PON system according to embodiment 14. The optical line terminal 260a of the 50G-PON system includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a burst TIA 267, and a DA-APD 268 of the present disclosure. Note that the DA-PD of the present disclosure may be applied instead of the DA-APD 268 of the present disclosure.

29 is a diagram showing the configuration of an optical line terminal (ONU) of a 50G-PON system according to embodiment 14. The optical line terminal 260b of the 50G-PON system includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a TIA 267a, and a DA-APD 268 of the present disclosure.

The effects of the semiconductor light receiving element according to the present disclosure will be further described.
Among the DA-APDs disclosed herein, the APD having an InAlAs digital alloy structure multiplication layer controls the thickness of the multiplication layer within a predetermined range to set the ionization rate ratio k to zero, thereby making the multiplication time in formula (6) almost zero. As a result, the response band of the APD does not deteriorate even if the multiplication factor is increased. In other words, in the DA-APD disclosed herein, the band is limited only by the RC time constant and the carrier travel time, as in the case of conventional PDs. Therefore, the wide band required for the 50G-PON system is possible, and reception is possible without digital band compensation by a DSP.

In addition, when the ionization rate ratio k approaches zero, excess noise that deteriorates reception sensitivity is suppressed, making it unnecessary to amplify the optical signal using an SOA. Furthermore, even in PON systems other than 50G-PON systems, it becomes possible to achieve more branching than before. As a result, it is possible to achieve low cost and power saving for PON systems.

<Effects of Fourteenth Embodiment>
As described above, according to the optical line terminal of embodiment 14, the DA-APD or DA-PD disclosed herein is used as the semiconductor photodetector, thereby achieving the effect of obtaining an optical line terminal that can increase the transmission distance of an optical signal and reduce power consumption.

Embodiment 15.
Fig. 30 is a diagram showing a configuration of a multi-level intensity modulation transmitting/receiving apparatus 300 according to embodiment 15. Fig. 31A and Fig. 31B are diagrams showing received waveforms of the multi-level intensity modulation transmitting/receiving apparatus 300 according to embodiment 15.

The multilevel intensity modulation transmitter/receiver 300 is a multilevel intensity modulation transmitter/receiver using the PAM (Pulse Amplitude Modulation) method, which is a multilevel intensity modulation method. In the transmitter, the digital signal generated by the DSP 301 is converted to analog by the DAC 302a, amplified by the driver amplifier 303, and the light source 304 consisting of a DFB laser or EML is driven to emit an optical signal to the optical fiber cable 310.

Meanwhile, in the receiving section, the light passes through the optical fiber cable 310 and the optical system and enters the DA-APD 305, which is the semiconductor light receiving element of the present disclosure, where the optical signal is converted to a current and multiplied, and is further amplified in the Linear-TIA 306, after which it is converted to a digital signal in the ADC 302b, and signal processing is performed by the DSP 301. Note that the DA-PD of the present disclosure may be used instead of the DA-APD 305 of the present disclosure.

<Functions and Effects of the Multilevel Intensity Modulation Transmitter/Receiver According to the Fifteenth Embodiment>
In the PAM type multi-level intensity modulation transmitting/receiving device 300, not only binary signals of 1 and 0 such as NRZ (None Return to Zero) and RZ (Return to Zero), but also, for example, in PAM4 (Pulse Amplitude Modulation-4), it is necessary to receive four values with different optical signal intensities. An example of a PAM4 received waveform is shown in FIG. 31A. An index called TDECQ (Transmitter Dispersion and Eye Closure Quaternary) is used to determine whether the received waveform in PAM4 is good or bad. TDECQ is calculated by the following formula (17).

TDECQ(dB)=10·log(OMA/(6·Qt·R)) (17)

In formula (17), the optical modulation amplitude (OMA) is the total amplitude from level 0 to level 3, Qt is a value dependent on the SER (Symbol Error Rate) defined by the IEEE (Institute of Electrical and Electronics Engineers), and R is the additional noise value required to achieve the SER value. TDECQ (dB) is defined as, for example, 3 dB or less. In order to reduce TDECQ (dB),
(1) The eye opening at each level must be uniform. (2) The noise at each level must be low.

In order for the eye opening at each of the four levels, which have different optical signal strengths, to be uniform, the semiconductor light receiving element must have excellent linearity. Here, good linearity of a semiconductor light receiving element means that the photocurrent Iph increases in proportion to the optical input power Pin. In other words, even if the optical input power Pin changes, if Iph/Pin is constant, it can be said to have good linearity.

In addition, PAM needs to receive signals with low to high intensity, so it needs to have an excellent dynamic range. In other words, even if the optical input power Pin increases, if the drop in Iph/Pin is small, the dynamic range can be said to be good. As shown in the received waveform in Figure 31B, if the linearity and dynamic range deteriorate, the eye opening formed between level 2 and level 3 deteriorates.

In the case of APDs, the linearity deteriorates because, when the photocurrent increases with an increase in optical input, the number of holes and electrons traveling in the multiplication layer and the light absorption layer increases, causing a change in the electric field distribution in the multiplication layer and the light absorption layer. This phenomenon is called the space charge effect.

The inventors have studied a model of degradation of the linearity of an APD. Figures 32A and 32B are diagrams for explaining the operation of a PD when a high optical input is applied. As shown in Figure 32A, when the optical input increases and the photocurrent increases, a space charge effect acts as if a voltage drop occurs due to the series resistance and no voltage is applied to the pn junction. This voltage drop reduces the multiplication factor. This is because the generated electrons and holes affect the electric field distribution as shown in Figure 32B. The series resistance Rli that degrades the linearity of an APD is expressed by the following formula (18).

Rli = Rsc + Rd + Rlo (18)

In equation (18), Rsc is the resistance due to the space charge effect, Rd is the element resistance, and Rlo is the load resistance. Rd and the load resistance are usually several tens of Ω, but Rsc can be several hundreds of Ω or more.

The inventors have found that, when the time it takes for electrons and holes generated by light absorption to pass through the depletion layer is Td, Rsc can be expressed by the following formula (19).

Rsc=W·Td/(2εS) (19)

In equation (19), W is the thickness of the depletion layer, ε is the dielectric constant, and S is the pn junction area.
The resistance Rsc due to the space charge effect is proportional to the time it takes for electrons and holes to pass through the depletion layer, Td, so that Rsc can be reduced by increasing the speed of electrons and holes passing through to reduce Td.

In the PD and APD having at least the InAlAs digital alloy structure electron transit layer of the present disclosure, the transit time of electrons in the electron transit layer is short, so Rsc is reduced, and as a result, the eye opening becomes uniform, so that TDECQ satisfies the specified value. Furthermore, it is possible to increase the transmission distance and reduce the driving current of the transmitting laser.

Among the DA-APDs of the present disclosure, the following describes a case where an APD in which both the electron transit layer and the multiplication layer have an InAlAs digital alloy structure is used.
First, the operation of the APD at high light input will be described. FIG. 33 is a diagram for explaining the operation of the APD at high light input. When a large number of electrons and holes are generated in the multiplication layer, the electric field in the multiplication layer of the APD changes, that is, the so-called space charge effect occurs. Due to the occurrence of this space charge effect, the multiplication factor of the APD decreases and the linearity deteriorates. As described above, since the deterioration of the linearity of the APD is caused by the series resistance Rsc, it is necessary to reduce the residence time Tdm of the electrons and holes in the depletion layer. In particular, when the multiplication factor increases, the residence time Tdm in the multiplication layer increases. Tdm is the same as the so-called multiplication time, and is expressed by the following formula (20).

Residence time Tdm = multiplication time = 2πNkMτav (20)

In equation (20), N is the Emmons coefficient (which depends gently on the ionization rate ratio k), M is the multiplication factor, and τav is the average time it takes for electrons and holes to travel through the multiplication layer. The residence time Tdm excludes the one-way transit time that carriers take to traverse the multiplication layer. N is 0.55, 0.83, 1.1, and 2.0 when the ionization rate ratio k = 0.5 (InP), 0.2 (InAlAs), 0.1 (Si), and 0 to 0.001 (InAlAs digital alloy structure), respectively.

Figure 34 shows the residence time Tdm of electrons and holes for each material that makes up the multiplication layer. In the InAlAs digital alloy structure multiplication layer, the residence time Tdm within the multiplication layer is dramatically reduced. In other words, electrons and holes are quickly discharged from the multiplication layer, suppressing the space charge effect in the multiplication layer, resulting in improved linearity and dynamic range in the InAlAs digital alloy structure multiplication layer.

As a result, while the eye opening of PAM4 was non-uniform with a conventional APD as shown in Fig. 31B, the eye opening is uniform with the DA-APD disclosed herein as shown in Fig. 31A, making it possible for TDECQ to satisfy the specified value. Therefore, when the DA-APD disclosed herein is used, an APD can be used in a PAM transceiver as well, making it possible to increase the transmission distance of optical signals and reduce the drive current of the transmitting laser.

<Effects of the Fifteenth Embodiment>
As described above, according to the multi-level intensity modulation transmitting/receiving device of embodiment 15, the DA-APD or DA-PD disclosed herein is used as the semiconductor photodetector, thereby achieving the effect of obtaining a multi-level intensity modulation transmitting/receiving device that can increase the transmission distance of an optical signal and reduce power consumption.

Embodiment 16.
Fig. 35 is a schematic diagram showing the configuration of a radio on fiber system 400 (Radio on fiber: RoF) according to a sixteenth embodiment. Fig. 36 is a schematic diagram showing the configuration of a radio on fiber system 450, which is a comparative example. The radio on fiber system 400 includes a light source 401, a transmission line 402 such as an optical fiber cable, a DA-APD 403 of the present disclosure, and an antenna 404. Note that the DA-PD of the present disclosure may be used instead of the DA-APD 403 of the present disclosure.

In a radio-on-fiber system 400 according to the sixteenth embodiment, an analog electrical amplitude signal is input to a light source 401 such as an LD and converted into an optical amplitude signal. The converted optical amplitude signal is transmitted through an optical fiber cable, i.e., a transmission path 402. The transmitted optical amplitude signal is multiplied and converted into an electrical amplitude signal using a DA-APD 403 according to the present disclosure. The converted electrical amplitude signal is transmitted to an antenna 404 and radiated as a radio wave signal.

The radio-on-fiber system 400 according to the sixteenth embodiment can efficiently supply signals to the antenna 404 that is far from the electrical signal source. In addition, since no analog-to-digital or digital-to-analog conversion is performed during transmission, the system has a simple configuration and consumes little power.

<Functions and Effects of Radio-on-Fiber System According to Sixteenth Embodiment>
In the comparative example radio-on-fiber system 450 shown in FIG. 36, if the signal is attenuated during transmission through the optical fiber cable, the signal cannot be amplified by the PD 406, and therefore a sufficient radio signal cannot be emitted from the antenna.

Furthermore, when a conventional APD is used, as shown in Figures 32A and 32B, an increase in the number of electrons and holes in the multiplication layer changes the electric field distribution, causing the multiplication factor to saturate and making it impossible to ensure the dynamic range. This not only results in a failure to obtain sufficient amplitude for the electrical signal, but also in the problem of analog signal distortion. As a result, it is difficult to apply a conventional APD to a radio-on-fiber system 450 such as the comparative example.

On the other hand, in the PD and APD having at least the InAlAs digital alloy structure electron transit layer of the present disclosure used in the radio-on-fiber system 400 according to the sixteenth embodiment, the time Td for electrons and holes to pass through the depletion layer is short, so that Rsc is small. As a result, it is possible to obtain a response with good linearity over a wide dynamic range and a large current amplitude.

Furthermore, in the DA-APD403 having an electron transit layer and a multiplication layer made of an InAlAs digital alloy structure as disclosed herein, as shown in FIG. 34, the residence time Tdm of electrons and holes in the multiplication layer is short, so that changes in the electric field distribution in the multiplication layer are suppressed. As a result, a response with excellent linearity is obtained over a wide dynamic range. In other words, since the DA-APD403 disclosed herein multiplies the signal, the original signal can be reproduced and a large current amplitude can be obtained.

The multiplication factor of the DA-APD403 disclosed herein can be in the range of 1.2 to 10 times. However, as the multiplication factor increases, the signal becomes distorted, so it is desirable to use a multiplication factor in the range of 1.2 to 5 times. Furthermore, considering the loss of the optical fiber and the fact that the quantum efficiency of the APD is about 80% and not 100%, it is optimal to use a multiplication factor of 2 to 3 times to compensate for such losses.

<Effects of Sixteenth Embodiment>
As described above, according to the radio-on-fiber system of the sixteenth embodiment, the radio-on-fiber system is configured using the DA-APD or DA-PD of the present disclosure, which has the effect of making it possible to output a strong radio signal even if the optical transmission distance is long.

Embodiment 17.
37 is a schematic diagram showing a configuration of a digital coherent receiving apparatus 500 according to embodiment 17. The digital coherent receiving apparatus 500 according to embodiment 17 is characterized in that it uses the DA-APD 505a of the present disclosure. Note that the DA-PD of the present disclosure may be used instead of the DA-APD 505a of the present disclosure.

In digital coherent communication, optical signals with both phase and intensity modulated are polarization multiplexed and transmitted through optical fiber. In the digital coherent receiving device 500, the optical signal input from the optical fiber cable 501 is first polarization-separated by the polarization separator 502. After polarization separation, each polarized signal light is input to a 90-degree hybrid device 503a and a 90-degree hybrid device 503b, respectively. Meanwhile, the laser light locally emitted from the semiconductor laser 504 is separated into two signals with a phase shift of 90 degrees from each other.

The signal light and laser light are multiplexed, and the signal light is further separated into orthogonal components (I, Q) and output. The four optical signals, i.e., the orthogonal I and Q components for each polarization, totaling four optical signals, are each incident on four balanced detectors 505 arranged in 90-degree hybrid devices 503a, 503b, in which two of the DA-APDs 505a disclosed herein are connected in series as a pair. The electrical signal output from the balanced detector 505 is input to the DSP 506. The digital coherent receiving device 500 according to embodiment 17 has the above configuration.

<Function of the digital coherent receiving device according to the seventeenth embodiment>
FIG. 38A is a diagram showing waveforms of a digital coherent receiving device which is a comparative example, and FIG. 38B is a diagram showing waveforms of a digital coherent receiving device according to embodiment 17.

In conventional balanced detectors, PDs were used as semiconductor light receiving elements that receive signal light. On the other hand, the DA-APD 505a disclosed herein can multiply signals, making it possible to suppress local light. In addition, when a conventional APD is used, as shown in FIG. 33, an increase in the number of electrons and holes in the multiplication layer changes the electric field distribution, resulting in saturation of the multiplication factor and making it impossible to ensure a dynamic range. This not only results in insufficient amplitude of the electrical signal, but also in distortion of the analog signal. As a result, as shown in FIG. 38A, in the comparative example, the interval between waveforms A1 and B1 becomes narrow, and the intensity signal of the constellation waveform is distorted, making it difficult to apply an APD.

On the other hand, in the PD and APD having at least the InAlAs digital alloy structure electron transit layer of the present disclosure used in the digital coherent receiving device 500 according to embodiment 17, the time Td for electrons and holes to pass through the depletion layer is short, so Rsc is small. Since the effect of the resistance Rsc due to the space charge effect is small, a constellation waveform with excellent linearity can be obtained over a wide dynamic range.

Furthermore, in the DA-APD 505a having an electron transit layer and a multiplication layer made of an InAlAs digital alloy structure according to the present disclosure, as shown in FIG. 34, the residence time Tdm of electrons and holes in the multiplication layer is short, so that changes in the electric field distribution in the multiplication layer are suppressed. As a result, as shown in FIG. 38B, when the DA-APD 505a according to the present disclosure is used, the interval between waveform A and waveform B becomes wider, and a constellation waveform with excellent linearity over a wide dynamic range is obtained. In other words, even if a signal is multiplied by an APD, the original signal can be reproduced, and a large current amplitude can be obtained.

The multiplication factor of the DA-APD505a disclosed herein can be in the range of 1.2 to 10. However, as the multiplication factor increases, the signal becomes distorted, so it is preferable to use a multiplication factor in the range of 1.2 to 5.

<Effects of Seventeenth Embodiment>
As described above, according to the digital coherent receiving device of embodiment 17, the DA-APD or DA-PD disclosed herein is applied as a semiconductor photodetector for receiving an optical signal, and thus it is possible to reduce the drive current of the local light (laser), that is, to reduce the power consumption of the digital coherent receiving device.

Embodiment 18.
39 is a schematic diagram showing the configuration of a SPAD sensor (Single Photon Avalanche Diode) system according to embodiment 18. The SPAD sensor system 600 includes a photoelectron measurement circuit 601, a SPAD sensor 602 including the DA-APD of the present disclosure, and a quenching circuit 603.

SPADs can be used not only to count the number of photons but also as highly sensitive light-receiving elements. However, they require constant cycling from A: Quenching voltage, described below, to B: Geiger mode voltage, described below. The cycling period is on the order of nanoseconds to microseconds. If the cycling period between A: Quenching voltage and B: Geiger mode voltage can be shortened, it is possible to increase the response speed of the SPAD. In order to increase the response speed of the SPAD, it is necessary to reduce the pn junction capacitance, and it is effective to increase the thickness of the depletion layer by thickening the travel layer.

In the DA-APD having at least the InAlAs digital alloy structure electron transport layer of the present disclosure, the transport time is short even if the transport layer is made thick, so there is little deterioration in response speed. In other words, when the DA-APD of the present disclosure is used in a SPAD, it becomes possible to switch between A: Quenching voltage and B: Geiger mode voltage, which have a fast response speed, and it is possible to improve the response band of the SPAD sensor 602.

Furthermore, when the SPAD sensor system 600 uses a DA-APD5 having an electron transport layer and a multiplication layer made of the InAlAs digital alloy structure of the present disclosure, photons incident on the SPAD sensor system 600 are absorbed in the light absorption layer of the SPAD sensor 602 made of the DA-APD of the present disclosure, generating pairs of electrons and holes, and the electrons flow into the multiplication layer. An electric field about 10% higher than the avalanche breakdown electric field is applied to the multiplication layer.

This state is called the Geiger mode. In the Geiger mode, the electrons are multiplied to a level of ^106. The generated electrons flow as a current and flow into the photoelectron measurement circuit 601. If the current generated by one photon is known in advance, it is possible to count the number of photons incident on the SPAD sensor system 600.

Figure 40A is a diagram showing the multiplication characteristics of a SAPD sensor system as a comparative example, and Figure 40B is a diagram showing the multiplication characteristics of a SAPD sensor system according to embodiment 18. If an electric field equal to or greater than the avalanche breakdown electric field is continuously applied to the multiplication layer, an excess current will flow out, so the voltage applied to the SPAD sensor 602 after detecting a photon is quickly reduced to weaken the electric field of the multiplication layer. This is called quenching. In other words, as shown in the comparison of the multiplication characteristics of the SPAD sensor in Figures 40A and 40B, the voltage is lowered from B: Geiger mode voltage to A: quenching voltage to stop the chain multiplication, and then the voltage is increased again from A: quenching voltage to B: Geiger mode voltage to allow the incident photons to be received with high sensitivity.

The quenching circuit 603 that controls the voltage is classified into a passive circuit and an active circuit. In a passive circuit, when a current flows due to a photon incident on the SPAD sensor 602, a voltage drop occurs in a resistor connected in series to the SPAD sensor 602, and the voltage applied to the SPAD sensor 602 decreases. In other words, the quenching circuit 603 operates to repeatedly apply a voltage equal to or greater than the breakdown voltage and a voltage less than the breakdown voltage to the SPAD sensor 602.

<Actions and Effects of the SPAD Sensor System According to the Eighteenth Embodiment>
The SPAD sensor system 600 according to the eighteenth embodiment can be used not only for counting the number of photons but also as a highly sensitive semiconductor light receiving element. However, it is necessary to constantly repeat the voltage from B: Geiger mode voltage to A: quenching voltage. The repetition period is on the order of nanoseconds to microseconds. If the difference between A: quenching voltage and B: Geiger mode voltage can be reduced, the repetition period can be shortened and the response speed of the SPAD sensor system 600 can be increased.

In the passive quenching circuit 603, it is possible to reduce the resistance value connected in series to the SPAD sensor 602, and the response speed of the SPAD sensor 602 is increased. In addition, in the active quenching circuit 603, the voltage amplitude is reduced, so that it is possible to simplify the drive circuit and reduce power consumption, and further, it is possible to widen the response band.

The effect of using the InAlAs digital alloy structure of the present disclosure as a multiplication layer will be described below.
In the InAlAs digital alloy structure multiplication layer of the present disclosure, as shown in Figures 7A and 9B, the dead space length is long, so multiplication does not occur at low electric fields. However, as the electric field is increased, the dead space length becomes shorter, so the multiplication factor increases rapidly and leads to breakdown. In the APD of the InAlAs random alloy multiplication layer and the APD having the digital alloy InAlAs multiplication layer with a thick multiplication layer, if the voltage at which the dark current exceeds 10 μA is set as the breakdown voltage, the multiplication factor at 90% of the breakdown voltage exceeds 10 times. On the other hand, in the InAlAs digital alloy structure multiplication layer of the present disclosure, the multiplication factor at a voltage of 90% of the breakdown voltage is 10 times or less.

Because the voltage required for breakdown depends on the device structure, such as the thickness of the light absorption layer and the carrier concentration of the electric field relaxation layer, the effect is verified here using the quantifiable electric field of the multiplication layer. Note that above the reach-through voltage (approximately 12 V), the voltage applied to the SPAD sensor 602 is proportional to the electric field of the multiplication layer.

Figure 41 shows the calculated difference between the quenching electric field and the Geiger mode electric field for each material constituting the multiplication layer. It can be seen that in the InAlAs digital alloy structure multiplication layer of the present disclosure, the difference between the quenching electric field and the Geiger mode electric field of each multiplication layer is 170 kV/cm, which is particularly low. The electric field is 120 kV/cm lower than that of an InAlAs digital alloy structure multiplication layer having a superlattice structure similar to the InAlAs digital alloy structure multiplication layer of the present disclosure but a layer thickness of 200 nm or more that has not been thinned.

<Effects of the eighteenth embodiment>
As described above, according to the SPAD sensor system of the eighteenth embodiment, the DA-APD of the present disclosure is used in the SPAD sensor, and therefore the difference between the quenching electric field and the Geiger mode electric field, i.e., the applied voltage difference, can be reduced, thereby achieving the effect of obtaining a SPAD sensor system that enables an improved response band, a simplified quenching circuit, and reduced power consumption.

Embodiment 19.
Fig. 42 is a diagram showing the configuration of a LIDAR (Light Detection and Ranging: LiDAR) device according to embodiment 19. Fig. 43A is a diagram showing a received waveform of an APD 700 of a LIDAR device as a comparative example, and Fig. 43B is a diagram showing a received waveform of the APD of the LIDAR device 700 according to embodiment 19.

The LIDAR device 700 according to the nineteenth embodiment includes a light source 701, a DA-APD 702 of the present disclosure, a TIA 703, and a distance measurement circuit 704. Note that the DA-PD of the present disclosure may be used instead of the DA-APD 702 of the present disclosure. The light source 701 emits pulsed light (hereinafter referred to as pulsed light) or frequency-modulated light.

In the LIDAR device 700 according to the 19th embodiment, the distance to the object 705 is calculated by measuring the time it takes for the pulsed light emitted from the light source to hit the object 705 and return to the semiconductor light receiving element. An LD or the like is used as the light source 701. To measure long distances, the amount of light from the LD needs to be increased, but for eye safety reasons, an upper limit is set for the amount of light emitted from the LD. For this reason, it is necessary to increase the sensitivity of the semiconductor light receiving element. Therefore, in the LIDAR device 700 according to the 19th embodiment, the DA-APD 702 disclosed herein is used with high amplification as the semiconductor light receiving element.

The detected light pulse is multiplied by the DA-APD 702 of the present disclosure and converted into a current pulse. It is then amplified by the TIA 703 and input to the distance measurement circuit 704, and the time when the intensity of the pulse signal exceeds a preset discrimination line is determined to be the arrival time, as shown in Figures 43A and 43B. The timing of the emission of the light pulse from the light source 701 is input as a signal to the distance measurement circuit 704, and the distance to the object 705 can be calculated by multiplying the time difference between the two by the speed of light and dividing the result by 2. A method is also used in which frequency-modulated light is emitted and the distance is calculated from the frequency difference between the emitted wave and the returning reflected wave.

<Actions and Effects of the LIDAR Device According to the Nineteenth Embodiment>
Since the reflectance of the object 705 is not necessarily high and the reflection direction varies, it is necessary to detect weak light with an APD. In a conventional APD, as shown in Fig. 43A, when the voltage is set to achieve high multiplication, the multiplication time becomes long and the current pulse width output from the APD becomes wide. In addition, the tunnel current increases, making it difficult to distinguish the light pulse. Even in a method of calculating the distance from the frequency difference between the emitted wave and the reflected wave, it becomes difficult to distinguish the frequency.

On the other hand, in the PD and APD having at least the InAlAs digital alloy structure electron transit layer of the present disclosure used in the LIDAR device 700 according to embodiment 19, the time Td for electrons and holes to pass through the depletion layer is short, so the deterioration of the response speed is small. Therefore, a highly sensitive receiver can be realized by reducing the pn junction capacitance of the APD and increasing the feedback resistance of the TIA 703. As a result, not only is it possible to measure the distance to a distant object 705, but the light output of the light source 701 can be reduced, thereby saving power and improving safety for the eyes.

Furthermore, in the DA-APD 505a having an electron transit layer and a multiplication layer made of the InAlAs digital alloy structure of the present disclosure, as described in the explanation of the operation of embodiment 1, even at a high multiplication of 20 times or more, the tunnel current does not increase, so it is easy to identify weak light. Also, as shown in FIG. 34, since the residence time in the multiplication layer is short, as shown in FIG. 43B, a current pulse with a large peak intensity is obtained, so that the identification sensitivity is high. As a result, not only is it possible to measure the distance to a distant object, but the light output of the light source can be reduced, thereby saving power and further improving safety for the eyes.

<Effects of the nineteenth embodiment>
As described above, according to the LIDAR device of embodiment 19, reflected light from an object is received by the DA-APD or DA-PD of the present disclosure, which makes it possible to measure the distance to a distant object, reduces the power consumption of the light source, and provides a LIDAR device that is also safer for the eyes.

While the present disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations.

Therefore, countless variations not illustrated are contemplated within the scope of the technology of this disclosure. For example, this includes modifying, adding, or omitting at least one component, or extracting at least one component and combining it with a component of another embodiment.

1 n-type InP substrate, 1a Fe-doped semi-insulating InP substrate, 2 n-type InP buffer layer, 2a n-type InAlAs buffer layer, 2b n-type InP conductive layer, 3, 47 i-type InAlAs digital alloy structure electron transport layer, 4 i-type InAlGaAs graded layer, 5, 43 i-type InGaAs light absorption layer, 6 i-type InAlGaAs/InAlAs graded layer, 7 p-type InP window layer, 8 p-type InGaAs contact layer, 11 n-type InP window layer, 13, 45 i-type InAlAs multiplication layer, 15 p-type diffusion region, 17 separation groove, 18 surface protection film, 20 Fe-doped semi-insulating InP buried layer, 25 p-type InAlAs conductive layer, 31, 31a, 31b, 51 n-type electrode, 32, 52 p-type electrode, 33 opening, 35 anti-reflective coating film, 40 p-type InAlGaAs contact layer, 41 p-type InP conductive layer, 42 i-type InAlGaAs/InAlAs graded layer, 14, 44 p-type InP field relaxation layer, 46 n-type InAlAs field adjustment layer, 48 n-type InAlAs field adjustment layer, 49 n-type InAlAs conductive layer, 50 n-type InGaAs contact layer, 53 metal film, 90 incident light, 100, 100a, 110, 110a, 120, 120a, 130, 130a, 140, 140a, 150, 150a, 160, 160a, 170, 170a, 180, 190, 200 Semiconductor light receiving element, 250a, 260, 260a, 260b, 270 Optical line terminal, 251, 261, 274 FEC, 252, 262, 273, 303 Driver amplifier, 253, 263, 272, 304, 401, 701 Light source, 254, 264, 271 WDM, 255, 265a, 301, 506 DSP, 256, 266a, 302b ADC, 258 APD, 257, 267 Burst TIA, 265, 278 CDR, 266, 277 Limiting amplifier, 267a, 276, 703 TIA, 268, 275, 305, 403, 505a, 702 DA-APD, 300 Multilevel intensity modulation transmitter/receiver, 302a DAC, 310, 501 Optical fiber cable, 306 Linear-TIA, 400, 450 Optical fiber radio system, 402 Transmission line, 404 Antenna, 406 PD, 500 Digital coherent receiver, 501 Optical fiber cable, 502 Polarization separator, 503a, 503b 90-degree hybrid device, 504 Semiconductor laser, 505 Balanced detector, 600 SPAD sensor system, 601 Optoelectronic measurement circuit, 602 SPAD sensor, 603 Quenching circuit, 700 Lidar device, 704 Distance measurement circuit, 705 Object

Claims (19)

An InP substrate;
an n-type semiconductor layer formed on the InP substrate;
an i-type electron transit layer having a digital alloy structure formed on the n-type semiconductor layer;
an n-type electric field relaxation layer formed on the i-type electron transport layer;
an i-type multiplication layer formed on the n-type electric field buffer layer;
a p-type electric field buffer layer formed on the i-type multiplication layer;
a light absorbing layer formed on the p-type electric field buffer layer;
A semiconductor light receiving element comprising: The semiconductor light-receiving element according to claim 1, characterized in that the digital alloy structure is formed by stacking two types of semiconductor layers, each made of a different semiconductor material, alternately at a period of two to six atomic layers. 3. The semiconductor light-receiving element according to claim 2 , wherein the two kinds of semiconductor layers are any combination of an InAs layer and an AlAs layer, an InAlAs layer and an InGaAs layer, or InGaAlAs layers having different composition ratios. 2. The semiconductor light-receiving element according to claim 1, wherein the i-type multiplication layer has a digital alloy structure and a thickness of the i-type multiplication layer is 60 nm or more and 130 nm or less. 5. The semiconductor light-receiving element according to claim 1, wherein the n-type semiconductor layer is an n-type conductive layer, and an n-type electrode is provided on a portion of the n - type conductive layer formed on the InP substrate that is partially exposed. 5. The semiconductor light-receiving element according to claim 1, wherein an i-type or n-type window layer is formed on the light absorption layer, a p-type impurity diffusion region is formed at least inside the window layer, and a p-type electrode is provided on an upper portion of the p-type impurity diffusion region. 7. The semiconductor light-receiving element according to claim 6 , wherein an isolation groove is provided on an outer periphery of the p-type impurity diffusion region, the isolation groove reaching the n-type semiconductor layer. 7. The semiconductor light-receiving element according to claim 6 , wherein a light incidence area is provided on a rear surface of said InP substrate opposite to said p-type electrode. An InP substrate;
a p-type semiconductor layer formed on the InP substrate;
a light absorbing layer formed on the p-type semiconductor layer;
a p-type electric field relaxation layer formed on the light absorption layer;
an i-type multiplication layer formed on the p-type electric field buffer layer;
an n-type electric field buffer layer formed on the i-type multiplication layer;
an i-type electron transit layer having a digital alloy structure formed on the n-type electric field buffer layer;
A semiconductor light receiving element comprising: The semiconductor light-receiving element according to claim 9 , characterized in that the digital alloy structure is formed by stacking two types of semiconductor layers, each made of a different semiconductor material, alternately at a period of two to six atomic layers. 11. The semiconductor light-receiving element according to claim 10 , wherein the two kinds of semiconductor layers are any combination of an InAs layer and an AlAs layer, an InAlAs layer and an InGaAs layer, or InGaAlAs layers having different composition ratios. 10. The semiconductor light-receiving element according to claim 9 , wherein the i-type multiplication layer has a digital alloy structure and a thickness of the i-type multiplication layer is 60 nm or more and 130 nm or less. A semiconductor light receiving element according to any one of claims 1 to 4 and 9 to 12 ,
an optical multiplexer/demultiplexer that inputs an optical signal to the semiconductor light receiving element;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
a clock data recovery circuit connected to the amplifier circuit and configured to recover clock data from the amplified electrical signal;
a forward error correction circuit connected to the clock data recovery circuit for correcting an error in the clock data;
An optical line terminal comprising: A semiconductor light receiving element according to any one of claims 1 to 4 and 9 to 12 ,
an optical multiplexer/demultiplexer that inputs an optical signal to the semiconductor light receiving element;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
an analog/digital conversion circuit connected to the amplifier circuit and converting the amplified electrical signal into a digital signal;
a digital signal processing circuit connected to the analog/digital conversion circuit and processing the digital signal;
a forward error correction circuit connected to the digital signal processing circuit for correcting errors in the digital signal;
An optical line terminal comprising: A semiconductor light receiving element according to any one of claims 1 to 4 and 9 to 12 , which receives a multi-level intensity modulated optical signal;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
an analog/digital conversion circuit connected to the amplifier circuit and converting the amplified electrical signal into a digital signal;
a digital signal processing circuit connected to the analog/digital conversion circuit and processing the digital signal;
A multilevel intensity modulation transmitting/receiving device comprising: a light source that emits an analog modulated optical signal;
A semiconductor light receiving element according to any one of claims 1 to 4 and 9 to 12 , which receives the optical signal that has been analog-modulated;
a transmission path for transmitting an analog electrical signal output from the semiconductor light receiving element to an antenna;
an antenna connected to the transmission line and configured to radiate the analog electrical signal as a radio wave signal;
A radio-on-fiber system comprising: A semiconductor light receiving element according to any one of claims 1 to 4 and 9 to 12 ,
a polarization splitter that splits the polarization of the intensity- and phase-modulated polarization multiplexed optical signal;
a 90-degree hybrid that splits and combines the optical signals output from the polarization splitter;
a digital signal processing circuit connected to the 90-degree hybrid device and processing a digital signal;
A digital coherent receiving device comprising: A SPAD sensor including a semiconductor light receiving element according to any one of claims 1 to 4 and 9 to 12 ;
a quenching circuit for repeatedly applying a voltage equal to or greater than a breakdown voltage and a voltage equal to or less than the breakdown voltage to the SPAD sensor;
an optoelectronic measurement circuit for measuring an electrical signal output from the SPAD sensor;
A SPAD sensor system comprising: a light source that emits pulsed or frequency modulated light;
a semiconductor light receiving element according to any one of claims 1 to 4 and 9 to 12 , which receives light emitted from the light source and reflected by an object;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
a distance measuring circuit for calculating a distance based on the electrical signal amplified by the amplifier circuit;
A lidar device comprising:

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