TW201947240A - Method of compensating offsets for chips - Google Patents

Abstract

The present invention relates to a method of compensating offsets for chips. Multiple chips are respectively mounted on a first carrier according to a first coordinates, and then an offset and offset direction of each chip on the first carrier at an environment with high temperature are measured. The first coordinates is amended to a third coordinates according to the offset and offset direction of the corresponding chip. The chips or new chips are respectively mounted on a second carrier and then the second carrier with the chips are placed in the environment with high temperature. Therefore, the offset of each chip on the second carrier is compensated. A probe accurately aligns and touches each chip on the second carrier to decrease measurement errors caused by chip's offset at the environment with high temperature.

Description

Wafer offset compensation method

The present invention relates to a method for compensating an offset, and more particularly to a method for compensating an offset of a wafer.

In the step of dicing the wafer in the semiconductor packaging process, a plurality of wafers are formed after the wafer is diced; then, the plurality of wafers are rearranged and adhered to a carrier board (hereinafter referred to as a patch) according to a preset coordinate position, and the preparation is performed. A high temperature test step.

After the carrier board and the plurality of wafers on the carrier board are sent to a high-temperature test environment, the high-temperature characteristic test can be performed on each wafer. Because there is an adhesive layer between the plurality of wafers and the carrier board, the adhesive layer has thermal softening characteristics. As a result, the positions of the plurality of wafers are shifted. It is further observed that the position deviation amount and direction of the wafer are not fixed, and there is no regularity and divergence. There is no overall rule to perform offset compensation in accordance with.

In a high-temperature environment, the high-temperature test probe contacts various wafers for high-temperature testing according to the preset coordinate position of the patch; however, because the position of the wafer is usually offset, the probe cannot properly contact the wafer, resulting in abnormal testing. It is necessary to further propose solutions to improve the accuracy of high temperature testing.

In view of the problem that the test wafer is abnormal due to position shift in a high-temperature test environment, the main object of the present invention is to provide a method for compensation of the chip shift amount to improve the result that the probe cannot contact the test due to the chip position shift. Test anomalies.

The main technical means used to achieve the above purpose is to make the wafer offset compensation method include: (a) Prepare a first carrier board, and perform the first patch according to the first coordinate position at normal temperature, so that The plurality of first wafers are respectively adhered to a first coordinate position corresponding to the first carrier board; (b) the first carrier board and the first wafers thereon are placed in a high temperature environment; (c) in Measuring a second coordinate position of each of the first wafers on the first carrier plate in a high temperature environment; (d) calculating a difference between the first coordinate position and the second coordinate position of each first wafer to obtain each of the Offset and direction of the first wafer; (e) Calculate a third coordinate position of each first wafer; wherein the third coordinate position is based on the offset of each first wafer on the first carrier. The coordinate position after the first coordinate position is compensated by its offset in the opposite direction; and (f) preparing a second carrier board and performing a second paste at normal temperature based on the third coordinate position Tablets were tested in the same high temperature environment.

It can be known from the above description that the present invention is mainly sent to a high-temperature environment after the first placement, to measure the offset amount and direction of each first wafer in the high-temperature environment, and then adjust the first of each wafer accordingly. The coordinate position is used as the second patch to adjust the coordinate position of each chip arranged on the second carrier; so when the second patch is completed and enters a high temperature environment, the offset of each wafer is compensated for high temperature testing Correctly contact each of the wafers with a probe to reduce test abnormalities caused by wafer offset.

The present invention is a method for offset compensation for a semiconductor packaging process in which a wafer is abnormal due to a positional shift in a high-temperature test environment. The technical content of the method for offset compensation of a wafer is described with reference to the embodiments and the drawings.

First, referring to FIG. 1A to FIG. 1D, a plurality of first batches of wafers (hereinafter referred to as first wafers 11) are formed after slicing a wafer 10, and each of the first wafers 11 is picked up by a vacuum suction member 50. According to the first coordinate position P11 (X11, Y11) corresponding to the first wafer 11 being picked up, the first wafer 11 is stuck on the first carrier plate 20; and so on until the last one picked up The first chip 11 is adhered to the first carrier plate 20 according to its corresponding first coordinate position P1n (X1n, Y1n), that is, the first patch of the first carrier plate 20 is completed; in this embodiment, the first A carrier plate 20 is provided with a first adhesive layer 21 for adhering the first wafers 11.

Please refer to FIG. 2A and FIG. 2B, which are top views of the first carrier plate 20 after the first placement, and then four adjacent first wafers 11a, 11b, 11c, and 11d are used to describe the wafer of the present invention. Offset compensation method; the first coordinate positions on which the first wafers 11a, 11b, 11c, 11d completed at room temperature based on the first coordinates are P _1i , P _1j , P _1k , P _1q , And a gap D is maintained between any two adjacent first wafers 11a / 11b, 11c / 11d, 11a / 11c, 11b / 11d.

Referring to FIG. 3A, the first carrier board 20 and the first wafers 11a, 11b, 11c, and 11d thereon are sent into a high-temperature test environment. Because the adhesive layer has thermal softening characteristics, each of the first The position of a wafer 11a, 11b, 11c, 11d is shifted, that is, from the first coordinate positions P _1i , P _1j , P _1k , P _1q to the second coordinate positions P _2i , P _2j , P _2k , P _2q ; The first coordinate positions P _1i , P _1j , P _1k , P _1q and the second coordinate positions P _2i , P _2j , P _2k , and P _{2q of} each of the first wafers 11a, 11b, 11c, and 11d are further calculated. Offsets (dx, dy) and offset directions of the first wafers 11a, 11b, 11c, and 11d in a high-temperature test environment; a worst case is assumed here, that is, the upper left first wafer 11a is lowered to the right The maximum offsets dx / dmax, dy / dmax are shifted to the right and down respectively, and the first wafer 11b at the top right is shifted to the left and bottom, respectively, and the maximum offsets dx / dmax, dy / dmax are moved to the left and down, respectively. , The first right wafer 11c in the lower right direction is shifted to the right and the upper direction by the maximum shift amounts dx / dmax and dy / dmax, respectively, and the first left wafer 11c is in the left direction. Maximum offset shift direction dx / dmax, dy / dmax respectively. In this embodiment, in order to ensure that adjacent first wafers 11a, 11b, 11c, and 11d do not collide with each other during the offset process, the distance D between two adjacent first wafers 11 at room temperature shown in FIG. 2B is greater than The maximum offset dmax is more than twice.

Since the offsets and directions of the first wafers 11a, 11b, 11c, and 11d after the high temperature test have been calculated, the offsets and offsets of the first wafers 11a, 11b, 11c, and 11d can be calculated. Move the direction, and update the first coordinate positions P _1i , P _1j , P _1k , P _1q corresponding to the first wafers 11a, 11b, 11c, and 11d to the third coordinate positions P _3i , P _3j , P _3k , P _3q ; then, the first wafers 11 a, 11 b, 11 c, and 11 d on the first carrier board 20 can be rearranged on a second carrier board according to the third coordinate positions P _3i , P _3j , P _3k , and P _3q 30, as shown in FIG. 3B, the second placement is performed; in addition, the second wafer 11 'cut from the same batch of the same wafer can also be used, that is, as shown in FIG. 4A, the second wafers 11' are based on The third coordinate position is rearranged on the second carrier plate 30. The second carrier plate 30 is also provided with a second adhesive layer 31 for adhering the first wafer 11 or the second wafer 11 '. In this embodiment, the material and dimensions of the second carrier board and the first carrier board are the same.

Referring to FIG. 3B again, the third coordinate position P _3i of the upper left wafer 11a is from the first coordinate position P _1i and is moved to the left and upward by the opposite direction (upper left) of the high temperature offset direction (lower right). The offset depends on the third coordinate position P _3j of the upper right wafer 11b from the first coordinate position P _1j and its high temperature offset direction (lower left) is opposite to the upper direction (upper right) and its offset is shifted to the right and upward The third coordinate position P _3k of the lower left wafer 11c is from the original first coordinate position P _1k , and its offset is shifted to the left and down by the high temperature shift direction (upper right) and the opposite direction (lower left). Depends on; the third coordinate position P _3q of the lower right wafer 11d is shifted from the first coordinate position P _1q to the right and down by the opposite direction (lower right) of its high temperature shift direction (upper left). It depends. Please refer to FIG. 4A again, which is a top plan view of the second carrier plate 30 after completing the patch according to the third coordinate position.

Because the second carrier plate 30 is also provided with a second adhesive layer 31 having the same material and size as the first adhesive layer 21, and the second carrier plate 30 after being patched is sent into the same high temperature test environment, The second adhesive layer 31 should be the same as or similar to the first adhesive layer 21 when heated and softened, so that the position of each of the second wafers 11 ′ will show an offset phenomenon as shown in FIG. 3A; 11 'has been rearranged according to the third coordinate position, so its offset can be correctly compensated, and it is arranged as shown in FIG. 4B, that is, it returns to or approaches the first coordinate position of each wafer.

In summary, the main steps of the wafer offset compensation method of the present invention include: (a) preparing a first carrier board, and performing the first patch according to the first coordinate position at normal temperature to A chip is adhered to a first coordinate position corresponding to the first carrier board; (b) the first carrier board and the first wafers on the first carrier board are put into a high temperature environment; (c) in a high temperature environment Measuring a second coordinate position of each of the first wafers on the first carrier; (d) calculating a difference between a first coordinate position and a second coordinate position of each of the first wafers to obtain each of the first Offset and offset direction of the wafer; (e) Calculate a third coordinate position of each first wafer; wherein the third coordinate position is based on the offset direction of each first wafer on the first carrier plate. The coordinate position after the first coordinate position is compensated by its offset; and (f) preparing a second carrier board and performing a second patch at normal temperature based on the third coordinate position, Tested in the same high temperature environment.

Therefore, the present invention is mainly sent to a high-temperature environment after the first placement to measure the offset amount and direction of each first wafer in the high-temperature environment, and then adjust the first coordinate position of each wafer accordingly. As the second patch, adjust the coordinate position of each of the wafers arranged on the second carrier; so when the second patch is completed and enters the high temperature environment, the offset of each wafer will be compensated for the high temperature test probe. Correctly contact each wafer to reduce test abnormalities caused by wafer shift due to high temperature.

The above description is only an embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed by the embodiments as above, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field of the art, Within the scope not departing from the technical solution of the present invention, when the above disclosed technical content can be used to make a few changes or modifications to equivalent equivalent embodiments, as long as it does not depart from the technical solution of the present invention, it is in accordance with the technical essence of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

10‧‧‧ wafer

11‧‧‧ the first chip

11’‧‧‧ second chip

20‧‧‧ the first carrier board

21‧‧‧The first adhesive layer

30‧‧‧Second carrier board

31‧‧‧Second adhesive layer

50‧‧‧Vacuum suction piece

FIGS. 1A to 1D are schematic diagrams illustrating the operation of the first carrier plate after the first placement at the next room temperature according to the present invention. FIG. 2A: a top plan view of FIG. 1D. Fig. 2B: a partially enlarged view of Fig. 2A. FIG. 3A is a schematic diagram of FIG. 2A after a part of the wafer is shifted in a high-temperature environment. FIG. 3B is a partial top plan view of the second carrier after the second patching at the normal temperature of the present invention. FIG. 4A is a top plan view of the second carrier board after the second placement at normal temperature according to the present invention. FIG. 4B is a schematic diagram of FIG. 4A after the wafer is shifted in a high-temperature environment.

Claims (10)

A wafer offset compensation method includes the following steps: (a) preparing a first carrier plate, and performing a first patch according to a first coordinate position at normal temperature, so as to respectively attach a plurality of first wafers to the first substrate; A first coordinate position corresponding to the carrier plate; (b) sending the first carrier plate and the first wafers thereon to a high temperature environment; (c) measuring the first carrier plate in a high temperature environment A second coordinate position of each of the first wafers; (d) calculating a difference between the first coordinate position and the second coordinate position of each of the first wafers to obtain an offset and an offset of each of the first wafers Direction; (e) calculating a third coordinate position of each of the first wafers; wherein the third coordinate position is opposite to the offset direction of each first wafer on the first carrier plate, The coordinate position after the first coordinate position is compensated by the shift amount; and (f) preparing a second carrier board, and performing a second patch according to the third coordinate position at normal temperature, and sending it to the same high temperature environment test. According to the wafer offset compensation method described in claim 1, the second patch of step (f) is to affix the first wafers to the corresponding third coordinate positions of the second carrier. According to the wafer offset compensation method described in claim 1, the second patch of step (f) is to stick a plurality of second wafers to the third coordinate positions corresponding to the second carrier. According to the wafer offset compensation method described in any one of claims 1 to 3, among the first wafers in step (a), a distance between two adjacent first wafers is larger than a maximum offset More than twice. The wafer offset compensation method according to any one of claims 1 to 3, wherein: the first carrier board is provided with a first adhesive layer; and the second carrier board is provided with a second adhesive layer. The wafer offset compensation method according to claim 4, wherein: a first adhesive layer is disposed on the first carrier; and a second adhesive layer is disposed on the second carrier. According to the wafer offset compensation method described in claim 5, the material and size of the first adhesive layer and the second adhesive layer are the same. According to the wafer offset compensation method described in claim 6, the material and size of the first adhesive layer and the second adhesive layer are the same. According to the wafer offset compensation method described in claim 7, the materials and dimensions of the first carrier board and the second carrier board are the same. According to the wafer offset compensation method described in claim 8, the materials and dimensions of the first carrier board and the second carrier board are the same.