TW201944477A - Semiconductor fabrication method - Google Patents

Abstract

A semiconductor fabrication method includes providing a structure substrate, wherein the structure substrate has a device region and an isolation region at a peripheral region of the device region, wherein a first stop layer and a first oxide layer are disposed over the device region and the isolation region. A second stop layer is formed on the first oxide. A second oxide layer is formed on the second stop layer. A first-stage polishing process is performed on the second oxide layer and the second stop layer to remove a portion of the second stop layer at the device region and stop at the first oxide. A second-stage polishing process is performed on the first oxide layer, stopping at the second stop layer at the isolation region and stopping at the first stop layer at the device region.

Description

Semiconductor manufacturing method

The present invention relates to semiconductor manufacturing technology, and more particularly to a semiconductor manufacturing method.

Semiconductor manufacturing technology is to manufacture electronic components and connecting wires required by a circuit on a wafer to form an integrated circuit. The transistor component is the main part of the circuit, and generally involves a large number of transistors. For example, a memory device requires a large number of memory cells. Each memory cell contains at least one transistor. These components are densely manufactured together in the planned component area. These components generally operate in the low voltage range and can also be referred to as low voltage components.

However, based on the multifunctionality of the integrated circuit, in response to the needs of some control functions, the electronic components need to operate in the high voltage range. These high-voltage components are generally located within the element area and are also located around the low-voltage components. Isolation areas are also generally located around the component area. The isolation area generally has only a simple isolation structure and does not form electronic components. The isolation structure is generally, for example, an insulating material, and more preferably, a dielectric material. That is, the element density in the isolation region will be zero or significantly smaller than the element region.

In the semiconductor manufacturing process, grinding is generally required to flatten the manufacturing working surface, which is beneficial to subsequent manufacturing. However, during the grinding process, since the area of the element with a lower density has a smaller degree of abrasion resistance, it is easier to be abraded, resulting in excessive abrasion and depression of this area. If the polished surface continues to be subjected to other subsequent processes, such as the etch-back process, the isolation area will be ground to cause sagging. Therefore, compared to the dense component area, the etch-back process will be over-etched, which may cause isolation. The structural performance is reduced, or even the manufacturing of the overall circuit fails.

How to prevent the grinding process from causing excessive grinding and sinking in a relatively low-density region is a consideration for semiconductor manufacturing technology.

The invention relates to a semiconductor manufacturing method. In an isolation region with a low element density, after a grinding process, it can effectively prevent the surface from sinking at a low element density and provide better flatness. The flat surface continues to manufacture semiconductor elements.

According to an embodiment, the present invention provides a semiconductor manufacturing method including providing a structural substrate, wherein the structural substrate has an element region and an isolation region in a peripheral region of the element region, wherein a first stop layer and a first oxide layer are disposed in the element region. And the isolation area. A second stop layer is formed on the first oxide layer. A second oxide layer is formed on the second stop layer. A first-stage polishing process is performed on the second oxide layer and the second stop layer to remove a part of the second stop layer on the element region and stop on the first oxide layer. A second-stage polishing process is performed on the first oxide layer, and the isolation region stops on the second stop layer and the element region stops on the first stop layer.

According to an embodiment, in the aforementioned semiconductor manufacturing method, wherein the structural substrate includes a silicon substrate as a base, and a plurality of gate structures are formed in the element region.

According to an embodiment, in the aforementioned semiconductor manufacturing method, the device region includes a low-voltage device region, or includes a low-voltage device region and a high-voltage device region.

According to an embodiment, in the aforementioned semiconductor manufacturing method, the first stop layer is silicon nitride, and the second stop layer is silicon nitride.

According to an embodiment, in the aforementioned semiconductor manufacturing method, the two stop layers are conformally formed on a surface of an integrated structure under the two stop layers.

According to an embodiment, in the aforementioned semiconductor manufacturing method , the second stop layer in the element region includes a recessed region located between two adjacent element structures.

According to one embodiment, in the aforementioned semiconductor manufacturing, further comprising subsequent processes, the second stage is polished flat surface polishing process is based.

According to an embodiment, in the aforementioned semiconductor manufacturing method , the step of providing the structural substrate includes providing a silicon substrate, the silicon substrate is planned with the device region and the isolation region. Forming a plurality of semiconductor elements on the silicon substrate, wherein top portions of the plurality of semiconductor elements are exposed. A polycrystalline silicon layer is formed to cover the plurality of semiconductor elements in the element region and to cover the isolation region. The first stop layer is formed on the polycrystalline silicon layer. The first oxide layer is formed on the element region and the first stop layer in the isolation region.

According to an embodiment, in the aforementioned semiconductor manufacturing method , the plurality of semiconductor elements are metal gates of a memory cell.

According to an embodiment, in the foregoing semiconductor manufacturing method , after the second-stage grinding process, an etch-back process with no selective ratio between the dielectric material and the polycrystalline silicon material is performed to expose the plurality of semiconductor elements at a predetermined height Place.

According to one embodiment, the aforementioned method of manufacturing a semiconductor, further comprising the definition of the polysilicon layer.

According to an embodiment, in the foregoing semiconductor manufacturing method , the first stop layer and the second stop layer are both silicon nitride layers deposited by atomic layers.

According to an embodiment, in the aforementioned semiconductor manufacturing method , the first-stage polishing process is controlled by operating for a fixed time.

According to an embodiment, in the aforementioned semiconductor manufacturing method , the second stop layer is nitride, and the second-stage polishing process is stopped at the second stop layer by using a polishing selection ratio of nitride to oxide.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

In the manufacture of integrated circuits, the layout of its components will include component areas and isolation areas. Semiconductor elements are densely formed in the element area. These semiconductor elements generally include some low-voltage elements with a large number, and may also include, for example, a small number of high-voltage elements. There is generally an isolation area around the element area, which may include an isolation structure. In terms of component density or component loading, the component area density will be greater than the component density in the isolation area.

Based on the manufacturing process of semiconductor devices, it generally involves a grinding process in order to obtain an overall flat surface. Based on this flat surface as a working plane, the subsequent processes continue. However, due to the lower component density in the isolation region, the material in this region is relatively easy to be removed. Therefore, after the grinding process, the isolation area will be depressed.

The present invention further investigates this phenomenon, and proposes improved technologies in response thereto. Some examples are described below, but the present invention is not limited to some examples.

1A to 1C are schematic cross-sectional structures of a general polishing process considered in accordance with the present invention. Referring to FIG. 1A, the substrate 100 generally includes a device region 50 and an isolation region 60. The isolation region 60 is around the element region 50. The element region 50 of the substrate 100 is formed with an initial element structure 102 and an insulating layer 104.

Regarding the manufacturing process of the device region 50, a dual-gate silicon-oxide-nitride-oxide-silicon (SONOS) memory structure is taken as an example. The device structure 102 is, for example, a memory gate structure including a metal gate. 108. Under the metal gate 108, there is an oxide-nitride-oxide (ONO) structure that can be used to store data as a gate insulation layer. The metal gate 108 also has a cap layer 110. The aforementioned element structure 102 is only an embodiment, but the present invention is not limited to this element structure.

Due to the design of the dual-gate architecture, it also needs to select the gate structure to operate next to the memory gate. In this way, the polycrystalline silicon layer 106 covers the substrate 100 and is formed on the gate structure 102 and the insulating layer 104. The stop layer 112, for example, silicon nitride, is formed on the polycrystalline silicon layer 106, conforms to the undulations of the upper surface structure, and is used to stop the subsequent polishing. An oxide layer 114 is also formed on the stop layer 112. The structure formed in the element region 50 may be collectively referred to as an embodiment of a structural substrate. The structure substrate may have other structures according to the semiconductor element to be manufactured, and is not limited to the embodiments described.

While the element region 50 is forming a structure, the isolation region 60 does not need to form the element structure 102. Therefore, the isolation region 60 includes, for example, a comprehensive and simultaneously deposited material stack, such as the insulating layer 104, the polycrystalline silicon layer 106, the stop layer 112, and An oxide layer 114 or the like.

Since the element region 50 includes the element structure 102, there is a undulating structure on the upper surface thereof, which is generally higher than the structure of the isolation region 60. Therefore, it is generally necessary to perform a polishing process to achieve comprehensive planarization. Referring to FIG. 1B, the polishing process polishes the oxide layer 114 to stop the stop layer 112 in the device region 50. However, the element density in the isolation region is relatively low and it is easier to be ground, resulting in a depression 116 in the isolation region 60, for example, to the extent of 200 angstroms. In this way, the overall plane after grinding is not an ideal flat surface, but does not reach a flat working surface. After carefully exploring the phenomenon, the present invention observes that at least the insufficiently flat working surface will produce adverse effects on some subsequent manufacturing processes.

In an embodiment, referring to FIG. 1C, for example, the manufacturing of a dual-gate memory cell may involve performing an etch-back process without etching selectivity on the polished working surface to expose the element structure 102. As mentioned above, the element structure 102 is exemplified by a gate structure, which needs to expose the capping layer 110. In this way, the material layer of the isolation region 60 is also etched. However, since the depression 116 caused by the grinding also continues to exist, the isolation region 60 also has the depression 118 after the etch-back process. This depression may affect the function of the isolation region 60, or more serious situations may cause damage to the isolation region 60.

After investigating the problem of polishing, the present invention also proposes a manufacturing technology that can reduce the aforementioned phenomenon.

2A to 2E are schematic cross-sectional structures of a grinding process according to an embodiment of the present invention. Referring to FIG. 2A, similar to FIG. 1A, the substrate 200 is planned with an element region 70 and an isolation region 80. The isolation region 80 is around the element region 70. The element region 70 of the substrate 200 is formed with an initial element structure 202 and an insulating layer 204. The embodiment of the insulating layer 204, for example, functions as a gate insulating layer in the following, but the present invention is not limited thereto. The insulating layer 204 is only used to indicate that a variety of foundation structures may have been formed on the substrate 200. In addition, the element region 70 may also include a high-voltage element structure 203. A high-voltage gate structure is taken as an example, but the present invention is not limited thereto.

Regarding the manufacturing process of the device region 70, a dual-gate silicon-oxide-nitride-oxide-silicon memory structure is taken as an example. The device structure 202 is, for example, a memory gate structure including a metal gate 208. Under the metal gate 208, there is an oxide-nitride-oxide (ONO) structure that can be used to store data, as a gate insulation layer. A cap layer 210 is also provided on the metal gate 208. The aforementioned element structure 202 is only an embodiment, but the present invention is not limited to this element structure.

In one embodiment, the polycrystalline silicon layer 206 covers the substrate 200 and is formed on the gate structure 202 and the insulating layer 204. The first stop layer 212 is, for example, silicon nitride, formed on the polycrystalline silicon layer 206, and conforms to the undulations of the upper surface structure, and is used to stop the subsequent polishing process in the element region 70. An oxide layer 214 is also formed on the stop layer 212.

While the element region 70 is forming a structure, the isolation region 80 does not need to form the element structure 202. Therefore, the isolation region 80 includes, for example, a comprehensive and simultaneously deposited material stack, such as an insulating layer 204, a polycrystalline silicon layer 206, a stop layer 212, and A stack of oxide layers 214 and the like.

The foregoing description is that a preliminary structure has been formed on the substrate 200, but it is not limited to the illustrated embodiment. That is, the above substrate 200 and the structures that have been manufactured on the substrate 200 may be collectively referred to as a structural substrate.

Then, the present invention continues to form a second-stage stop layer 250 on the oxide layer 214, which extends on the element region 70 and the isolation region 80. Next, an oxide layer 252 is formed on the stop layer 250 and also extends to cover the element region 70 and the isolation region 80. The second-stage stop layer 250 cooperates with the two-stage grinding method described later, which can effectively prevent the isolation region 80 from being depressed under the grinding process, and provide a flat surface of better quality as a working surface for subsequent processes.

The first two stop layers 212, 250 may be silicon nitride in one embodiment. The formation method may adopt, for example, an atomic layer deposition (Atomic layer deposition, ALD) process.

Referring to FIG. 2B, the first-stage polishing is performed first. By using the selection of the polishing liquid, in addition to the oxide polishing, the stop layer 250 can also be polished. The stop layer 250 is, for example, silicon nitride. The first stage of polishing is to expose the underlying oxide layer 214 in the element region 70. In the isolation region 80, the stop layer 250 can be maintained. Therefore, for example, a predetermined time is used to control the polishing operation time. The underlying oxide layer 214 can be stopped and exposed. However, according to an embodiment, since the portion of the stop layer 250 in the isolation region 80 has no element structure, its height will be lower than the portion of the stop layer 250 in the element region 70, so the portion of the stop layer 250 in the isolation region 80 remains.

It can be understood here that the stop layer 250 may have some residues in the deep recesses located in the element region 70 due to the undulating height caused by the element structure 202 and will not be completely removed, but this will not affect the mechanism of the present invention. The polishing at this stage is mainly to substantially remove a part of the stop layer 250 in the element region 70 to expose the surface of the oxide layer 214. In addition, a portion of the stop layer 250 in the isolation region 80 remains.

Referring to FIG. 2C, a second-stage grinding process is performed. The second stage of the polishing process utilizes the control of the polishing liquid, etc., so that the isolation region 80 can stop at the stop layer 250, and at the same time, the polishing at the element region 70 can stop at the stop layer 212, where the stop layer 250 is in the element region 70 According to the actual undulation height, there may be a small amount of residue, but it is not absolute. In an embodiment, the polishing liquid at this stage may select a component whose oxide has a higher polishing selection ratio than the nitride, thus allowing the stop layers 212, 250 to achieve the effect of stopping the polishing.

From the effect point of view, the height of the isolation region 80 is at the position of the stop layer 250, which prevents the depression in the isolation region 80. For example, a better flatness between the element region 70 and the isolation region 80 can be achieved. Best flat work surface.

In addition, as mentioned above, the stop layer 250 may still have a slight residue after the second-stage polishing in the element region 70, but it will not affect the polishing mechanism of the present invention, which can effectively reduce the problem of depression caused by excessive polishing in the isolation region 80.

Referring to FIG. 2D, the manufacturing of a dual-gate memory cell is taken as an example, similar to that described in FIG. 1C, which involves an etch-back process with a non-etch selectivity ratio on the polished working surface to expose the element structure 202, such as The cap layer 210 is exposed. Since the previous stage of polishing provides better flatness between the element region 70 and the isolation region 80, after etch-back, the element region 70 and the isolation region 80 can maintain substantially the same height. The structure in the isolation region 80 does not generate a depression, which causes performance degradation or even damage.

Referring to FIG. 2E, a subsequent process may define a polycrystalline silicon layer 206, for example, for a dual-gate memory cell, it may be a structure forming a selection gate 218. However, the present invention is not limited to the subsequent processes mentioned.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

50, 70‧‧‧ component area

60, 80‧‧‧ isolated areas

100, 200‧‧‧ substrate

102, 202‧‧‧ Element Structure

104, 204‧‧‧ Insulation

106, 206‧‧‧ polycrystalline silicon layers

108, 208‧‧‧ metal gate

110, 210‧‧‧ block layer

112, 212‧‧‧Stop level

114, 214‧‧‧ oxide layer

116, 118‧‧‧ Depression

203‧‧‧High-voltage component structure

218‧‧‧Select gate

250‧‧‧Stop level

252‧‧‧oxide

1A to 1C are schematic cross-sectional structures of a general polishing process considered in accordance with the present invention. 2A to 2E are schematic cross-sectional structures of a grinding process according to an embodiment of the present invention.

Claims (14)

A semiconductor manufacturing method includes: providing a structural substrate, wherein the structural substrate has an element region and an isolation region in a region surrounding the element region, wherein a first stop layer and a first oxide layer are disposed on the element region and the isolation region; forming A second stop layer is on the first oxide layer; a second oxide layer is formed on the second stop layer; a first-stage polishing process is performed on the second oxide layer and the second stop layer to remove the second stop layer A part of the second stop layer on the element region and stops on the first oxide layer; and performing a second-stage polishing process on the first oxide layer, and stopping on the second stop layer in the isolation region and on The element region stops on the first stop layer. The semiconductor manufacturing method according to item 1 of the scope of patent application, wherein the structural substrate includes a silicon substrate as a base, and a plurality of gate structures are formed in the element region. The semiconductor manufacturing method according to item 1 of the scope of patent application, wherein the element region includes a low-voltage element region, or includes a low-voltage element region and a high-voltage element region. According to the method of claim 1, the first stop layer is silicon nitride, and the second stop layer is silicon nitride. The semiconductor manufacturing method according to item 1 of the scope of patent application, wherein the two stop layers are conformally formed on a surface of an integrated structure under the two stop layers. The semiconductor manufacturing method according to item 1 of the scope of patent application, wherein the second stop layer in the element region includes a recessed region located between two adjacent element structures. The semiconductor manufacturing method described in item 1 of the scope of patent application, further includes a subsequent process, which is based on the flat surface polished by the second-stage polishing process. The semiconductor manufacturing method according to item 1 of the scope of patent application, wherein the step of providing the structural substrate includes: providing a silicon substrate, the silicon substrate is planned with the element region and the isolation region; forming a plurality of semiconductor elements on the silicon substrate Wherein the top portions of the plurality of semiconductor elements are exposed; a polycrystalline silicon layer is formed, covering the plurality of semiconductor elements in the element region and overlying the isolation region; forming the first stop layer on the polycrystalline silicon layer And forming the first oxide layer on the element region and the first stop layer of the isolation region. The semiconductor manufacturing method according to item 8 of the scope of patent application, wherein the plurality of semiconductor elements are metal gates of a memory cell. The semiconductor manufacturing method according to item 8 of the scope of patent application, wherein after the second-stage grinding process, an etch-back process with no selective ratio between the dielectric material and the polycrystalline silicon material is performed to expose the multiple semiconductor elements. Where you want it to be. The method for manufacturing a semiconductor according to item 10 of the patent application scope further includes defining the polycrystalline silicon layer. The semiconductor manufacturing method according to item 1 of the scope of the patent application, wherein the first stop layer and the second stop layer are both silicon nitride layers deposited by atomic layers. The semiconductor manufacturing method according to item 1 of the scope of patent application, wherein the first-stage grinding process is controlled by operating for a fixed period of time. The semiconductor manufacturing method according to item 1 of the scope of the patent application, wherein the second stop layer is nitride, and the second-stage polishing process is stopped at the second stop layer by using a polishing selection ratio of the nitride to the oxide. .