TW201944400A - Input/output multiplexer thereof - Google Patents

Abstract

An input/output multiplexer is provided. The input/output multiplexer includes a bit-line amplifier, a level rising circuit, and a sensing amplifier. The bit-line amplifier is coupled to a first bit line and a second bit line. The bit-line amplifier operates under a high operation voltage and a low operation voltage to amplify voltage difference between the first bit line and the second bit line in a read mode. In a first selection period of the read mode, according to the amplified voltage difference, a voltage level of a first local data terminal of the bit-line amplifier is an initial level, and a voltage level of a second local data terminal thereof is decreased from the initial level. The level rising circuit increases the voltage level of the first local data terminal in the first selection period. The sensing circuit generates first readout data and second readout data according to the increased voltage level of the first local data terminal and the voltage level of the second local data terminal.

Description

   I / O multiplexer   

The invention relates to a memory device, and more particularly to an input-output multiplexer of a memory device.

Recently, due to the increase in the density and capacity of the memory and the high speed and low power consumption requirements for the memory, the input and output of the sensor in the multiplexer The read and write margins are reduced, which causes a bottleneck in the improvement of memory capacity and speed.

Therefore, the present invention provides an input / output multiplexer of a memory device, which can not only increase the sensing margin when reading data from the memory array, but also can write data into the memory array. Speed up writing.

An embodiment of the present invention provides an I / O multiplexer coupled to a memory array through a plurality of bit lines. The memory array includes a plurality of memory cells. The I / O multiplexer includes a bit line amplifier, a level boost circuit, and a sense amplifier. The bit line amplifier is coupled to a first bit line and a second bit line of the plurality of bit lines, and operates at a high supply voltage and a low supply voltage to amplify the first in a read mode. A voltage difference between the voltage level of the bit line and the voltage level of the second bit line. During a first selection period of the read mode, according to the amplified voltage difference, the voltage level of a first local data terminal of the bit line amplifier is initially an initial level, and the voltage of the second local data terminal of the bit line amplifier is initially The level drops from the initial level towards a low supply voltage. The level raising circuit is coupled to the first local data terminal and the second local data terminal, and raises the voltage level of the first local data terminal from the initial level during the first selection period. The sense amplifier is coupled to the first local data terminal and the second local data terminal, and generates a corresponding first bit according to the boosted voltage level of the first local data terminal and the voltage level of the second local data terminal in the read mode. A first readout of the meta line and a second readout of the second bit line.

An embodiment of the present invention provides a memory device including a complex digit line, a complex bit line interlaced with the complex number, a memory array, a decoder, and an input / output multiplexer. The memory array includes a plurality of memory cells. Each memory cell is coupled to one of the complex digital element lines and one of the complex digital element lines. A first memory cell in the plurality of memory cells is coupled to a first word line in the plurality of digit lines and a first bit line in the plurality of bit lines. A second memory cell in the plurality of memory cells is coupled to a second word line in the plurality of digit lines and a second bit line in the plurality of bit lines. The decoder is coupled to the complex digital element lines and enables the complex digital element lines respectively. The I / O multiplexer is coupled to the complex bit line and includes a complex write / read circuit. A first write / read circuit in the complex write / read circuit includes a bit line amplifier, a level boost circuit, and a sense amplifier. The bit line amplifier is coupled to the first bit line and the second bit line, and operates at a high supply voltage and a low supply voltage to amplify when the first word line is enabled in a read mode. A voltage difference between the voltage level of the first bit line and the voltage level of the second bit line. During a first selection period of the read mode, according to the amplified voltage difference, the voltage level of a first local data terminal of the bit line amplifier is initially an initial level, and the voltage level of a second local data terminal of the bit line amplifier is initially The voltage level drops from the initial level toward a low supply voltage. The level raising circuit is coupled to the first local data terminal and the second local data terminal, and raises the voltage level of the first local data terminal from the initial level during the first selection period. The sense amplifier is coupled to the first local data terminal and the second local data terminal, and generates a corresponding first bit according to the boosted voltage level of the first local data terminal and the voltage level of the second local data terminal in the read mode. A first readout of the meta line and a second readout of the second bit line. The first read data and the second read data correspond to the voltage stored in the first memory cell.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows.

1‧‧‧Memory device

10‧‧‧Memory Array

11‧‧‧ decoder

12‧‧‧ Controller

13‧‧‧I / O multiplexer

20‧‧‧bit line amplifier

21‧‧‧level boost circuit

22‧‧‧write amplifier

23‧‧‧Sense Amplifier

24, 25‧‧‧N type transistor

30, 31‧‧‧P type transistor

32 ... 35‧‧‧N type transistor

60 ... 65‧‧‧P type transistor

66 ... 70‧‧‧N-type transistor

71, 72‧‧‧ Inverter

100, 100 (0,1) ‧‧‧Memory cells

130_0 ... 130_n, 130_x‧‧‧‧write / read circuit

210、211‧‧‧P type transistor

ACE‧‧‧Acceleration enable voltage

BL0 ... BLn, BLx, BLB0 ... BLBn, BLBx‧‧‧bit lines

CMA‧‧‧sensing enable signal

CSL0 ... CSLn, CSLx‧‧‧Select signal

GND‧‧‧ ground voltage

IN0 ... INn, INB0 ... INBn, INx‧‧‧

Ldq, LdqB‧‧‧ local data terminal

Mdqs‧‧‧Switch signal

Mdq, MdqB‧‧‧ Main Data Terminal

N20, N21, N30, N31, N60 ... N63‧‧‧nodes

OUT0 ... OUTn, OUTx, OUTB0 ... OUTBn, OUTBx‧‧‧Read data

P_CSL1‧‧‧Selection period

P50, P51‧‧‧ metastable point

T40 ... T42‧‧‧Time

T50 ... T52‧‧‧Time

Voltage level of V_BL1‧‧‧ bit line BL1

V_BLB1‧‧‧ Voltage level of bit line BLB1

V_Ldq‧‧‧Voltage level of local data terminal Ldq

V_LdqB‧‧‧Voltage level of local data terminal LdqB

V_Mdq‧‧‧Voltage level of the main data terminal Mdq

V_MdqB‧‧‧Voltage level of the main data terminal MdqB

V _A ‧‧‧ Preset Level

VDD‧‧‧High supply voltage

Vint‧‧‧ initial level

VSS‧‧‧Low supply voltage

WE‧‧‧ write enable signal

WL0 ... WLm‧‧‧Character line

FIG. 1 illustrates a memory device according to an embodiment of the present invention.

FIG. 2 shows an input-output multiplexer according to an embodiment of the present invention.

The third diagram is a bit line sensor according to an embodiment of the present invention.

The fourth chart is a timing diagram of changes in main signals and main voltage levels of the memory device in the read mode according to an embodiment of the present invention.

The fifth chart is a timing diagram of changes in main signals and main voltage levels of the memory device in the write mode according to an embodiment of the present invention.

The sixth diagram is a sense amplifier according to an embodiment of the present invention.

Hereinafter, examples of several embodiments of the present invention will be explained with reference to related drawings.

FIG. 1 shows a memory device according to an embodiment of the present invention. Referring to FIG. 1, the memory device 1 includes a memory array 10, a decoder 11, a controller 12, an input / output multiplexer 13, word lines WL0 to WLm, and bit lines BL0 to BLn and BLB0 to BLBn. , M is an odd number greater than or equal to 1, and n is an integer greater than or equal to 1. The memory device 1 is operable in a reading mode or a writing mode. The memory array 10 includes a plurality of memory cells 100 arranged in a plurality of columns (horizontal) and a plurality of rows (vertical), and each memory cell is coupled to a word line and a bit line. In the embodiment of FIG. 1, the memory cells arranged in the same column are coupled to the same word line. For example, the memory cells arranged in the first column of FIG. 1 are all coupled to the word line WL0; the memory cells arranged in the second column of FIG. 1 are all coupled to the word line WL1. One part of the memory cells arranged in the same row is coupled to one bit line, and the other part is coupled to another bit line. For example, the memory cells arranged in the first row of FIG. 1 are coupled to the word lines WL0, WL2, and the memory cells coupled to WLm-1 are coupled to the bit line BL0, coupled to the word lines WL1, WL3, Bit line BLB0 is coupled to the memory cell of WLm; the memory cell arranged in the second row of Figure 1 is coupled to word line WL0, WL2, and the memory cell of WLm-1 is coupled to bit line BL1. The word line WL1, WL3, and the memory cell of WLm are coupled to the bit line BLB1. Therefore, it can be known that the memory cells arranged in the same row are alternately coupled to the bit lines BLx and BLBx, and x is an integer from 0 to n. In this embodiment, the bit lines BLx and BLBx coupled to the memory cells in the same row may be referred to as a group of bit lines.

The decoder 11 is coupled to the word lines WL0 ~ WLm. The decoder 11 can enable one word line at a time, thereby selecting memory cells arranged on the same column. The memory device 1 can read or write data to the selected memory cell. The timing of enabling the word lines WL0 to WLm by the decoder 11 is controlled by the controller 12.

The input / output multiplexer 13 includes a plurality of write / read circuits 130_0 to 130_n. Each write / output circuit corresponds to a row of memory cells, that is, each write / output circuit is coupled to a corresponding set of bit lines. For example, the write / read circuit 130_0 is coupled to a group of bit lines BL0 and BLB0; the write / read circuit 130_1 is coupled to a group of bit lines BL1 and BLB1. The input / output multiplexer 13 receives the acceleration enable voltage ACE, the write enable signal WE, the switch signal Mdqs, the sensing enable signal CMA, and the selection signals CSL0 ~ CSLn from the controller 12 to control the write / read Operation of the circuits 130_0 ~ 130_n. The selection signals CSL0 ~ CSLn are provided to the write / read circuits 130_0 ~ 130_n, respectively. Through the operation of the input / output multiplexer 13, the memory device 1 can generate readout data OUT0 ~ OUTn and OUTB0 ~ OUTBn corresponding to the voltage stored in the memory cell 100 in the read mode, and can write according to the write in the write mode. Enter the data IN0 ~ INn and INB1 ~ INBn to change the voltage stored in the memory cell 100.

Figure 2 shows the architecture of the write / output circuit 130_x. Referring to FIG. 2, the write / output circuit 130_x is any one of the write / output circuits 130_0 to 130_n. Hereinafter, the operation of the input / output multiplexer 13 in the read mode and the write mode will be described using the write / output circuit 130_x as the write / output circuit 130_1 (x = 1) as an example. The write / output circuit 130_1 includes a bit line amplifier 20, a level boost circuit 21, a write amplifier 22, a sense amplifier 23, and N-type transistors 24 and 25. The bit line amplifier 20 is coupled to a corresponding set of bit lines BL1 and BLB1, and is controlled by the selection signal CSL1.

FIG. 3 shows a bit line amplifier 20 according to an embodiment of the present invention. Referring to FIG. 3, the bit line amplifier 20 operates at a high supply voltage VDD and a low supply voltage VSS. The bit line amplifier 20 is connected to the bit lines BL1 and BLB1 through the nodes N30 and N31, respectively. The bit line amplifier 20 includes P-type transistors 30 and 31 and N-type transistors 32-35. A first terminal (source) of the P-type transistor 30 receives a high supply voltage VDD, a second terminal (drain) thereof is coupled to the node N30, and a control terminal (gate) thereof is coupled to the node N31. A first terminal of the P-type transistor 31 receives a high supply voltage VDD, a second terminal thereof is coupled to the node N31, and a control terminal thereof is coupled to the node N30. A first terminal (drain) of the N-type transistor 32 is coupled to the node N30, a second terminal (source) thereof receives the low supply voltage VSS, and a control terminal (gate) thereof is coupled to the node N31. A first terminal of the N-type transistor 33 is coupled to the node N31, a second terminal thereof receives the low supply voltage VSS, and a control terminal thereof is coupled to the node N30. A first terminal of the N-type transistor 34 is coupled to the node N30, a second terminal thereof is coupled to the local data terminal Ldq of the bit line amplifier 20, and a control terminal thereof receives a selection signal CSL1. A first terminal of the N-type transistor 35 is coupled to the node N31, a second terminal thereof is coupled to the local data terminal LdqB of the bit line amplifier 20, and a control terminal thereof receives a selection signal CSL1. In this embodiment, the low supply voltage VSS is lower than the high supply voltage VDD, such as the ground voltage GND. Through the operation of the transistors 30 to 33, the bit line amplifier 20 can amplify the voltage difference between the voltage levels of the bit lines BL1 and BLB1 to the voltage difference between the high supply voltage VDD and the low supply voltage VSS. The voltage levels of the local data terminals Ldq and LdqB are initially an initial level Vint, for example, equal to the level of the high supply voltage VDD.

Referring back to FIG. 2, the first terminal (drain) of the N-type transistor 24 is coupled to the local data terminal Ldq, the second terminal (source) is coupled to the node N20, and the control terminal (gate) thereof receives the switching signal. Mdqs. A first terminal of the N-type transistor 25 is coupled to the local data terminal LdqB, a second terminal thereof is coupled to the node N21, and a control terminal thereof receives the switching signal Mdqs. In the read mode and the write mode, the controller 12 enables the switching signal Mdqs to turn on the N-type transistors 24 and 25.

The level raising circuit 21 includes P-type transistors 210 and 211. The P-type transistors 210 and 211 have a threshold voltage Vthp. A first terminal (source) of the P-type transistor 210 is coupled to the node N20, a second terminal (drain) thereof receives the variable voltage ACE, and a control terminal (gate) thereof is coupled to the node N21. A first terminal of the P-type transistor 211 is coupled to the node N21, a second terminal thereof receives the variable voltage ACE, and a control terminal thereof is coupled to the node N20. In the embodiment of the present invention, the level of the variable voltage ACE is not fixed, and can be changed between a preset level (for example, the level V _A shown in FIG. 4) and the level of the low supply voltage VSS . In one embodiment, the preset level is higher than the level of the high supply voltage VDD and does not exceed the level of the sum of the high supply voltage VDD and the threshold voltage Vthp. In other words, the maximum value of the variable voltage is greater than the high supply voltage VDD but does not exceed the sum of the high supply voltage VDD and the threshold voltage Vthp.

The write amplifier 22 is coupled to the nodes N20 and N21, that is, the write amplifier 22 is coupled to the local data terminal Ldq through the node N20 and the N-type transistor 24, and is coupled to the local data terminal LdqB through the node N21 and the N-type transistor 25. . The write amplifier 22 receives the write enable signal WE from the controller 12 and operates under the write enable signal WE in the write mode. The main data terminals Mdq and MdqB of the sense amplifier 23 are coupled to the nodes N20 and N21 respectively, that is, the main data terminal Mdq of the sense amplifier 23 is coupled to the local data terminal Ldq through the node N20 and the N-type transistor 24, and sense The main data terminal MdqB of the amplifier 23 is coupled to the local data terminal LdqB through the node N21 and the N-type transistor 25. The voltage levels of the main data terminals Mdq and MdqB are initially the initial level Vint. The sense amplifier 23 receives the sensing enable signal CMA from the controller 12 and operates under the sensing enabling signal CMA in the read mode.

Hereinafter, the detailed operation of the input / output multiplexer 13 in this case will be described using the write / output circuit 130_1 as an example.

Figure 4 shows the voltage level V_CSL1 of the signal CSL1, the voltage levels V_Ldq and V_LdqB of the local data terminals Ldq and LdqB, the variable voltage ACE, and the voltage levels V_Mdq of the main data terminals Mdq and MdqB in the read mode And V_MdqB, and a timing diagram of changes in the sensing enable signal CMA. It is assumed that the memory device 1 performs a data reading operation on a memory cell (circled by a dotted line and labeled as 100 (0, 1)) coupled to the word line WL1 and the bit line BL1 in the read mode. The operation of the write / output circuit 130_1 in the read mode will be described below through FIGS. 2-4. The N-type transistors 24 and 25 are turned on in the read mode. In the case of performing a data reading operation on the memory cell 100 (0,1), the controller 12 controls the decoder 11 to enable only the word line WL1, thereby selecting the memory cell 100 (0,1). The voltage stored in the memory cell 100 (0,1) indicates that the data stored in the digital field is "1" or "0". For example, when the memory cell 100 (0,1) stores a high voltage, it means that the data stored in the digital field is "1"; when the memory cell 100 (0,1) stores a low voltage, it means the digital field The stored data is "0". When the word line WL1 is enabled, the voltage level of the bit line BL1 coupled to the memory cell 100 (0,1) changes with the voltage stored in the memory cell 100 (0,1). For example, the voltage level of the bit line BL1 starts to rise from a precharge level (for example, 1 / 2VDD) according to the voltage stored in the memory cell 100 (0,1). Since the decoder 11 does not enable other word lines WL0 and WL2 to WLm, the memory cell coupled to the word line BLB1 is not selected, so that the voltage level of the word line BLB1 is maintained at the precharge level. At this time, through the operation of the transistors 30 to 33 of the bit line amplifier 20, the voltage level of the node N30 is clamped at the voltage level of the high supply voltage VDD, and the voltage level of the node N31 is clamped at the low supply voltage VSS In other words, the voltage difference between the voltage levels of the bit lines BL1 and BLB1 is amplified to the voltage difference between the high supply voltage VDD and the low supply voltage VSS.

In the read mode, the selection signal CSL1 is enabled at the time point T40 (that is, the level of the high supply voltage VDD). A period during which the selection signal CSL1 is at a high voltage level is referred to as a selection period P_CSL1. When the selection signal CSL1 is at the level of the high supply voltage VDD, the N-type transistors 34 and 35 are turned on. At this time, the voltage level V_Ldq of the local data terminal Ldq is maintained at its initial level Vint (that is, the level of the high supply voltage VDD) with the voltage level of the node N30, and the voltage level V_LdqB of the local data terminal LdqB follows The voltage level of the node N31 gradually decreases from the initial level Vint toward the level of the low supply voltage VSS. Until the time point T41, the variable voltage ACE has been at the level of the low supply voltage VSS. Therefore, between time points T40 and T41, the P-type transistors 210 and 211 are turned off, and the voltage level V_Ldq continues to be maintained at its initial level Vint, while the voltage level V_LdqB continues to decrease toward the low supply voltage VSS. When the variable voltage ACE is raised to the preset level V _A (that is, the level of the high supply voltage VDD) at time T41, the P-type transistor 210 is turned on, and the P-type transistor 211 is still turned off. At this time, the voltage level V_Ldq is gradually increased from the initial level Vint to the preset level V _A according to the increased variable voltage ACE, and the voltage level V_LdqB continues to decrease toward the low supply voltage VSS. Referring to Figure 4, since the main data terminals Mdq and MdqB are coupled to the local data terminals Ldq and LdqB, respectively, their voltage levels V_Mdq and V_MdqB change with the voltage levels V_Ldq and V_LdqB. Among them, after time point T41, The voltage level V_Mdq gradually increases from the initial level Vint toward the preset level V _A. According to an embodiment of the present invention, the time point T41 at which the level of the variable voltage ACE is raised is delayed from the start time point T40 of the selection period P_CSL1, and the level of the variable voltage ACE is at the end of the selection period P_CSL1 (time point T42) Switch to low supply voltage VSS.

When the controller 12 enables the sensing enable signal CMA during the selection period P_CSL1, the sense amplifier 23 senses the voltage levels V_Mdq and V_MdqB of the main data terminals Mdq and MdqB to generate a corresponding memory cell 100 (0,1). The read-out data OUT1 and OUTB1 of the stored voltage. A back-end device, such as a processor, coupled to the memory device 1 can learn that the data stored in the memory cell 100 (0,1) is a logic "1" or "0" according to the read data OUT1 and OUTB1. Referring to FIG. 4, since the voltage level V_Mdq is not maintained at the initial level Vint after the time point T41, but gradually increases from the initial level Vint toward the preset level V _A , so the voltage level between V_Mdq and V_MdqB The increase in the difference causes the sensing margin of the sense amplifier 23 at the main data terminal Mdq relative to the main data terminal MdqB to increase, which accelerates the reading speed of the memory device 1. As shown in FIG. 4, compared with the case where the voltage level V_Mdq in the conventional technology is still the initial level Vin, the voltage level V_Mdq is increased by the level raising circuit 21 in this case, so that the sensing margin has a ΔV amplitude Increase, where △ V = V _A -Vint.

Figure 5 shows the voltage level V_CSL1 of the signal CSL1, the voltage levels V_Ldq and V_LdqB of the local data terminals Ldq and LdqB, the variable voltage ACE, and the voltage levels V_Mdq and Mdq and MdqB of the main data terminals in the write mode V_MdqB and the timing diagram of changes in the sensing enable signal CMA. Assume that the memory device 1 is in a write-read mode and wants to perform a data write operation on the memory cell 100 (0,1) to write the data “1” to the memory cell 100 (0) that originally stored the data “0”. ,1). The operation of the write / output circuit 130_1 in the write mode will be described below with reference to FIGS. 2, 3, and 5. The N-type transistors 24 and 25 are turned on in the write mode. In the case of performing a data writing operation on the memory cell 100 (0,1), the controller 12 controls the decoder 11 to enable only the word line WL1, thereby selecting the memory cell 100 (0,1). In the write mode, the write amplifier 22 receives the input data IN1. When the controller 12 enables the write enable signal WE, the write amplifier 22 operates according to the write data IN1, so that the voltage level V_Mdq of the main data terminal Mdq is maintained at its initial level Vint (that is, the level of the high supply voltage VDD). Level), and the voltage level V_MdqB of the main data terminal MdqB gradually decreases from the initial level Vint toward the low supply voltage VSS. Since the ground data terminals Ldq and LdqB are respectively coupled to the main data terminals Mdq and MdqB, the changes in the voltage levels V_Ldq and V_LdqB are the same as the changes in the voltage levels V_Mdq and V_MdqB. As shown in FIG. 5, the voltage level V_Ldq is maintained at its initial level Vint, and the voltage level V_LdqB gradually decreases from the initial level Vint toward the low supply voltage VSS.

In the write mode, the selection signal CSL1 is enabled at the time point T50 (that is, the level of the high supply voltage VDD). When the selection signal CSL1 is at the level of the high supply voltage VDD, the N-type transistors 34 and 35 are turned on. At this time, through the operation of the transistors 30 to 33 of the bit line amplifier 20, the voltage level V_BL1 of the bit line BL1 is responded to the voltage level V_Ldq of the local data terminal Ldq and is supplied from the low supply voltage VSS level to the high level. The level of the voltage VDD rises gradually, and the voltage level V_BLB1 of the bit line BLB1 responds to the voltage level V_LdqB of the local data terminal LdqB, and the level of the high supply voltage VDD starts to gradually decrease toward the level of the low supply voltage VSS. Until the time point T51, the variable voltage ACE has been at the level of the low supply voltage VSS. Therefore, between time points T50 and T51, the P-type transistors 210 and 211 are turned off, and the voltage level V_Ldq continues to be maintained at its initial level Vint, while the voltage level V_LdqB continues to decrease toward the low supply voltage VSS. When the variable voltage ACE is raised to the preset level V _A (that is, the level of the high supply voltage VDD) at the time point T51, the P-type transistor 210 is turned on, and the P-type transistor 211 is still turned off. At this time, the voltage level V_Ldq is gradually increased from the initial level Vint to the preset level V _A according to the increased variable voltage ACE, and the voltage level V_LdqB continues to decrease toward the low supply voltage VSS. Referring to FIG. 5, the voltage levels V_Mdq and V_MdqB also have the same change. According to an embodiment of the present invention, the time point T51 at which the level of the variable voltage ACE is raised is delayed from the start time point T50 of the selection period P_CSL1, and the level of the variable voltage ACE is at the end of the selection period P_CSL1 (time point T52) Switch to low supply voltage VSS.

As the difference between the voltage levels V_Ldq and V_LdqB increases, the voltage level V_BL1 of the bit line BL1 can quickly rise to the level of the high supply voltage VDD and the voltage level V_BLB1 of the bit line BLB1 can be quickly reduced to a low level Level of the supply voltage VSS. Referring to FIG. 5, due to the rapid changes in the voltage levels V_BL1 and V_VBLB1 during the selection period P_CSL1, the metastable point P50 of the bit line differential 20 is compared with the metastable point P51 of the conventional technology. It happens earlier in time. This enables the selected memory cell 100 (0,1) to store the voltage representing the corresponding data “1” according to the voltage level V_BL1 of the bit line BL1 earlier.

According to the above, the memory device 1 of the present invention increases the voltage difference between the local data terminals Ldq and LdqB (and between the main data terminals Mdq and MdqB) through the level raising circuit 21, thereby improving the reading of the memory cells And write speed without sacrificing the read / write margin of the input / output multiplexer 13.

The sixth diagram is a sense amplifier 23 according to an embodiment of the present invention. Referring to FIG. 6, the sense amplifier 23 includes P-type transistors 60 to 65, N-type transistors 66 to 70, and inverters 71 and 72. A first terminal (source) of the P-type transistor receives a high supply voltage VDD, a second terminal (drain) thereof is coupled to the node N60, and a control terminal (gate) thereof receives a sensing enable signal CMA. A first terminal of the P-type transistor 60 receives the high supply voltage VDD, a second terminal thereof is coupled to the node N61, and a control terminal thereof receives the sensing enable signal CMA. A first terminal of the P-type transistor 61 receives a high supply voltage VDD, a second terminal thereof is coupled to the node N60, and a control terminal thereof is coupled to the node N61. A first terminal of the P-type transistor 62 receives a high supply voltage VDD, a second terminal thereof is coupled to the node N60, and a control terminal thereof is coupled to the node N61. A first terminal of the P-type transistor 63 receives the high supply voltage VDD, a second terminal thereof is coupled to the node N61, and a control terminal thereof is coupled to the node N60. A first terminal of the P-type transistor 64 is coupled to the node N60, a second terminal thereof is coupled to the node N61, and a control terminal thereof receives the sensing enable signal CMA.

A first terminal (drain) of the N-type transistor 66 is coupled to the node N60, a second terminal (source) thereof is coupled to the node N62, and a control terminal (gate) thereof is coupled to the node N61. A first terminal of the N-type transistor 67 is coupled to the node N61, a second terminal thereof is coupled to the node N63, and a control terminal thereof is coupled to the node N60. A first terminal of the P-type transistor 65 is coupled to the node N62, a second terminal thereof is coupled to the node N63, and a control terminal thereof receives the sensing enable signal CMA. A first terminal of the N-type transistor 68 is coupled to the node N62, a second terminal thereof is coupled to the node N64, and a control terminal thereof is coupled to the main data terminal Mdq. A first terminal of the N-type transistor 69 is coupled to the node N63, a second terminal thereof is coupled to the node N64, and a control terminal thereof is coupled to the main data terminal MdqB. A first terminal of the N-type transistor 70 is coupled to the node N64, a second terminal thereof receives the low supply voltage VSS, and a control terminal thereof receives the sensing enable signal CMA.

The input terminal of the inverter 71 is coupled to the node N60, and the readout data OUTBx (for example, x = 1) is generated at the output terminal of the inverter 71. The input terminal of the inverter 72 is coupled to the node N61, and the read-out data OUTx (for example, x = 1) is generated at the output terminal of the inverter 72. Through the operation of P-type transistors 60 to 65, N-type transistors 66 to 70, and inverters 71 and 72, the sense amplifier 23 can generate readouts according to the voltage levels V_Mdq and V_MdqB of the main data terminals Mdq and MdqB. The data OUT1 and OUTB1 are used to represent a voltage stored in a corresponding memory cell.

The circuit architecture shown in FIG. 6 is only an exemplary example. In other embodiments, different circuit architectures may be used to implement the sense amplifier 23 in this case.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

Claims (10)

    An input-output multiplexer is coupled to a memory array through a plurality of bit lines. The memory array includes a plurality of memory cells. The input-output multiplexer includes: a one-bit line amplifier coupled to the bit lines. A first bit line and a second bit line, and operate at a high supply voltage and a low supply voltage to amplify the voltage level of the first bit line and the second bit line in a read mode. A voltage difference between the voltage levels of the bit lines, wherein during a first selection period of the read mode, the voltage level of a first local data terminal of the bit line amplifier is based on the amplified voltage difference. The initial level is an initial level, and the voltage level of a second local data terminal of the bit line amplifier decreases from the initial level toward the low supply voltage; a quasi-boost circuit is coupled to the first local data terminal and The second local data terminal, and the voltage level of the first local data terminal is raised from the initial level during the first selection period; and a sense amplifier is coupled between the first local data terminal and the first local data terminal Two local data terminals, and should read Formula to generate a first readout data corresponding to the first bit line and a voltage corresponding to the second bit line according to the boosted voltage level of the first local data end and the voltage level of the second local data end. A second readout.         The input / output multiplexer according to item 1 of the scope of patent application, wherein the level boosting circuit includes: a first transistor having a control terminal coupled to the second local data terminal and coupled to the first local data A first terminal of the terminal, and a second terminal output terminal receiving a variable voltage; and a second transistor having a control terminal coupled to the first local data terminal, a first terminal coupled to the second local data terminal, and A second output terminal receiving the variable voltage.         The input / output multiplexer described in item 2 of the scope of patent application, wherein the level of the variable voltage is initially the level of the low supply voltage, and the level of the variable voltage is within the first selection period Raise above this high supply voltage.         The input / output multiplexer according to item 3 of the scope of the patent application, wherein the time point of increasing the level of the variable voltage is delayed from the start time point of the first selection period.         The input / output multiplexer according to item 2 of the scope of patent application, wherein the first transistor and the second transistor have a threshold voltage, and the maximum value of the variable voltage does not exceed the high supply voltage and the The sum of the critical voltages.         The I / O multiplexer according to item 2 of the scope of the patent application, wherein the first transistor and the second transistor are P-type transistors.         The input / output multiplexer according to item 2 of the scope of the patent application, further comprising: a third transistor coupled between the first local data terminal and the level boosting circuit; and a fourth transistor, Coupled between the second local data terminal and the level boosting circuit; wherein the third transistor and the fourth transistor are turned on in the read mode.         The input / output multiplexer according to item 7 of the patent application scope, wherein the third transistor and the fourth transistor are N-type transistors.         According to the input / output multiplexer described in item 1 of the scope of patent application, the method further includes: a write amplifier coupled to the first local data terminal and the second local data terminal, and receiving a write in a write mode Data; wherein, in the write mode, the write amplifier operates according to the write data, so that the voltage level of the first local data terminal is initially the initial level, and the voltage level of the second local data terminal is determined by the The initial level drops towards the low supply voltage; wherein, during a second selection period of the write mode, the level boosting circuit raises the voltage level of the first local data terminal from the initial level; and, During the second selection period, the bit line amplifier changes the voltage level of the first bit line and the second local data line according to the boosted voltage level of the first local data end and the voltage level of the second local data end. The voltage level of the bit line is used to write a voltage corresponding to the written data to one of the memory cells.         The input / output multiplexer described in item 1 of the scope of patent application, wherein the initial level is equal to the level of the high supply voltage.