TWI646549B - Input/output multiplexer thereof - Google Patents

Abstract

An input-input multiplexer includes a bit line amplifier, a level boost circuit, and a sense amplifier. The bit line amplifier is coupled to the first and second bit lines and operates at a high supply voltage and a low supply voltage to amplify a voltage difference between the first and second bit lines in a read mode. During the first selection period of the read mode, according to the amplified voltage difference, the voltage level of the first local data terminal of the bit line amplifier is an initial level, and the voltage level of the second local data terminal is decreased by the initial level. The level boosting circuit boosts the voltage level of the first local data terminal during the first selection period. The sense amplifier generates the first and second read data according to the boosted voltage level of the first local data terminal and the voltage level of the second local data terminal.

Description

Input and output multiplexer

The present invention relates to a memory device, and more particularly to an input-output multiplexer for a memory device.

Recently, due to the increase in the density and capacity of the memory and the requirements for high speed and low power consumption of the memory, the input and output of the sensor are input to the multiplexer. The read and write margins are reduced, which causes the memory to experience bottlenecks in terms of capacity and speed.

Accordingly, the present invention provides an input-output multiplexer for a memory device that not only increases sensing margin when reading data from a memory array, but also can write data to a memory array. Speed up writing.

An embodiment of the present invention provides an input-output multiplexer coupled to a memory array through a plurality of bit lines. This memory array includes a plurality of memory cells. The output multiplexer includes a bit line amplifier, a level boost circuit, and a sense amplifier. The bit line amplifier is coupled to a first bit line and a second bit line of the plurality of bit lines, and operates at a high supply voltage and a low supply voltage to amplify the first in a read mode A voltage difference between the voltage level of the bit line and the voltage level of the second bit line. a first selection in the read mode During the period, according to the amplified voltage difference, the voltage level of a first local data terminal of the bit line amplifier is initially an initial level, and the voltage level of the second local data terminal of the bit line amplifier is supplied from an initial level to a low level. The voltage drops. The level boosting circuit is coupled to the first local data terminal and the second local data terminal, and increases the voltage level of the first local data terminal from the initial level during the first selection period. The sense amplifier is coupled to the first local data end and the second local data end, and in the read mode, generates a corresponding first bit according to the boosted voltage level of the first local data end and the voltage level of the second local data end A first readout data of the meta-line and a second readout data corresponding to the second bitline.

An embodiment of the present invention provides a memory device including a complex digital element line, a complex bit line interleaved with the above complex number, a memory array, a decoder, and an input-input multiplexer. The memory array includes a plurality of memory cells. Each of the memory cells is coupled to one of the complex digital meta-lines and one of the plurality of complex bit lines. A first memory cell of the plurality of memory cells is coupled to a first word line of the complex digital line and a first bit line of the plurality of bit lines. A second memory cell of the plurality of memory cells is coupled to a second word line of the complex digital line and a second bit line of the plurality of bit lines. The decoder is coupled to the complex digital element lines and respectively enables the complex digital element lines. The output multiplexer is coupled to the plurality of bit lines and includes a plurality of write/read circuits. A first write/read circuit in the above plurality of write/read circuits includes a bit line amplifier, a level boost circuit, and a sense amplifier. The bit line amplifier is coupled to the first bit line and the second bit line, and operates at a high supply voltage and a low supply voltage to amplify when the first word line is enabled in a read mode a voltage between the voltage level of the first bit line and the voltage level of the second bit line difference. During a first selection period of the read mode, according to the amplified voltage difference, the voltage level of a first local data terminal of the bit line amplifier is initially an initial level, and a second local data terminal of the bit line amplifier The voltage level drops from the initial level toward the low supply voltage. The level boosting circuit is coupled to the first local data terminal and the second local data terminal, and increases the voltage level of the first local data terminal from the initial level during the first selection period. The sense amplifier is coupled to the first local data end and the second local data end, and in the read mode, generates a corresponding first bit according to the boosted voltage level of the first local data end and the voltage level of the second local data end A first readout data of the meta-line and a second readout data corresponding to the second bitline. The first read data and the second read data correspond to voltages stored by the first memory cell.

The above described objects, features and advantages of the present invention will become more apparent and understood.

1‧‧‧ memory device

10‧‧‧ memory array

11‧‧‧Decoder

12‧‧‧ Controller

13‧‧‧Input and output multiplexer

20‧‧‧ bit line amplifier

21‧‧ ‧ level riser circuit

22‧‧‧Write amplifier

23‧‧‧Sense Amplifier

24, 25‧‧‧N type transistor

30, 31‧‧‧P type transistor

32...35‧‧‧N type transistor

60...65‧‧‧P type transistor

66...70‧‧‧N type transistor

71, 72‧‧‧ reverser

100, 100 (0, 1) ‧ ‧ memory cells

130_0...130_n, 130_x‧‧‧Write/Read Circuit

210, 211‧‧‧P type transistor

ACE‧‧‧Acceleration enable voltage

BL0...BLn, BLx, BLB0...BLBn, BLBx‧‧‧ bit line

CMA‧‧‧Sense enable signal

CSL0...CSLn, CSLx‧‧‧Select signal

GND‧‧‧ Grounding voltage

IN0...INn, INB0...INBn, INx‧‧‧write data

Ldq, LdqB‧‧‧ local data side

Mdqs‧‧‧ switch signal

Mdq, MdqB‧‧‧ main data end

N20, N21, N30, N31, N60...N63‧‧‧ nodes

OUT0...OUTn, OUTx, OUTB0...OUTBn, OUTBx‧‧‧ Read data

P_CSL1‧‧‧Selection period

P50, P51‧‧‧ metastable point

T40...T42‧‧‧ time point

T50...T52‧‧‧ time point

Voltage level of V_BL1‧‧‧ bit line BL1

Voltage level of V_BLB1‧‧‧ bit line BLB1

V_Ldq‧‧‧Local data terminal Ldq voltage level

V_LdqB‧‧‧ Voltage level of local data terminal LdqB

V_Mdq‧‧‧ Main data terminal Mdq voltage level

V_MdqB‧‧‧ The voltage level of the main data terminal MdqB

V _A ‧‧‧Preset level

VDD‧‧‧high supply voltage

Vint‧‧‧ initial level

VSS‧‧‧low supply voltage

WE‧‧‧Write enable signal

WL0...WLm‧‧‧ character line

Fig. 1 shows a memory device in accordance with an embodiment of the present invention.

Figure 2 shows an input-input multiplexer in accordance with an embodiment of the present invention.

The third chart is a bit line sensor according to an embodiment of the present invention.

The fourth graph is a timing chart of changes in the main signal and the main voltage level of the memory device in the read mode according to an embodiment of the present invention.

The fifth graph is a timing chart of changes in the main signal and the main voltage level of the memory device in the write mode according to an embodiment of the present invention.

The sixth chart is a sense amplifier in accordance with an embodiment of the present invention.

Examples of several embodiments of the invention are described below with reference to the drawings.

Figure 1 is a diagram showing a memory device in accordance with an embodiment of the present invention. Referring to FIG. 1, the memory device 1 includes a memory array 10, a decoder 11, a controller 12, an input/output multiplexer 13, word lines WL0 to WLm, and bit lines BL0 to BLn and BLB0 to BLBn, wherein m is an odd number greater than or equal to 1, and n is an integer greater than or equal to 1. The memory device 1 is operable in a read mode or a write mode. The memory array 10 includes a plurality of memory cells 100 configured in a plurality of columns (lateral) and a plurality of rows (vertical), and each memory cell is coupled to a word line and a bit line. In the embodiment of FIG. 1, the memory cells arranged in the same column are coupled to the same word line. For example, the memory cells of the first column disposed in FIG. 1 are all coupled to the word line WL0; the memory cells disposed in the second column of FIG. 1 are all coupled to the word line WL1. A part of the memory cells arranged in the same row is coupled to one bit line, and the other part is coupled to the other bit line. For example, in the memory cell of the first row in FIG. 1, the memory cell coupling bit line BL0 coupled to the word lines WL0, WL2, and WLm-1 is coupled to the word lines WL1, WL3, The memory cell coupled to the WLm is connected to the bit line BLB0; in the memory cell disposed in the second row of FIG. 1, the memory cell coupled to the word line WL0, WL2, and WLm-1 is coupled to the bit line BL1, coupled The memory cells of the word line WL1, WL3, and WLm are coupled to the bit line BLB1. Therefore, it can be seen that the memory cells arranged in the same row are alternately coupled to the bit lines BLx and BLBx, and x is equal to an integer of 0 to n. In this embodiment, the bit lines BLx and BLBx of the memory cells coupled to the same row may be referred to as a group of bit lines.

The decoder 11 is coupled to the word lines WL0 WL WLm. The decoder 11 can enable one word line at a time, thereby selecting memory cells arranged in the same column. The memory device 1 can perform data reading or data writing on the selected memory cell. The timing at which the decoder 11 enables the word lines WL0 WL WLm is controlled by the controller 12.

The output multiplexer 13 includes a plurality of write/read circuits 130_0 to 130_n. Each write/read circuit corresponds to a row of memory cells, that is, each write/read circuit is coupled to a corresponding set of bit lines. For example, the write/read circuit 130_0 is coupled to a set of bit lines BL0 and BLB0; the write/read circuit 130_1 is coupled to a set of bit lines BL1 and BLB1. The input-input multiplexer 13 receives the acceleration enable voltage ACE, the write enable signal WE, the switch signal Mdqs, the sense enable signal CMA, and the selection signals CSL0 to CSLn from the controller 12 to control writing/reading. The operation of circuits 130_0~130_n. The selection signals CSL0 to CSLn are supplied to the write/read circuits 130_0 to 130_n, respectively. Through the operation of the input/output multiplexer 13, the memory device 1 can generate the readout data OUT0~OUTn and OUTB0~OUTBn corresponding to the voltage stored in the memory cell 100 in the read mode, and can be written in the write mode according to the write mode. The data IN0~INn and INB1~INBn are entered to change the voltage stored in the memory cell 100.

Figure 2 shows the write/read circuit 130_x architecture. Referring to Fig. 2, the write/read circuit 130_x is any one of the write/read circuits 130_0 to 130_n. Hereinafter, the operation of the input/output multiplexer 13 in the read mode and the write mode will be described taking the write/read circuit 130_x as the write/read circuit 130_1 (x=1) as an example. The write/read circuit 130_1 includes a bit line amplifier 20, a level boost circuit 21, a write amplifier 22, a sense amplifier 23, and N-type transistors 24 and 25. Bit line amplifier 20 is coupled to a corresponding group The bit lines BL1 and BLB1 are controlled by the selection signal CSL1.

3 is a diagram showing a bit line amplifier 20 according to an embodiment of the present invention. Referring to FIG. 3, the bit line amplifier 20 operates at a high supply voltage VDD and a low supply voltage VSS. The bit line amplifier 20 is connected to the bit lines BL1 and BLB1 through the nodes N30 and N31, respectively. The bit line amplifier 20 includes P-type transistors 30 and 31 and N-type transistors 32 to 35. The first end (source) of the P-type transistor 30 receives the high supply voltage VDD, the second end (drain) is coupled to the node N30, and the control terminal (gate) is coupled to the node N31. The first end of the P-type transistor 31 receives the high supply voltage VDD, the second end of the P-type transistor 31 is coupled to the node N31, and the control end thereof is coupled to the node N30. The first end (drain) of the N-type transistor 32 is coupled to the node N30, the second end (source) receives the low supply voltage VSS, and the control terminal (gate) thereof is coupled to the node N31. The first end of the N-type transistor 33 is coupled to the node N31, the second end of which receives the low supply voltage VSS, and the control end of which is coupled to the node N30. The first end of the N-type transistor 34 is coupled to the node N30, the second end of which is coupled to the local data terminal Ldq of the bit line amplifier 20, and the control terminal thereof receives the selection signal CSL1. The first end of the N-type transistor 35 is coupled to the node N31, the second end of which is coupled to the local data terminal LdqB of the bit line amplifier 20, and the control terminal thereof receives the selection signal CSL1. In this embodiment, the low supply voltage VSS is lower than the high supply voltage VDD, for example, the ground voltage GND. Through the operation of the transistors 30 to 33, the bit line amplifier 20 can amplify the voltage difference between the voltage levels of the bit lines BL1 and BLB1 to a voltage difference between the high supply voltage VDD and the low supply voltage VSS. The voltage levels of the local data terminals Ldq and LdqB are initially an initial level Vint, for example equal to the level of the high supply voltage VDD.

Referring back to Figure 2, the first end of the N-type transistor 24 (dip) The local data terminal Ldq is coupled, the second end (source) is coupled to the node N20, and the control terminal (gate) receives the switch signal Mdqs. The first end of the N-type transistor 25 is coupled to the local data terminal LdqB, the second end of the N-type transistor 25 is coupled to the node N21, and the control terminal thereof receives the switch signal Mdqs. In the read mode and the write mode, the controller 12 enables the switching signal Mdqs to turn on the N-type transistors 24 and 25.

The level boosting circuit 21 includes P-type transistors 210 and 211. The P-type transistors 210 and 211 have a threshold voltage Vthp. The first end (source) of the P-type transistor 210 is coupled to the node N20, the second end (drain) receives the variable voltage ACE, and the control terminal (gate) is coupled to the node N21. The first end of the P-type transistor 211 is coupled to the node N21, the second end of which receives the variable voltage ACE, and the control end of which is coupled to the node N20. In the embodiment of the present invention, the level of the variable voltage ACE is not fixed, and can vary between a preset level (for example, the level V _A shown in FIG. 4 ) and a level of the low supply voltage VSS . . In an embodiment, the preset level is higher than the level of the high supply voltage VDD and does not exceed the level of the sum voltage of the high supply voltage VDD and the threshold voltage Vthp. In other words, the maximum value of the variable voltage is greater than the high supply voltage VDD but does not exceed the sum of the high supply voltage VDD and the threshold voltage Vthp.

The write amplifier 22 is coupled to the nodes N20 and N21, that is, the write amplifier 22 is coupled to the local data terminal Ldq through the node N20 and the N-type transistor 24, and coupled to the local data terminal LdqB through the node N21 and the N-type transistor 25. . The write amplifier 22 receives the write enable signal WE from the controller 12 and operates in response to the write enable signal WE in the write mode. The main data terminals Mdq and MdqB of the sense amplifier 23 are respectively coupled to the nodes N20 and N21, that is, the main data terminal Mdq of the sense amplifier 23 passes through the node N20 and the N-type battery. The crystal 24 is coupled to the local data terminal Ldq, and the main data terminal MdqB of the sense amplifier 23 is coupled to the local data terminal LdqB through the node N21 and the N-type transistor 25. The voltage levels of the main data ends Mdq and MdqB are initially the initial level Vint. The sense amplifier 23 receives the sense enable signal CMA from the controller 12 and operates in accordance with the sense enable signal CMA in the read mode.

Hereinafter, the detailed operation of the input/output multiplexer 13 in the present case will be described by taking the write/read circuit 130_1 as an example.

Figure 4 shows the voltage level V_CSL1 of the signal CSL1, the voltage levels V_Ldq and V_LdqB of the local data terminals Ldq and LdqB, the variable voltage ACE, and the voltage level V_Mdq of the main data terminals Mdq and MdqB in the read mode. And V_MdqB, and the timing diagram of the change of the sensing enable signal CMA. It is assumed that the memory device 1 is to perform a data reading operation on the memory cells coupled to the word line WL1 and the bit line BL1 (circled by a broken line and labeled as 100 (0, 1)) in the read mode. The operation of the write/read circuit 130_1 in the read mode will be described below with reference to Figs. 2-4. The N-type transistors 24 and 25 are turned on in the read mode. In the case where a data reading operation is to be performed on the memory cell 100 (0, 1), the controller 12 controls the decoder 11 to enable only the word line WL1, thereby selecting the memory cell 100 (0, 1). The voltage stored in the memory cell 100 (0, 1) indicates that the data stored in the digital domain is "1" or "0". For example, when the memory cell 100 (0, 1) stores a high voltage, it indicates that the stored data is "1" in the digit field; when the memory cell 100 (0, 1) stores a low voltage, it indicates in the digital domain The stored data is "0". When the word line WL1 is enabled, the voltage level of the bit line BL1 coupled to the memory cell 100 (0, 1) changes with the voltage stored by the memory cell 100 (0, 1). For example, the voltage level of the bit line BL1 is from a precharge bit according to the voltage stored by the memory cell 100 (0, 1). Quasi (for example, 1/2VDD) starts to rise. Since the decoder 11 does not enable the other word lines WL0 and WL2 WL WLm, the memory cells coupled to the word line BLB1 are not selected, so that the voltage level of the word line BLB1 is maintained at the pre-charge level. At this time, through the operation of the transistors 30 to 33 of the bit line amplifier 20, the voltage level of the node N30 is clamped at the voltage level of the high supply voltage VDD, and the voltage level of the node N31 is clamped at the low supply voltage VSS. The voltage level, in other words, the voltage difference between the voltage levels of the bit lines BL1 and BLB1 is amplified to a voltage difference between the high supply voltage VDD and the low supply voltage VSS.

In the read mode, the selection signal CSL1 is enabled at time T40 (ie, becomes the level of the high supply voltage VDD). The period during which the selection signal CSL1 is at the high voltage level is referred to as the selection period P_CSL1. When the selection signal CSL1 is at the level of the high supply voltage VDD, the N-type transistors 34 and 35 are turned on. At this time, the voltage level V_Ldq of the local data terminal Ldq is maintained at its initial level Vint (ie, the level of the high supply voltage VDD) with the voltage level of the node N30, and the voltage level V_LdqB of the local data terminal LdqB follows. The voltage level of the node N31 is gradually decreased from the initial level Vint to the level of the low supply voltage VSS. Until time point T41, the variable voltage ACE is always at the level of the low supply voltage VSS. Therefore, between time points T40 and T41, the P-type transistors 210 and 211 are turned off, and the voltage level V_Ldq is continuously maintained at its initial level Vint, while the voltage level V_LdqB continues to fall toward the low supply voltage VSS. When the variable voltage ACE is raised to the preset level V _A (ie, the level of the high supply voltage VDD) at the time point T41, the P-type transistor 210 is turned on, and the P-type transistor 211 is still turned off. At this time, the voltage level V_Ldq is gradually increased from the initial level Vint to the preset level V _A according to the boosted variable voltage ACE, and the voltage level V_LdqB continues to decrease toward the low supply voltage VSS. Referring to FIG. 4, since the main data ends Mdq and MdqB are respectively coupled to the local data terminals Ldq and LdqB, the voltage levels V_Mdq and V_MdqB are changed with the voltage levels V_Ldq and V_LdqB, wherein after the time point T41, The voltage level V_Mdq is gradually increased from the initial level Vint toward the preset level V _A . According to an embodiment of the invention, the time point T41 of the level rise of the variable voltage ACE is delayed by the start time point T40 of the selection period P_CSL1, and the level of the variable voltage ACE is at the end of the selection period P_CSL1 (time point T42) Switch to the level of the low supply voltage VSS.

When the controller 12 enables the sensing enable signal CMA during the selection period P_CSL1, the sense amplifier 23 senses the voltage levels V_Mdq and V_MdqB of the main data terminals Mdq and MdqB to generate corresponding memory cells 100(0, 1). Read data OUT1 and OUTB1 of the stored voltage. The back end device coupled to the memory device 1, such as a processor, can know that the data stored in the memory cell 100 (0, 1) is a logical "1" or "0" based on the read data OUT1 and OUTB1. Referring to FIG. 4, since the voltage level V_Mdq is not always maintained at the initial level Vint after the time point T41, but is gradually increased from the initial level Vint toward the preset level V _A , the voltage levels V_Mdq and V_MdqB are The difference is increased such that the sensing margin of the sense amplifier 23 at the main data terminal Mdq relative to the main data terminal MdqB is increased, which speeds up the reading speed of the memory device 1. As shown in FIG. 4, compared with the case where the voltage level V_Mdq is still the initial level Vin in the prior art, since the level raising circuit 21 raises the voltage level V_Mdq, the sensing margin has a ΔV amplitude. The increase, where ΔV = V _A -Vint.

Figure 5 shows the voltage level V_CSL1 of the signal CSL1, the voltage levels V_Ldq and V_LdqB of the local data terminals Ldq and LdqB, the variable voltage ACE, the voltage levels V_Mdq of the main data terminals Mdq and MdqB in the write mode. V_MdqB, and a timing diagram of the change of the sensing enable signal CMA. It is assumed that the memory device 1 is in the write mode, and a data write operation is to be performed on the memory cell 100 (0, 1) to write the data "1" to the memory cell 100 of the original stored data "0" (0, 1). ). The operation of the write/read circuit 130_1 in the write mode will be described below through the second, third, and fifth figures. N-type transistors 24 and 25 are turned on in the write mode. In the case where a data write operation is to be performed on the memory cell 100 (0, 1), the controller 12 controls the decoder 11 to enable only the word line WL1, thereby selecting the memory cell 100 (0, 1). In the write mode, write amplifier 22 receives input data IN1. When the controller 12 enables the write enable signal WE, the write amplifier 22 operates according to the write data IN1, so that the voltage level V_Mdq of the main data terminal Mdq is maintained at its initial level Vint (ie, the bit of the high supply voltage VDD). The voltage level V_MdqB of the main data terminal MdqB gradually decreases from the initial level Vint toward the low supply voltage VSS. Since the ground data terminals Ldq and LdqB are respectively coupled to the main data terminals Mdq and MdqB, the changes of the voltage levels V_Ldq and V_LdqB are the same as the changes of the voltage levels V_Mdq and V_MdqB. As shown in FIG. 5, the voltage level V_Ldq is maintained at its initial level Vint, and the voltage level V_LdqB is gradually decreased from the initial level Vint toward the low supply voltage VSS.

In the write mode, the selection signal CSL1 is enabled at time T50 (ie, becomes the level of the high supply voltage VDD). When the selection signal CSL1 is at the level of the high supply voltage VDD, the N-type transistors 34 and 35 are turned on. At this time, through the operation of the transistors 30 to 33 of the bit line amplifier 20, the voltage level V_BL1 of the bit line BL1 is reflected by the voltage level V_Ldq of the local data terminal Ldq and is supplied from the level of the low supply voltage VSS. The level of the voltage VDD gradually rises, and the voltage level V_BLB1 of the bit line BLB1 is reflected by the voltage level V_LdqB of the local data terminal LdqB and gradually decreases from the level of the high supply voltage VDD toward the level of the low supply voltage VSS. Until time point T51, the variable voltage ACE is always at the level of the low supply voltage VSS. Therefore, between time points T50 and T51, the P-type transistors 210 and 211 are turned off, and the voltage level V_Ldq is continuously maintained at its initial level Vint, while the voltage level V_LdqB continues to fall toward the low supply voltage VSS. When the variable voltage ACE is raised to the preset level V _A (i.e., the level of the high supply voltage VDD) at the time point T51, the P-type transistor 210 is turned on, and the P-type transistor 211 is continuously turned off. At this time, the voltage level V_Ldq is gradually increased from the initial level Vint to the preset level V _A according to the boosted variable voltage ACE, and the voltage level V_LdqB continues to decrease toward the low supply voltage VSS. Referring to Figure 5, the voltage levels V_Mdq and V_MdqB also have the same change. According to an embodiment of the invention, the time point T51 of the level rise of the variable voltage ACE is delayed by the start time point T50 of the selection period P_CSL1, and the level of the variable voltage ACE is at the end of the selection period P_CSL1 (time point T52) Switch to the level of the low supply voltage VSS.

Since the difference between the voltage levels V_Ldq and V_LdqB is increased, the voltage level V_BL1 of the bit line BL1 can rise rapidly to the level of the high supply voltage VDD and the voltage level V_BLB1 of the bit line BLB1 can be quickly lowered to the low level. The level of the supply voltage VSS. Referring to FIG. 5, due to the rapid change of the voltage levels V_BL1 and V_VBLB1 in the P_CSL1 during the selection period, the metastable point P50 of the bit line amplifier 20 is compared with the metastable point P51 of the prior art. Time is relatively early. This allows the selected memory cell 100 (0, 1) to store the voltage of the corresponding data "1" earlier based on the voltage level V_BL1 of the bit line BL1.

According to the above, the memory device 1 of the present invention increases the voltage difference between the local data terminals Ldq and LdqB (and between the main data terminals Mdq and MdqB) through the level boosting circuit 21, thereby improving the reading of the memory cells. The write speed is not sacrificed, and the read/write margin of the input/output multiplexer 13 is not sacrificed.

The sixth graph is a sense amplifier 23 in accordance with an embodiment of the present invention. Referring to FIG. 6, the sense amplifier 23 includes P-type transistors 60-65, N-type transistors 66-70, and inverters 71 and 72. The first end (source) of the P-type transistor 60 receives the high supply voltage VDD, the second end (drain) is coupled to the node N60, and its control terminal (gate) receives the sensing enable signal CMA. The first end of the P-type transistor 61 receives the high supply voltage VDD, the second end of the P-type transistor 61 is coupled to the node N61, and the control terminal thereof receives the sensing enable signal CMA. The first end of the P-type transistor 62 receives the high supply voltage VDD, the second end of the P-type transistor 62 is coupled to the node N60, and the control end thereof is coupled to the node N61. The first end of the P-type transistor 63 receives the high supply voltage VDD, the second end of the P-type transistor 63 is coupled to the node N61, and the control end thereof is coupled to the node N60. The first end of the P-type transistor 64 is coupled to the node N60, the second end of the P-type transistor 64 is coupled to the node N61, and the control end thereof receives the sensing enable signal CMA.

The first end (drain) of the N-type transistor 66 is coupled to the node N60, the second end (source) of the N-type transistor 66 is coupled to the node N62, and the control terminal (gate) thereof is coupled to the node N61. The first end of the N-type transistor 67 is coupled to the node N61, the second end of the N-type transistor 67 is coupled to the node N63, and the control end thereof is coupled to the node N60. First end of P-type transistor 65 The node N62 is coupled to the node N63, and the control end thereof receives the sensing enable signal CMA. The first end of the N-type transistor 68 is coupled to the node N62, the second end of the N-type transistor 68 is coupled to the node N64, and the control end is coupled to the main data terminal Mdq. The first end of the N-type transistor 69 is coupled to the node N63, the second end of the N-type transistor 69 is coupled to the node N64, and the control end is coupled to the main data terminal MdqB. The first end of the N-type transistor 70 is coupled to the node N64, the second end thereof receives the low supply voltage VSS, and the control terminal thereof receives the sensing enable signal CMA.

The input of the inverter 71 is coupled to the node N60, and the readout data OUTBx (e.g., x = 1) is generated at the output of the inverter 71. The input of the inverter 72 is coupled to the node N61, and the read data OUTx (e.g., x = 1) is generated at the output of the inverter 72. Through the operation of the P-type transistors 60-65, the N-type transistors 66-70, and the inverters 71 and 72, the sense amplifier 23 can generate readouts according to the voltage levels V_Mdq and V_MdqB of the main data terminals Mdq and MdqB. The data OUT1 and OUTB1 are used to indicate the voltage stored in a corresponding memory cell.

The circuit architecture shown in FIG. 6 is only an example. In other embodiments, the sense amplifier 23 of the present invention can be implemented with different circuit architectures.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

Claims (10)

An input-output multiplexer coupled to a memory array through a plurality of bit lines, the memory array including a plurality of memory cells, the output-input multiplexer comprising: a one-bit line amplifier coupled to the bit line a first bit line and a second bit line, and operating at a high supply voltage and a low supply voltage to amplify the voltage level of the first bit line and the second in a read mode a voltage difference between the voltage levels of the bit lines, wherein during a first selection period of the read mode, the voltage level of a first local data terminal of the bit line amplifier is based on the amplified voltage difference Initially being an initial level, and a voltage level of a second local data terminal of the bit line amplifier is decreased from the initial level toward the low supply voltage; a quasi-rising circuit coupled to the first local data terminal and The second local data end, and the voltage level of the first local data end is raised by the initial level during the first selection period; and a sense amplifier coupled to the first local data end and the first Two local data ends, and the reading a first read data corresponding to the first bit line and corresponding to the second bit line according to the boosted voltage level of the first local data end and the voltage level of the second local data end A second read data. The input-output multiplexer according to claim 1, wherein the level-up circuit comprises: a first transistor having a control end coupled to the second local data terminal, a first end coupled to the first local data terminal, and a second end receiving a variable voltage; and a second transistor having a coupling The control end of the first local data end, the first end coupled to the second local data end, and the second end receiving the variable voltage. The input-output multiplexer of claim 2, wherein the level of the variable voltage is initially a level of the low supply voltage, and the level of the variable voltage is within the first selection period. Raise above this high supply voltage. The input-output multiplexer of claim 3, wherein a time point at which the level of the variable voltage rises is delayed by a start time point of the first selection period. The input/output multiplexer of claim 2, wherein the first transistor and the second transistor have a threshold voltage, and the maximum value of the variable voltage does not exceed the high supply voltage and The sum of the threshold voltages. The input-output multiplexer of claim 2, wherein the first transistor and the second transistor are P-type transistors. The input/output multiplexer of claim 2, further comprising: a third transistor coupled between the first local data terminal and the level rising circuit; and a fourth transistor, The second local data end is coupled between the second local data terminal and the level rising circuit; The third transistor and the fourth transistor are turned on in the read mode. The input-output multiplexer of claim 7, wherein the third transistor and the fourth transistor are N-type transistors. The input/output multiplexer of claim 1, further comprising: a write amplifier coupled to the first local data terminal and the second local data terminal, and receiving a write in a write mode Data; wherein, in the write mode, the write amplifier operates according to the write data, such that the voltage level of the first local data terminal is initially the initial level, and the voltage level of the second local data terminal is The initial level decreases toward the low supply voltage; wherein, during a second selection period of the write mode, the level boosting circuit boosts the voltage level of the first local data terminal from the initial level; and wherein During the second selection period, the bit line amplifier changes the voltage level of the first bit line and the second according to the boosted voltage level of the first local data end and the voltage level of the second local data end. The voltage level of the bit line is used to write a voltage corresponding to the data to one of the memory cells. The input-output multiplexer of claim 1, wherein the initial level is equal to the level of the high supply voltage.