TWI739494B - Sense amplification device - Google Patents

Abstract

A sense amplification device is provided. The sense amplification device includes a first sense amplifier, a second sense amplifier, and a third sense amplifier. An input terminal of the first sense amplifier is coupled to a first bit line. An input terminal of the second sense amplifier is coupled to a second bit line. The third sense amplifier has a differential input pair and a differential output pair, wherein a first input terminal of the differential input pair is coupled to an output terminal of the first sense amplifier, a second input terminal of the differential input pair is coupled to an output terminal of the second sense amplifier, a first output terminal of the differential output pair is coupled to the input terminal of the first sense amplifier, and a second output terminal of the differential output pair is coupled to the input terminal of the second sense amplifier.

Description

Sensing amplification device

The present invention relates to a signal amplifying circuit, and more particularly to a sensing amplifying device.

FIG. 1 shows a circuit block diagram of a memory cell array in a dynamic random access memory (DRAM) 100. The memory cell array of the DRAM 100 includes a plurality of sub-arrays 110-140. Each of the sub-arrays 110 to 140 has multiple bit lines BL0 and BL1, multiple character lines (not shown), and multiple memory cells (not shown). According to design requirements, these sub-arrays 110-140 can be conventional memory cell arrays or other memory cell arrays, so they will not be described in detail.

The DRAM 100 shown in FIG. 1 also includes a plurality of sense amplifiers. The bit lines of the two sub-arrays share a sense amplifier. Each of these sense amplifiers is a differential signal amplifier. That is, each of these sense amplifiers has a differential pair. The first end and the second end of the differential pair are respectively coupled to a bit line of different sub-arrays. For example, the first end of the differential pair of the sense amplifier 150 is coupled to the bit line BL0 of the sub-array 110, and the second end of the differential pair of the sense amplifier 150 is coupled to the bit line BL1 of the sub-array 120 .

The first terminal and the second terminal of the differential pair of the sense amplifier 150 shown in FIG. 1 have the same bit line capacitance. Load capacitance matching can be used for accurate differential sensing. As shown in FIG. 1, because there is no sense amplifier on one side of the edge sub-array (for example, the sub-array 110 or 140), the bit line capacitance matching is impossible. The edge sub-arrays 110 and 140 include dummy bit-lines (represented by dashed lines) and a plurality of dummy memory cells (not shown) connected to the dummy bit-lines. Generally speaking, pseudo memory cells are memory cells that are left unused. Therefore, half of the memory cells in the edge sub-array are unavailable.

。 FIG. 2 illustrates the sense amplifier 150, the bit line BL0 and the bit line BL1 shown in FIG. 1. FIG. 3 is a schematic diagram showing the waveforms of the word line WL, the control signal CSP, the control signal CSN, the data SN, the bit line BL0 and the bit line BL1 shown in FIG. 2. The horizontal axis shown in FIG. 3 represents time, and the vertical axis represents the signal level. Please refer to Figure 2 and Figure 3. The first power terminal of the sense amplifier 150 shown in FIG. 2 receives the control signal CSP, and the second power terminal of the sense amplifier 150 receives the control signal CSN. _{The capacitor C BL} shown in FIG. 2 represents the parasitic capacitance of the bit line BL0 and the bit line BL1. The memory cell MC shown in FIG. 2 represents one of a plurality of memory cells coupled to the bit line BL1 in the sub-array 120. The memory cell MC shows an equivalent circuit, including a switch SW and a memory element C _SN . The first end of the switch SW is coupled to the bit line BL1. The second end of the switch SW is coupled to the memory element C _SN . The control terminal of the switch SW is coupled to one word line WL among the plurality of word lines in the sub-array 120. When the word line WL turns on the switch SW, the sense amplifier 150 can sense (read) the data SN of the memory cell MC through the bit line BL1, thereby amplifying the level of the data SN. The sensing signal (the level difference between the bit line BL0 and the bit line BL1) can be expressed as

.

The sense amplifier 150 includes an NMOS pair and a PMOS pair. Due to the process variation, the Vth mismatch between the paired transistors in the sense amplifier 150 may be caused. Therefore, the sensing signal dV _SIG must be greater than the Vth mismatch so that the sensing amplifier 150 can correctly detect the sensing signal dV _SIG . However, as the process shrinks, the capacitance of the cell storage node (CSN) decreases and the sensing signal dV _SIG decreases. In addition, as the number of sense amplifiers on the chip increases, the Vth mismatch will increase statistically. Therefore, the sensing signal margin is reduced as the process shrinks.

It should be noted that the content of the "prior art" paragraph is used to help understand the present invention. Part of the content (or all of the content) disclosed in the "Prior Art" paragraph may not be the conventional technology known to those with ordinary knowledge in the technical field. The content disclosed in the "prior art" paragraph does not mean that the content has been known to those with ordinary knowledge in the technical field before the application of the present invention.

The invention provides a sensing amplification device for sensing (reading) bit line data.

In an embodiment of the present invention, the aforementioned sensing amplifier device includes a first sensing amplifier, a second sensing amplifier, and a third sensing amplifier. The input terminal of the first sense amplifier is coupled to the first bit line. The input terminal of the second sense amplifier is coupled to the second bit line. The third sense amplifier has a differential input pair and a differential output pair, wherein the first input terminal of the differential input pair is coupled to the output terminal of the first sense amplifier, and the second input terminal of the differential input pair is coupled to The output end of the second sense amplifier, the first output end of the differential output pair is coupled to the input end of the first sense amplifier, and the second output end of the differential output pair is coupled to the input of the second sense amplifier end.

Based on the above, the first sense amplifier and/or the second sense amplifier described in the embodiments of the present invention can amplify small signals on the bit line. The third sense amplifier may receive the amplified differential signal. Therefore, the sensing amplifying device can sense (read) the data of the bit line.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The term "coupling (or connection)" used in the full text of the description of this case (including the scope of the patent application) can refer to any direct or indirect connection means. For example, if it is described in the text that the first device is coupled (or connected) to the second device, it should be interpreted as that the first device can be directly connected to the second device, or the first device can be connected through other devices or some This kind of connection means is indirectly connected to the second device. In addition, wherever possible, elements/components/steps with the same reference numbers in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numerals or use the same terms in different embodiments may refer to related descriptions.

FIG. 4 is a circuit block diagram of a sensing amplification device 400 according to an embodiment of the present invention. The sense amplifier 400 may be a two-stage (2-stage) sense amplifier. In this embodiment, the sensing amplifying device 400 includes sensing amplifiers 410-430. The input terminal of the sense amplifier 410 is coupled to the bit line BLa. The input terminal of the sense amplifier 420 is coupled to the bit line BLb. The bit line BLa and the bit line BLb can be analogized with reference to the related description of the bit lines BL0 and BL1 shown in FIG. 1 and FIG. 2.

The bit line BLa is coupled to a plurality of memory cells in a sub-array of the memory cell array in the DRAM (for example, the memory cell MC1), and the bit line BLb is coupled to another sub-array in the memory cell array Multiple memory cells in (for example, memory cell MC2). The sub-array can be analogized with reference to the related description of the sub-arrays 110-140 shown in FIG. 1, and the memory cell MC1 and the memory cell MC2 can be analogized with reference to the related description of the memory cell MC shown in FIG.

The sense amplifiers 410 and 420 may be non-differential signal amplifiers (single-ended signal amplifiers) or any suitable type of amplifiers. The sense amplifier 410 can sense and amplify the signal on the bit line BLa, and output the amplified signal to the node SEN0, and the sense amplifier 420 can also sense and amplify the signal on the bit line BLb, and The amplified signal is output to node SEN1. When the sense amplifier 410 outputs the amplified signal corresponding to the signal on the bit line BLa to the node SEN0, the sense amplifier 420 may set the node SEN1 to the level of the reference voltage VSEN1 (for example, 1.2V). When the sense amplifier 420 outputs the amplified signal corresponding to the signal on the bit line BLb to the node SEN1, the sense amplifier 410 may set the node SEN0 to the level of the reference voltage VSEN0 (for example, 1.2V).

The sense amplifier 430 may be a differential signal amplifier. The sense amplifier 430 has a differential input pair and a differential output pair. The first input terminal of the differential input pair is coupled to the output terminal of the sense amplifier 410 through the node SEN0, and the second input terminal of the differential input pair is coupled to the output terminal of the sense amplifier 420 through the node SEN1 . The differential output pair of the sense amplifier 430 can provide the sensing result of the bit line BLa and the bit line BLb to the next-stage circuit (for example, an analog-to-digital converter). In addition, the first output terminal of the differential output pair is coupled to the input terminal of the sense amplifier 410, and the second output terminal of the differential output pair is coupled to the input terminal of the sense amplifier 420. Therefore, the sense amplifier 430 can sense and amplify the differential voltage between the nodes SEN0 and SEN1, and output the amplified signal to the bit lines BLa and BLb.

In the sense amplifier device 400, the small signals on the bit lines BLa and BLb are respectively amplified by the sense amplifiers 410 and 420 of the first stage, and then the amplified signals are output to the sense amplifier 430 of the second stage. Therefore, the strength of the differential signal received by the sense amplifier 430 is greater than the strength of the differential signal received by the sense amplifier 150 shown in FIG. 1. Therefore, even though the manufacturing process is scaled down, the embodiment shown in FIG. 4 can still achieve sufficient sensing signal tolerance. Therefore, the sense amplification device 400 has immunity to mismatch. In addition, it does not require precise bit line capacitance matching. Therefore, the edge sub-array can be equipped with sensing and amplifying devices 400 on both sides, and all memory cells of the edge sub-array can be used.

FIG. 5 is a schematic circuit diagram of a sense amplifier 500 according to an embodiment of the invention. The sense amplifier 500 is suitable for the sense amplifiers 410 and 420 of FIG. 4. In FIG. 5, the reference voltage VSEN can be analogized to the reference voltage VSEN0 or VSEN1 of FIG. 4, the bit line BL can be analogous to the bit line BLa or BLb of FIG. 4, and the node SEN can be analogous to the node SEN0 of FIG. 4. Or SEN1. The reference voltage VSEN, the control signal SENC, and the control signal BLC in FIG. 5 may be provided by other devices (not shown, such as a controller, a reference voltage generating circuit, etc.).

Please refer to FIG. 5, the sense amplifier 500 includes transistors 510 and 520. The transistor 510 includes a PMOS transistor or other transistors. The transistor 520 includes an NMOS transistor or other transistors. The first terminal (for example, the source) of the transistor 510 is coupled to the reference voltage VSEN. The second terminal (for example, the drain) of the transistor 510 is coupled to the output terminal of the sense amplifier 500 to output the amplified signal (or the reference voltage VSEN) to the node SEN. The control terminal (such as the gate) of the transistor 510 is controlled by the control signal SENC. The first terminal (for example, the source) of the transistor 520 is coupled to the input terminal of the sense amplifier 500 to receive the data signal of the bit line BL. The second end (for example, the drain) of the transistor 520 is coupled to the second end of the transistor 510. The control terminal (such as the gate) of the transistor 520 is controlled by the control signal BLC.

FIG. 6 is a schematic diagram illustrating the timing of the signal shown in FIG. 5 according to an embodiment of the present invention. The horizontal axis shown in FIG. 6 represents time, and the vertical axis represents the signal level. FIG. 6 shows the control signal on the word line WL. The period during which the control signal on the word line WL is at a high logic level is called the word line enable period WLE. When the control signal on the word line WL is at a high logic level, one of the multiple memory cells coupled to the bit line BL will be selected, and the selected corresponding memory cell will have data Output to bit line BL.

Please refer to Figure 5 and Figure 6. During the bit line precharging period PC, the control signal SENC turns on the transistor 510, and the control signal BLC drives the transistor 520 to precharge the bit line BL. The control signal BLC can drive the transistor 520 to set the level of the bit line BL to an appropriate precharge level (for example, 0.5V).

Then, before the initialization period 601 of the word line enable period WLE, the control signal SENC turns on the transistor 510 and the control signal BLC turns off the transistor 520. The transistor 510 can set the level of the node SEN to the precharge level (reference voltage VSEN) during the initialization period 601. After the transistor 520 is turned off, during the initialization period 601 of the word line enable period WLE, the word line WL turns on the memory cell to be read, causing the memory cell to be read to output data to the precharged bit On the element line BL. When the data is "1", the level of the bit line BL becomes higher than the precharge level. When the data is "0", the level of the bit line BL becomes lower than the precharge level.

After the initialization period 601 ends, the control signal SENC turns off the transistor 510. Then, in the sensing period 602 of the word line enable period WLE, the control signal SENC turns off the transistor 510, and the control signal BLC drives the transistor 520 to sense the bit line BL. During the sensing period 602 and the data on the bit line BL is in the first logic state (for example, “1”), the transistor 520 is turned off, so that the node SEN is maintained at the precharge level (for example, 1.2V). In the sensing period 602 and when the data of the bit line BL is in the second logic state (for example, “0”), the transistor 520 is turned on. Since the capacitance of the node SEN is much smaller than the capacitance of the bit line BL, the node SEN is discharged to a level close to the bit line BL.

FIG. 7 is a schematic circuit diagram of a sense amplifier 700 according to another embodiment of the present invention. The sense amplifier 700 is suitable for the sense amplifiers 410 and 420 of FIG. 4. In FIG. 7, the reference voltage VSEN can be analogous to the reference voltage VSEN0 or VSEN1 of FIG. 4, the bit line BL can be analogous to the bit line BLa or BLb of FIG. 4, and the node SEN can be analogous to the node SEN0 or SEN1. The reference voltage VSEN, the control signal SENC, the control signal PBLCS, the reference voltage VREF_BLC, and the control signal NBLCS in FIG. 7 may be provided by other devices (not shown, such as a controller, a reference voltage generating circuit, etc.). According to design requirements, the reference voltage VREF_BLC can be a fixed voltage.

Please refer to FIG. 7, the sense amplifier 700 includes a control circuit 710, a transistor 720 and a transistor 730. Transistors 720 and 730 can be deduced by analogy with reference to related descriptions of transistors 510 and 520 in FIG. The first terminal (for example, the source) of the transistor 720 is coupled to the reference voltage VSEN. The second terminal (for example, the drain) of the transistor 720 is coupled to the output terminal of the sense amplifier 700 to output the amplified signal (or the reference voltage VSEN) to the node SEN. The control terminal (such as the gate) of the transistor 720 is controlled by the control signal SENC. The first terminal (for example, the source) of the transistor 730 is coupled to the input terminal of the sense amplifier 700 to receive the data signal of the bit line BL. The second end (for example, the drain) of the transistor 730 is coupled to the second end of the transistor 720. The control terminal (such as the gate) of the transistor 730 is controlled by the control signal BLC.

The input terminal of the control circuit 710 is coupled to the input terminal of the sense amplifier 700 to receive the data signal of the bit line BL. The control circuit 710 can generate a control signal BLC to the control terminal of the transistor 730. The control circuit 710 can dynamically adjust the control signal BLC according to the level of the input terminal of the sense amplifier 700 (the level of the data signal of the bit line BL).

In the embodiment shown in FIG. 7, the control circuit 710 includes a transistor 711 and a transistor 712. The transistor 711 includes a PMOS transistor or other transistors. The transistor 712 includes an NMOS transistor or other transistors. The first end (for example, the source) of the transistor 711 receives the control signal PLBCS. The second terminal (for example, the drain) of the transistor 711 is coupled to the output terminal of the control circuit 710 to generate a control signal BLC to the control terminal of the transistor 730. The control terminal (such as the gate) of the transistor 711 is controlled by the reference voltage VREF_BLC. The first terminal (for example, the source) of the transistor 712 receives the control signal NBLCS. The second end (for example, the drain) of the transistor 712 is coupled to the second end of the transistor 711. The control terminal (eg, gate) of the transistor 712 is coupled to the input terminal of the control circuit 710 to receive the data signal of the bit line BL.

FIG. 8 is a schematic diagram illustrating the timing of the signal shown in FIG. 7 according to an embodiment of the present invention. Referring to FIGS. 7 and 8, during the bit line precharging period, the PC, the control signal PBLCS is pulled up, so the transistor 711 is turned on and the control signal BLC is pulled up. During the bit line precharging period PC, the control signal SENC turns on the transistor 720, and the control signal BLC drives the transistor 730 to precharge the bit line BL. The transistor 730 can set the level of the bit line BL to an appropriate precharge level (for example, 0.5V). The precharge level of the bit line BL is fed back to the control terminal of the transistor 712, so that the transistor 712 can dynamically adjust the level of the control signal BLC according to the level of the bit line BL.

After the PC ends during the bit line precharging period, the control signal PBLCS is pulled down, so the transistor 711 is turned off, so that the control signal BLC is pulled down by the transistor 712. Then, during the initialization period 801 of the word line enable period WLE, the control signal SENC turns on the transistor 720 and the control signal BLC turns off the transistor 730. The transistor 720 can set the level of the node SEN to the precharge level (reference voltage VSEN) during the initialization period 801. After the transistor 730 is turned off, the word line WL turns on the memory cell to be read, so that data is output to the precharged bit line BL.

After the initialization period 801 ends, the control signal SENC turns off the transistor 720. Then, during the WLE sensing period 802 during the word line enable period, the control signal PBLCS is pulled up again, so the transistor 711 is turned on and the control signal BLC is pulled up. During the sensing period 802, the control signal SENC turns off the transistor 720, and the control signal BLC drives the transistor 730 to sense the bit line BL. During the sensing period 802 and the data on the bit line BL is in the first logic state (for example, “1”), the transistor 730 is turned off, so that the node SEN is maintained at the precharge level (for example, 1.2V). In the sensing period 802 and when the data of the bit line BL is in the second logic state (for example, “0”), the transistor 730 is turned on, so the node SEN is discharged to a level close to the bit line BL. The level of the bit line BL (the level of the data voltage) is fed back to the control terminal of the transistor 712, so that the transistor 712 can dynamically adjust the level of the control signal BLC according to the level of the bit line BL.

During the bit line precharge period PC and the sensing period 802, the control circuit 710 can dynamically control the control signal BLC according to the level of the bit line BL. Therefore, the sense amplifier 700 can realize high-speed bit line precharging and sensing.

FIG. 9 is a schematic circuit diagram of a voltage generating circuit according to an embodiment of the present invention. The power supply voltage VP, the bias voltage VBLP, and the reference voltage VSS shown in FIG. 9 may be provided by other devices (not shown, such as a controller, a reference voltage generating circuit, etc.). The bias voltage VBLP may be a bit line precharge level target (for example, 0.5V). The voltage generating circuit shown in FIG. 9 can provide voltage to the control circuit 710, and all the sense amplifiers share a voltage generating circuit. In the voltage generator shown in FIG. 9, the level of the power supply voltage VP is the same as the high logic level of the control signal PBLCS, and the level of the output voltage VN is the same as the low logic level of the control signal NBLCS. The bias voltage VBLP can control the level of the reference voltage VREF_BLC and the level of the output voltage VN, and the bit line precharge level becomes the same as the level of the bias voltage VBLP.

The first terminal (for example, the source) of the transistor 913 receives the power supply voltage VP. The second terminal (for example, the drain) of the transistor 913 is coupled to the control terminal (for example, the gate) of the transistor 913, and provides a reference voltage VREF_BLC. The first end (for example, the drain) of the transistor 914 is coupled to the second end of the transistor 913. The second terminal (for example, the source) of the transistor 914 is coupled to the current source IBLC and provides an output voltage VN. The control terminal (eg, gate) of the transistor 914 receives the bias voltage VBLP. The current source IBLC is also coupled to the reference voltage VSS. The current source IBLC can control the current consumption in the control circuit 710 of the sense amplifier.

FIG. 10 is a schematic circuit diagram illustrating the sense amplifiers 410-430 shown in FIG. 4 according to another embodiment of the present invention. The reference voltage VSEN0~VSEN1, the control signal SENC0~SENC1, the control signal BLC0~BLC1, the voltage PCS, the voltage NCS, and the control signal EQ shown in FIG. ) To provide.

Please refer to FIG. 10, the sense amplifier 410 includes transistors 411-412. The first terminal (for example, the source) of the transistor 411 is coupled to the reference voltage VSEN0. The second terminal (for example, the drain) of the transistor 411 is coupled to the output terminal of the sense amplifier 410 to output the amplified signal (or the reference voltage VSEN0) to the node SEN0. The control terminal (such as the gate) of the transistor 411 is controlled by the control signal SENC0. The first terminal (for example, the source) of the transistor 412 is coupled to the input terminal of the sense amplifier 410 to receive the data signal of the bit line BLa. The second end (for example, the drain) of the transistor 412 is coupled to the second end of the transistor 411. The control terminal (such as the gate) of the transistor 412 is controlled by the control signal BLC0. The sense amplifier 410, the transistor 411, and the transistor 412 shown in FIG. 10 can be deduced by referring to the related description of the sense amplifier 500, the transistor 510 and the transistor 520 shown in FIG.

The sense amplifier 420 includes transistors 421 and 422. The first terminal (for example, the source) of the transistor 421 is coupled to the reference voltage VSEN1. The second terminal (for example, the drain) of the transistor 421 is coupled to the output terminal of the sense amplifier 420 to output the amplified signal (or the reference voltage VSEN1) to the node SEN1. The control terminal (such as the gate) of the transistor 421 is controlled by the control signal SENC1. The first terminal (for example, the source) of the transistor 422 is coupled to the input terminal of the sense amplifier 420 to receive the data signal of the bit line BLb. The second end (for example, the drain) of the transistor 422 is coupled to the second end of the transistor 421. The control terminal (such as the gate) of the transistor 422 is controlled by the control signal BLC1. The sense amplifier 420, the transistor 421, and the transistor 422 shown in FIG. 10 can be deduced by analogy with reference to the related description of the sense amplifier 500, the transistor 510 and the transistor 520 shown in FIG.

The sense amplifier 430 includes transistors 431 to 435. The first terminal and the second terminal (eg source and drain) of the transistor 435 are respectively coupled to the bit lines BLa and BLb. The control terminal (such as the gate) of the transistor 435 is controlled by the control signal EQ.

The first terminal (for example, the source) of the transistor 431 and the first terminal (for example, the source) of the transistor 432 are coupled to the voltage PCS. The level of the voltage PCS can be determined according to design requirements. The second terminal (for example, the drain) of the transistor 431 and the control terminal (for example, the gate) of the transistor 432 are coupled to the first output terminal of the sense amplifier 430, wherein the first output terminal of the sense amplifier 430 can be The amplified signal is fed back to the input terminal of the sense amplifier 410. The control terminal (such as the gate) of the transistor 431 and the second terminal (such as the drain) of the transistor 432 are coupled to the second output terminal of the sense amplifier 430, wherein the second output terminal of the sense amplifier 430 can be The amplified signal is fed back to the input terminal of the sense amplifier 420.

The first terminal (for example, the source) of the transistor 433 and the first terminal (for example, the source) of the transistor 434 are coupled to the voltage NCS. The level of voltage NCS can be determined according to design requirements. The second end (for example, the drain) of the transistor 433 is coupled to the first output end of the sense amplifier 430, wherein the first output end of the sense amplifier 430 can feed the amplified signal back to the input of the sense amplifier 410 end. The control terminal (such as the gate) of the transistor 433 is coupled to the second input terminal of the sense amplifier 430 to receive the amplified signal (or the reference voltage VSEN1) from the node SEN1. The second end (for example, the drain) of the transistor 434 is coupled to the second output end of the sense amplifier 430, wherein the second output end of the sense amplifier 430 can feed the amplified signal back to the input of the sense amplifier 420 end. The control terminal (such as the gate) of the transistor 434 is coupled to the first input terminal of the sense amplifier 430 to receive the amplified signal (or the reference voltage VSEN0) from the node SEN0.

FIG. 11 is a schematic diagram illustrating the timing of the signal shown in FIG. 10 according to an embodiment of the present invention. In FIG. 11, the dashed waveform represents the signal with the label "0" (for example, SENC0, VSEN0, BLC0, and SEN0), and the solid line represents the signal with the label "1" (for example, SENC1, VSEN1, BLC1, and SEN1). Please refer to Figure 10 and Figure 11. During the precharge period of the bit line PC, the voltages PCS and NCS are pulled up (for example, from 0.3 V to 0.5 V), the reference voltage VSEN0 is at a high level (for example, 1.3 V), and the reference voltage VSEN1 is at a low level (for example, 0.5 V), the control signals SENC0 and SENC1 are both low level (such as 0 V), the control signal BLC0 is high level, and the control signal BLC1 is low level (such as 0 V). Therefore, during the bit line precharge period PC, the transistor 412 can precharge the bit line BL0 (for example, from 0.3 V to 0.5 V), and the transistor 411 can set the node SEN0 to the level of the reference voltage VSEN0 ( For example, 1.3 V), and the transistor 421 can set the node SEN1 to the level of the reference voltage VSEN1 (for example, 0.5 V).

After the PC ends during the bit line precharging period, the control signal BLC0 is pulled down, so the transistor 412 is turned off. After the transistors 412 and 422 are turned off, the word line WL turns on the memory cell to be read, so that the memory cell to be read outputs data to the precharged bit line BLa. Next, during the initialization period 1101 of the WLE during the word line enable period, the control signals SENC0 and SENC1 turn on the transistors 411 and 421, and the control signals BLC0 and BLC1 turn off the transistors 412 and 422. The transistors 411 and 421 can set the levels of the nodes SEN0 and SEN1 to the levels of the reference voltages VSEN0 and VSEN1 during the initialization period 1101.

After the initialization period 1101 ends, the control signal SENC0 is pulled up (for example, pulled up from 0 V to 1.3 V) to turn off the transistor 411. Then, during the sensing period 1102 of the WLE during the word line enable period, the control signal SENC0 is at a high level (for example, 1.3 V) and the control signal SENC1 is at a low level (for example, 0 V), so that when the sense amplifier 410 will respond When the amplified signal of the signal on the bit line BLa is output to the node SEN0, the transistor 421 can set the node SEN1 to the level of the reference voltage VSEN1 (for example, 0.5 V). During the sensing period 1102, the control signal BLC0 is pulled up again and the control signal BLC1 maintains a low level, so the transistor 422 is turned off and the transistor 412 can sense the bit line BLa. While the sense amplifier 410 senses the bit line BLa, the control signal SENC1 turns on the transistor 421 and the control signal BLC1 turns off the transistor 422.

FIG. 12 is a schematic circuit diagram illustrating the sense amplifiers 410 to 430 of FIG. 4 according to still another embodiment of the present invention. The sense amplifier 430 and the transistors 431 to 435 in FIG. 12 can be deduced by analogy with reference to the related description of the embodiment in FIG. 10, so they will not be described again. The reference voltage VSEN0~VSEN1, the control signal SENC0~SENC1, the control signal PBLCS0~PBLCS1, the control signal NBLCS0~NBLCS1, the voltage PCS, the voltage NCS, the reference voltage VREF_BLC, and the control signal EQ shown in Figure 12 can be made by other devices (not shown) , Such as controller, reference voltage generating circuit, etc.) to provide.

Please refer to FIG. 12, the sense amplifier 410 includes transistors 411 to 414. The first terminal (for example, the source) of the transistor 411 is coupled to the reference voltage VSEN0. The second terminal (for example, the drain) of the transistor 411 is coupled to the output terminal of the sense amplifier 410 to output the amplified signal (or the reference voltage VSEN0) to the node SEN0. The control terminal (such as the gate) of the transistor 411 is controlled by the control signal SENC0. The first terminal (for example, the source) of the transistor 412 is coupled to the input terminal of the sense amplifier 410 to receive the data signal of the bit line BLa. The second end (for example, the drain) of the transistor 412 is coupled to the second end of the transistor 411. The control terminal (such as the gate) of the transistor 412 is controlled by the control signal BLC0. The first end (for example, the source) of the transistor 413 receives the control signal PLBCS0. The second end (for example, the drain) of the transistor 413 is coupled to the control end of the transistor 412 to provide the control signal BLC0. The control terminal (such as the gate) of the transistor 413 is controlled by the reference voltage VREF_BLC. The first terminal (for example, the source) of the transistor 414 receives the control signal NBLCS0. The second end (for example, the drain) of the transistor 414 is coupled to the second end of the transistor 413. The control terminal (eg, gate) of the transistor 414 is coupled to the bit line BLa. The sense amplifier 410 and the transistors 411 to 414 in FIG. 12 can be deduced by referring to the related descriptions of the sense amplifier 700, the transistor 720, the transistor 730, the transistor 711, and the transistor 712 in FIG.

The sense amplifier 420 includes transistors 421 to 424. The first terminal (for example, the source) of the transistor 421 is coupled to the reference voltage VSEN1. The second terminal (for example, the drain) of the transistor 421 is coupled to the output terminal of the sense amplifier 420 to output the amplified signal (or the reference voltage VSEN1) to the node SEN1. The control terminal (such as the gate) of the transistor 421 is controlled by the control signal SENC1. The first terminal (for example, the source) of the transistor 422 is coupled to the input terminal of the sense amplifier 420 to receive the data signal of the bit line BLb. The second end (for example, the drain) of the transistor 422 is coupled to the second end of the transistor 421. The control terminal (such as the gate) of the transistor 422 is controlled by the control signal BLC1. The first end (for example, the source) of the transistor 423 receives the control signal PLBCS1. The second end (for example, the drain) of the transistor 423 is coupled to the control end of the transistor 422 to provide the control signal BLC1. The control terminal (such as the gate) of the transistor 423 is controlled by the reference voltage VREF_BLC. The first terminal (for example, the source) of the transistor 424 receives the control signal NBLCS1. The second end (for example, the drain) of the transistor 424 is coupled to the second end of the transistor 423. The control terminal (eg, gate) of the transistor 424 is coupled to the bit line BLb. The sense amplifier 420 and the transistors 421 to 424 in FIG. 12 can be deduced by analogy with reference to the relevant descriptions of the sense amplifier 700, the transistor 720, the transistor 730, the transistor 711, and the transistor 712 shown in FIG.

FIG. 13 is a schematic diagram illustrating the timing of the signal shown in FIG. 12 according to an embodiment of the present invention. In Figure 13, the dashed waveform represents the signal with the label "0" (for example, SENC0, VSEN0, PBLCS0, BLC0, and SEN0), and the solid line represents the signal with the label "1" (for example, SENC1, VSEN1, PBLCS, BLC1, and SEN1). ). Please refer to Figure 12 and Figure 13. During the precharge period of the bit line PC, the voltages PCS and NCS are pulled up (for example, from 0.3 V to 0.5 V), the reference voltage VSEN0 is at a high level (for example, 1.3 V), and the reference voltage VSEN1 is at a low level (for example, 0.5 V), the control signals SENC0 and SENC1 are both low level (such as 0 V), the control signal PLBCS0 is high level (such as 1.3 V), the control signal PLBCS1 is low level (such as 0 V), and the control signal NBLCS0 and NBLCS1 is low level. Therefore, during the bit line precharge period PC, the control signal BLC0 is pulled high so that the transistor 412 can precharge the bit line BL0 (for example, from 0.3 V to 0.5 V), while the control signal BLC1 is maintained at a low level (For example, 0 V) makes the transistor 422 cut off. During the pre-charging period of the bit line PC, the transistor 411 can set the node SEN0 to the level of the reference voltage VSEN0 (for example, 1.3 V), and the transistor 421 can set the node SEN1 to the level of the reference voltage VSEN1 (for example, 0.5 V). ).

After the PC ends during the bit line precharging period, the control signal BLC0 is pulled down, so the transistor 412 is turned off. After the transistors 412 and 422 are turned off, the word line WL turns on the memory cell to be read, so that the memory cell to be read outputs data to the precharged bit line BLa. Next, during the initialization period 1301 of the WLE during the word line enable period, the control signals SENC0 and SENC1 turn on the transistors 411 and 421, and the control signals BLC0 and BLC1 turn off the transistors 412 and 422. The transistors 411 and 421 can set the levels of the nodes SEN0 and SEN1 to the levels of the reference voltages VSEN0 and VSEN1 during the initialization period 1301.

After the initialization period 1301 ends, the control signal SENC0 is pulled up (for example, pulled up from 0 V to 1.3 V) to turn off the transistor 411. Then, in the sensing period 1302 of the WLE during the word line enable period, the control signal SENC0 is at a high level (for example, 1.3 V) and the control signal SENC1 is at a low level (for example, 0 V), so that when the sense amplifier 410 will respond When the amplified signal of the signal on the bit line BLa is output to the node SEN0, the transistor 421 can set the node SEN1 to the level of the reference voltage VSEN1 (for example, 0.5 V). During the sensing period 1302, the control signal BLC0 is pulled up again and the control signal BLC1 maintains a low level, so the transistor 422 is turned off and the transistor 412 can sense the bit line BLa. While the sense amplifier 410 senses the bit line BLa, the control signal SENC1 turns on the transistor 421 and the control signal BLC1 turns off the transistor 422.

In summary, the present invention discloses a two-stage sensing amplifier (sensing amplifying device 400). In the sense amplifier device 400, the small signal (data signal) of the bit line BLa or BLb is amplified by the sense amplifier 410 or 420 of the first stage, and then the amplified signal is output to the sense amplifier 430 of the second stage. The sense amplifier 430 may receive the amplified differential signal, and perform a second stage amplifying operation on the amplified differential signal. Therefore, the sensing amplifying device 400 can sense the data of the bit line BLa and/or BLb. The intensity of the differential signal received by the sense amplifier 430 is greater than the intensity of the differential signal received by the sense amplifier 150 shown in FIG. 1. Although the manufacturing process has been scaled down, the sensing amplifying device 400 can still achieve sufficient sensing signal tolerance. Therefore, the sense amplification device 400 may not require precise bit line capacitance matching. The edge sub-array (for example, the sub-array 110 or 140 shown in FIG. 1) can be equipped with sensing and amplifying devices 400 on both sides, and all the memory cells of the edge sub-array can be used.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: Dynamic random access memory 110~140: Sub-array 150, 410, 420, 430, 500, 700: Sense amplifier 400: Sense amplifier 411~414, 421~424, 431~435, 510~520 , 711~712, 720, 730, 913~914: Transistor 601, 801, 1101, 1301: Initialization period 602, 802, 1102, 1302: Sensing period 710: Control circuit BL, BL0, BL1, BLa, BLb: Bit lines BLC, BLC0, BLC1, CSP, CSN, EQ, NBLCS, NBLCS0, NBLCS1, PLBCS, PBLCS0, PLBCS1, SENC, SENC0, SENC1: control signal C _BL : capacitor C _SN : memory element IBLC: current source MC, MC1, MC2: memory cell NCS, PCS: voltage PC: bit line precharge period SEN, SEN0, SEN1: node SN: data SW: switch VBLP: bias voltage VN: output voltage VP: power supply voltage VREF_BLC, VSEN, VSEN0 , VSEN1, VSS: reference voltage WL: word line WLE: character line enable period

FIG. 1 shows a schematic diagram of a circuit block of a memory cell array in a dynamic random access memory. FIG. 2 illustrates the sense amplifier and bit line shown in FIG. 1. FIG. 3 is a schematic diagram showing the waveforms of the word line, control signal, data and bit line shown in FIG. 2. FIG. 4 is a schematic block diagram of a circuit of a sensing and amplifying device according to an embodiment of the present invention. FIG. 5 is a schematic circuit diagram of a sense amplifier according to an embodiment of the invention. FIG. 6 is a schematic diagram illustrating the timing of the signal shown in FIG. 5 according to an embodiment of the present invention. FIG. 7 is a schematic circuit diagram of a sense amplifier according to another embodiment of the present invention. FIG. 8 is a schematic diagram illustrating the timing of the signal shown in FIG. 7 according to an embodiment of the present invention. FIG. 9 is a schematic circuit diagram of a voltage generating circuit according to another embodiment of the present invention. FIG. 10 is a schematic diagram illustrating a circuit of the sense amplifier shown in FIG. 4 according to another embodiment of the present invention. FIG. 11 is a schematic diagram illustrating the timing of the signal shown in FIG. 10 according to an embodiment of the present invention. FIG. 12 is a schematic diagram illustrating a circuit of the sense amplifier shown in FIG. 4 according to still another embodiment of the present invention. FIG. 13 is a schematic diagram illustrating the timing of the signal shown in FIG. 12 according to an embodiment of the present invention.

400: Sensing amplification device

410, 420, 430: sense amplifier

BLa, BLb: bit line

MC1, MC2: memory cell

SEN0, SEN1: Node

VSEN0, VSEN1: reference voltage

Claims (10)

A sensing amplifier device includes: a first sensing amplifier having an input end coupled to a first bit line; a second sensing amplifier having an input end coupled to a second bit line; And a third sense amplifier having a differential input pair and a differential output pair, wherein a first input end of the differential input pair is coupled to an output end of the first sense amplifier, and the differential A second input terminal of the input pair is coupled to an output terminal of the second sense amplifier, a first output terminal of the differential output pair is coupled to the input terminal of the first sense amplifier, and the difference A second output end of the dynamic output pair is coupled to the input end of the second sense amplifier, wherein the first sense amplifier includes: a first transistor having a first end coupled to a first reference Voltage, wherein a second terminal of the first transistor is coupled to the output terminal of the first sense amplifier, and a control terminal of the first transistor is controlled by a first control signal; and a second The transistor has a first end coupled to the input end of the first sense amplifier, wherein a second end of the second transistor is coupled to the second end of the first transistor, and the first end A control terminal of the two transistors is controlled by a second control signal. The sensing amplifier device of claim 1, wherein each of the first sensing amplifier and the second sensing amplifier is a non-differential signal amplifier, and the third sensing amplifier is a differential signal amplifier . The sensing amplification device according to claim 1, wherein the first transistor includes a PMOS transistor, and the second transistor includes an NMOS transistor. The sensing amplifier device according to claim 1, wherein, during a bit line precharging period before a word line enabling period, the first control signal turns on the first transistor and the second control signal drives The second transistor is used to precharge the first bit line; during an initialization period during the enabling period of the word line, the first control signal turns on the first transistor and the second control signal turns off the second battery Crystal; and in a sensing period of the word line enable period after the initialization period, the first control signal turns off the first transistor and the second control signal drives the second transistor to sense the first transistor One yuan line. The sensing amplification device according to claim 4, wherein, during the sensing period and when the data of the first bit line is in a first logic state, the second transistor is turned off; and During the sensing period and when the data of the first bit line is in a second logic state, the second transistor is turned on. The sensing amplifier device of claim 1, wherein, during the period when the second sense amplifier is sensing the second bit line, the first control signal turns on the first transistor and the second control signal turns off The second transistor. The sensing amplifier device according to claim 1, wherein the first sensing amplifier further includes: a control circuit having an input terminal coupled to the input terminal of the first sensing amplifier for generating the second sensing amplifier The control signal is given to the control terminal of the second transistor, and the control circuit dynamically adjusts the second control signal according to the level of the input terminal of the first sense amplifier. The sensing and amplifying device according to claim 7, wherein the control circuit includes: a third transistor having a first end to receive a third control signal, wherein a second end of the third transistor is coupled to An output terminal of the control circuit generates the second control signal to the control terminal of the second transistor, and a control terminal of the third transistor is controlled by a second reference voltage; and a fourth transistor , Having a first end receiving a fourth control signal, wherein a second end of the fourth transistor is coupled to the second end of the third transistor, and a control end of the fourth transistor is coupled To the input terminal of the control circuit. The sensing amplifier device according to claim 8, wherein the third transistor includes a PMOS transistor, and the fourth transistor includes an NMOS transistor. The sensing amplifier device according to claim 1, wherein the third sensing amplifier includes: a first transistor having a first terminal coupled to a first voltage, wherein a second transistor of the first transistor Terminal is coupled to the first output terminal of the third sense amplifier, and a control terminal of the first transistor is coupled to the second terminal of the third sense amplifier Output terminal; a second transistor having a first terminal coupled to the first voltage, wherein a second terminal of the second transistor is coupled to the second output terminal of the third sense amplifier, and A control terminal of the second transistor is coupled to the first output terminal of the third sense amplifier; a third transistor having a first terminal coupled to a second voltage, wherein the third transistor A second terminal of the third sensor amplifier is coupled to the first output terminal, and a control terminal of the third transistor is coupled to the second input terminal of the third sense amplifier; and a first Four transistors having a first terminal coupled to the second voltage, wherein a second terminal of the fourth transistor is coupled to the second output terminal of the third sense amplifier, and the fourth transistor A control terminal of is coupled to the first input terminal of the third sense amplifier.

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