TW201942985A - 不使用載體之模腔扇出封裝及其製造方法 - Google Patents

不使用載體之模腔扇出封裝及其製造方法 Download PDF

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TW201942985A
TW201942985A TW108104681A TW108104681A TW201942985A TW 201942985 A TW201942985 A TW 201942985A TW 108104681 A TW108104681 A TW 108104681A TW 108104681 A TW108104681 A TW 108104681A TW 201942985 A TW201942985 A TW 201942985A
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molding
die
frame
molding compound
rdl
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TW108104681A
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TWI856007B (zh
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明皓 沈
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中國大陸商 成都奕斯偉系統技術有限公司
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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Abstract

揭示了一種製造一半導體裝置之方法，所述方法包含模製及固化一成框部件，所述成框部件具有界定一凹陷陣列之一上側。然後將半導體晶粒黏合到各別凹陷內之所述成框部件上。所述成框部件之所述上側及所述晶粒覆蓋有一RDL。所述RDL之形成包含一介電材料之沈積，所述介電材料亦填充所述凹陷內之所述晶粒及所述成框部件之間的間隙。所述成框部件可被模製成具有一定厚度，所述厚度可提供機械強度以抵抗在所述RDL之所述形成或其它製造製程期間對所述晶粒之損壞，例如由於所述晶粒之翹曲。在完成所述RDL之後，然後可以從所述成框部件之下側移除此過量成框部件材料，並且可以切割所述結構以將所述晶粒分離成各別半導體裝置。

Description

不使用載體之模腔扇出封裝及其製造方法
相關申請
本申請要求2018年2月9日提交之題為《模腔扇出（Molded Cavity Fanout）》之美國臨時申請第62/628,500號的優先權，其以全文引用之方式併入本文中。
本揭示案係關於半導體封裝技術。
半導體裝置通常可見於現代電子產品中。半導體裝置之電子組件之數目及密度不同。分立半導體裝置通常含有一種類型之電子組件，例如發光二極管（LED）、小信號電晶體、電阻器、電容器、電感器及功率金屬氧化物半導體場效應電晶體（MOSFET）。積體半導體裝置通常含有數百至數百萬個電子組件。積體半導體裝置之實例包含微控制器、微處理器、電荷耦合裝置（CCD）、太陽能電池及數位微鏡裝置（DMD）。
半導體裝置執行廣泛多種功能，諸如信號處理、高速計算、發射及接收電磁信號、控制電子裝置、將太陽光轉變為電能，以及為電視顯示器創建視覺投影。半導體裝置可見於娛樂、通信、電力轉換、網路、電腦及消費產品領域。半導體裝置亦可見於軍事應用、航空、汽車、工業控制器及辦公設備。
半導體裝置利用半導體材料之電特性。半導體材料之原子結構允許藉由應用電場或基極電流或經由摻雜製程來操縱其導電性。摻雜將雜質引入半導體材料中以操縱及控制半導體裝置之導電性。
半導體裝置含有主動及被動電結構。包含雙極及場效電晶體之主動結構控制電流之流動。藉由改變摻雜位準及應用電場或基極電流，電晶體促進或限制電流之流動。包含電阻器、電容器及電感器之被動結構在執行各種電氣功能所需之電壓及電流之間建立了關係。被動及主動結構電連接以形成電路，這使得半導體裝置能夠執行高速計算及其它有用功能。
半導體裝置通常使用兩個複雜之製造製程來製造，即前端製造及後端製造，各製造製程包括潛在之數百個步驟。前端製造包括在半導體晶圓之表面上形成複數個晶粒。各半導體晶粒通常為相同的，且含有藉由電連接主動與被動組件而形成之電路。後端製造包括自成品晶圓中單體化單獨半導體晶粒並封裝晶粒以提供結構支撐及環境隔離。
在本說明書中，術語「晶粒」、「半導體晶片」及「半導體晶粒」可互換使用。本文中使用之術語晶圓包含具有曝露表面之任何結構，根據本發明在其上沈積有一層，例如，以形成電路結構。
圖1A至1E示出了用於製造具有再分佈層（RDL）之半導體封裝之典型方法的示意性橫截面圖。
參考圖1A，將多個半導體晶粒100置放在黏合層102上，黏合層102又施加到載體基板104上。各晶粒100包含由半導體材料製成之基板，所述半導體材料諸如砷化鎵（GaAs）、氮化鎵（GaN）或矽（Si），其上（或其中）形成有積體電路。接下來，如圖1B所示，在半導體晶粒100上及黏合層102之曝露部分上沈積（或形成）封裝材料106。取決於用作封裝材料106之材料，然後執行固化製程以至少部分地固化封裝材料106。
在封裝材料106固化之後，封裝材料106變為部分剛性並形成封裝結構。封裝材料106具有大於期望之初始厚度。因此，封裝材料106之曝露表面經歷研磨（及/或拋光及/或磨蝕）製程以曝露晶粒100，如圖1C所示。在一些情況下，可以對封裝材料106之表面進行化學機械拋光製程。參照圖1D，在晶粒100上方形成RDL層108，包含與晶粒100電連通之各種絕緣層及導電跡線。此外，可以形成與RDL層108電連通之接觸結構（例如，焊球）110。參考圖1E，然後將載體基板104及黏合層102從結構上脫黏。從此處，可以將結構切割（cut/diced）成具有晶粒100中之各別晶粒之單獨半導體裝置。
如上所述封裝製程之封裝製程具有若干缺點。封裝製程通常包含使用載體基板104，因為需要強力機械支撐來防止翹曲。載體基板104之添加及移除為所述製程增加了另外的步驟，這增加了製造之時間及費用。而且，使用另外的封裝劑來填充晶粒100之間的間隙。由於研磨掉過量封裝劑之步驟，這也增加了製造費用並增加了製造時間。因此，在工業中存在對改進之封裝製程之需求，與先前製程相比，所述製程可以降低成本及製造時間。
根據本揭示案之一些實施例，一種製造半導體裝置之方法包含提供配置成形成具有複數個凹陷之模製結構之第一及第二模製板。接下來，在第一及第二模製板之間分配模製化合物，且然後將第一及第二模製板集合在一起，以在第一及第二模製板之間模製所述模製化合物；然後凝固模製化合物，藉此形成成框部件，所述成框部件包括在成框部件中界定複數個凹陷的複數個成框結構。接下來，將各複數個晶粒黏合到成框部件之各別凹陷內之成框部件，使得各複數個晶粒至少部分地由複數個成框結構中之至少一者包圍。在一些此類實施例中，各晶粒具有各別主動表面及至少一個各別積體電路區域。接下來，在成框部件之晶粒及成框結構上形成再分佈層（RDL），藉此產生多晶粒面板。在一些此類實施例中，RDL之形成包含在各晶粒及各別相鄰成框結構之間的複數個凹陷中形成介電結構。接下來，沿複數個成框結構切割（cut/diced）多層面板以獲得個別分開半導體裝置。
在一些實施例中，模製化合物可包括環氧樹脂。在一些此類實施例中，模製化合物之凝固可包含固化環氧樹脂。
在一些實施例中，所述方法可進一步包括在第一及第二模製板之間提供離型膜，使得在將第一及第二模製板集合在一起之前，所述離型膜在模製化合物與第一及第二模製板中之至少一者之間。
在一些實施例中，成框部件之複數個凹陷被配置在成框部件之第一側上，並且其中所述方法進一步包括從成框部件之第二側移除成框部件之材料，第二側與成框部件之第一側相對。
在一些實施例中，各複數個晶粒包括矽。
在一些實施例中，RDL層包含電連接到各別晶粒之導電結構。
根據本揭示案之一些實施例，一種製造半導體裝置之方法包含提供複數個模製板，所述複數個模製板配置成形成具有第一及第二凹陷之模製結構。接下來，使用複數個模製板使模製化合物成形，且然後凝固模製化合物，藉此形成成框部件，所述成框部件包括在成框部件中界定第一及第二凹陷之複數個成框結構；接下來，將第一及第二晶粒分別黏合到成框部件之第一及第二凹陷內之成框部件，使得各第一及第二晶粒至少部分地由複數個成框結構中之至少一者包圍。在一些實施例中，各第一及第二晶粒具有各別主動表面及至少一個各別積體電路區域。接下來，在成框部件之第一及第二晶粒及成框結構上形成再分佈層（RDL），藉此產生多晶粒面板。在一些實施例中，RDL之形成可包含在各第一及第二晶粒及各別相鄰成框結構之間在第一及第二凹陷中形成介電結構。接下來，沿複數個成框結構切割（cut/diced）多層面板以獲得個別分開半導體裝置。
在一些實施例中，模製化合物包括環氧樹脂。在一些此類實施例中，模製化合物之凝固可包含固化環氧樹脂。
在一些實施例中，所述方法可進一步包括鄰近各複數個模製板中之至少一者提供離型膜，使得在模製化合物之成形之前，離型膜在模製化合物與複數個模製板中之至少一者之間。
在一些實施例中，成框部件之第一及第二凹陷被配置在成框部件之第一側上。在一些此類實施例中，所述方法可進一步包括從成框部件之第二側移除成框部件之材料，所述第二側與成框部件之第一側相對。
在一些實施例中，各第一及第二晶粒包括矽。
在一些實施例中，RDL層包含電連接到第一及第二晶粒中之至少一者之導電結構。
根據本揭示案之一些實施例，一種半導體裝置包括具有主動表面及至少一個積體電路區域之晶粒。所述裝置亦包括鄰近所述晶粒之成框結構及至少部分地介於晶粒及成框結構之介電結構。所述裝置進一步包括在晶粒上、在成框結構上及在介電結構上之再分佈層（RDL）。在一些此類實施例中，RDL電連接到晶粒。
在一些實施例中，成框結構可包括模製化合物。在一些此類實施例中，模製化合物可包括環氧樹脂。
在一些實施例中，晶粒包括矽。
在一些實施例中，RDL至少包括介電層及在介電層中之金屬特徵。在一些此類實施例中，金屬特徵中之至少一者電連接到晶粒。
本揭示案係關於一種晶圓級封裝製程。例如，在半導體晶圓封裝製程中，晶圓可為其上具有數千個晶片之半導體晶圓或裝置晶圓。薄晶圓，尤其超薄晶圓（厚度小於60微米或甚至30微米）非常不穩定，且比傳統厚晶圓更容易受到應力影響。在處理期間，薄晶圓可能容易破裂及翹曲。因此，臨時黏合到剛性支撐載體基板可以降低損壞晶圓之風險。然而，支撐載體之使用包括附接載體基板並隨後移除載體基板。此等附加步驟允許以包括在製造製程中之另外時間及費用為代價來獲得所需之增加剛性。因此，本文揭示之方法允許不需要使用載體基板之的晶圓級封裝製程。相反，成框部件模製成具有用於支撐各別晶粒之一個或多個空腔。然後可以使用所需之半導體封裝操作（包含RDL形成及切割成個別分開晶片）來處理具有成框部件支撐之晶粒。
在本發明之以下詳細描述中，參考了附圖，所述附圖形成了本發明之一部分，並且其中藉助於說明之方式示出了可以實踐本發明的特定實施例。足夠詳細地描述此等實施例，以使熟習此項技術者能夠實踐本發明。在不脫離本發明之範疇之情況下，可使用其它實施例且可進行結構改變。
因此，以下詳細描述不應被視為具有限制意義，並且本發明之範疇僅由所附申請專利範圍以及此類申請專利範圍所賦予的等同物的完整範疇來限定。
現在將參考附圖描述本發明之一或多個實施方式，其中相同之附圖標記始終用於表示相同之元件，且其中所說明之結構不一定按比例繪製。
圖2A-2D示出了根據本揭示案之用於製造晶圓級封裝之例示性方法的示意性橫截面圖。
更特定言之，圖2A示出了根據本揭示案之實施例的用於模製成框部件的模製設備（在圖2B中最佳地示出了形成的成框部件208）。模製設備包含第一模製板202、第二模製板204及離型膜205，並一次全部地及單獨地模製成框部件之成框結構與凹陷。雖然結合所示實施例示出並描述了兩個模製板，但應當瞭解，替代實施例可以包含兩個以上板，所述兩個以上板可配置成一起工作以形成根據本揭示案之成框部件208。
第一模製板202可由例如金屬製成，且多個突起部207形成於第一模製板202中並從第一模製板202之按壓表面延伸。突起部207在數量及位置上對應於由成框部件支撐之半導體晶粒214（例如，如圖2C所示）。突起部207形成為由第一模製板202支撐之矩形形狀的按壓部件。在包含多於兩個模製板之替代實施例中，突起部207可以全部提供在單個模製板上，或者突起部207可以分佈在多於一個模製板之間。突起部207成形為允許在模製化合物206（例如，諸如由圖2B中之橫截面圖及圖3中之平面圖所示之成框結構210界定的凹陷212）中形成各別矩形或正方形凹陷（如在平面圖中，例如在圖3中觀察到的）。替代地，代替形成矩形或正方形凹口或除了形成矩形或正方形凹口之外，還可以為在模製化合物206中形成之凹口選擇任何期望之形狀。突起部207之尺寸可以根據需要選擇，較佳地至少部分地基於放置在其中的晶粒的尺寸。第二模製板204包含例如可由金屬形成之按壓體。
可在第一模製板202與第二模製板204之間的第二模製板204的接觸表面上提供視情況選用之離型膜205，使得在將模製化合物206供應到模製設備之前，離型膜205在模製化合物206與第一模製板202與第二模製板204中之至少一者之間。在一些實施例中，第一模製板202及/或第二模製板204可配置成加熱模製化合物206，以便作為形成成框部件208之製程的一部分而固化或硬化模製化合物206。在此類實施例中，離型膜205可以在固化製程期間保持在第一及第二模製板202、204之間的適當位置。離型膜205可以具有彈性及耐熱性，並且可能希望其在低於模製設備被加熱之溫度的溫度下具有軟化特性。例如，在一些實施例中，第一及/或第二模製板202、204可以加熱至約150℃，因此較佳地將離型膜205之軟化溫度選擇為等於或高於150℃。例如，離型膜205可包括熱塑性氟樹脂（例如，ETFE）塑膠膜。
在一些實施例中，模製化合物206可為用於半導體之若干已知環氧模製化合物中的任一者，較佳地為適合於壓縮模製的已知類型。模製化合物206之壓縮模製可藉由將模製化合物206置放到由第一及第二模製板202、204界定之模腔中來完成。在一些實施例中，模製化合物206及/或第一及/或第二模製板202、204可在將模製化合物206置放在圖2A所示之模製設備中之前被預熱。由第一及第二模製板202、204界定之模腔藉由使第一及第二模製板202、204更靠近在一起而閉合，例如藉由如圖2A中的箭頭所指示的頂部力。第一及第二模製板202、204施加壓力以迫使模製化合物206成形為基於在壓縮操作期間鄰近模製化合物206之第一及第二模製板202、204之表面形狀的形狀。
使用圖2A中所示之模製設備中模製製程可在部分固化階段中使用顆粒、油灰狀物質或預成型件形式的熱固性樹脂。在固化之前，環氧樹脂包含樹脂及固化劑。當聚合發生時，材料變成有時稱為「玻璃態」之有組織之晶體型結構。在此狀態下，分子可以振動但以其它方式鎖定在適當位置。隨著溫度升高，分子可以更自由地移動並且材料逐漸開始軟化。隨著溫度繼續升高，聚合物最終經歷深度狀態轉變為更柔韌的橡膠態。儘管這種狀態轉變在一定溫度範圍內逐漸發生，但玻璃化轉變溫度範圍（Tg）通常由特定溫度表示。實際的玻璃化轉變溫度範圍取決於幾個因素，包含材料的分子結構、樣品製備、固化時間表及固化程度。然而，作為實例，已知環氧模製化合物可用作具有在120℃及170℃範圍內之特定玻璃化轉變溫度（Tg）的模製化合物206。在此類實施例中，可將第一及/或第二模製板202、204加熱到模製化合物206的至少特定Tg，以便至少部分地固化模製化合物206。因此，第一及/或第二模製板202、204可以對模製化合物206施加熱及壓力，並且較佳保持熱及壓力直到模製化合物206已固化為止。然而，在一些實施例中，此時可以僅執行用於固化模製化合物206的固化製程的一部分，且可在稍後時間（諸如在以下結合圖2D描述之材料移除操作之後）完成固化製程。
圖2B為可使用圖2A中所示之模製設備形成之成框部件208的實施例的橫截面圖。此外，圖3示出了可使用圖2A所示之模製設備形成中成框部件208的實施例的平面圖。因此，成框部件208可由固化模製化合物206（例如環氧模製化合物）形成。成框部件208包括在成框部件208中界定複數個凹陷212的複數個成框結構210。成框部件208至少部分地用於消除在先前製程中使用之載體基板（諸如圖1A-1D中所示之載體基板104）之使用。
接下來轉向圖2C，複數個半導體晶粒214設置在成框部件208之凹陷212中。例如，半導體晶粒214可以使得各晶粒214具有各別主動表面及至少一個各別積體電路區域。在一些實施例中，晶粒214在成框部件208的各別凹陷212內黏合到成框部件208。較佳地，如圖2C所示，各複數個晶粒214被置放在各別凹陷212中，並且至少部分地由成框結構210包圍。
在一些實施例中，可以使用取放（PnP）程序將晶粒214置放在凹陷212中。較佳地藉由已知之PnP裝置（未示出）執行PnP程序。例如，典型之PnP裝置包含用於抓取要置放在凹陷212中之一者中的晶粒214的黏合頭。然後，黏合頭將晶粒214平移到凹陷212並將晶粒214附接在其中。此製程稱為取放運動。為了保持製造製程之總體品質及良好的產量，需要仔細的晶粒處理。由於晶粒214之精細性質（特別在晶粒214的作用側），使用PnP機器允許拾取、移動及置放晶粒214的最小接觸及相對力。然而，在一些實施例中，手動移除之程度可以與藉由使用PnP機器之自動化製程結合使用，或者代替藉由使用PnP機器之自動化製程而使用。然而，通常藉由使用PnP自動化來降低對晶粒214之機械損壞的可能性。此外，使用PnP裝置可允許減少製造時間，因為已知之PnP裝置可用來實現否則為困難的快速輸出轉向。此外，使用自動PnP裝置可以降低置放誤差，例如與晶粒方向相關之誤差。在一些實施例中，人工執行之任務可以包含在PnP裝置操作中。例如，一些PnP裝置允許操作者藉由在放大之屏幕上觀看晶粒214來手動調整X及Y座標以在拾取之晶粒214上居中。根據各種已知之PnP裝置及操作方法，可以以多種方式藉由PnP裝置收集拾取晶粒214。例如，在一些PnP裝置中，晶粒214可以藉由PnP裝置使用真空動力機械臂拾取，所述機械臂掃入適當位置，拾取晶粒214，並且然後將晶粒置放到期望的一個凹陷212中。為了允許晶粒214及成框部件208之間的牢固黏合，用於將晶粒214附接到凹陷212中的適當黏合時間及力為較佳。
可以使用形成黏合層215之黏合劑將晶粒214附接並保持在凹陷212中的適當位置。黏合層215可以為黏合帶，或替代地可以為經由旋塗製程等施加到凹陷212中之膠或環氧樹脂。在一些實施例中，黏合層215可包括例如可市售之晶粒附接膜（DAF）。在一些實施例中，黏合層215可包括例如市售之用於晶粒附接之環氧糊狀黏合劑
接下來轉到圖2D，在晶粒214上及成框部件208上形成再分佈層（RDL）216。RDL 216之形成包含用介電材料塗層或層壓晶粒214及成框部件208以平坦化上表面。現在亦參考圖4，其示出圖2D所示部分之放大圖，介電材料亦藉由填充晶粒214及其相鄰成框結構210之間的間隙來形成介電結構218。在一些實施例中，介電材料可能不能填充晶粒214與其相鄰成框結構210之間的間隙，這取決於如何處理介電材料或由於介電材料的尺寸。
RDL 216之其餘部分可以根據已知方法形成，通常包括金屬與介電材料層之形成。RDL 216之金屬結構電連接到晶粒214上之接觸點。此外，為了提供RDL 216及其它電路之間的電連接，形成複數個凸塊222，諸如微凸塊或銅柱。視情況，可以執行熱處理以回流凸塊222。
一旦完成上述製程，就可以使用材料移除製程從成框部件208移除過量材料。當形成成框部件208時，選擇厚度以提供足夠的機械強度以減輕晶圓翹曲，且藉此允許從晶粒214有效地製造半導體裝置。然而，一旦製造製程足夠接近完成以減少翹曲問題，就可以減小晶粒214背側上之成框部件208的過量厚度。材料移除製程可以包含例如研磨以從晶粒214的背面移除過量成框部分220。
可以理解，進一步處理可以包含沿切口區域的切割或鋸切製程，以將單獨晶粒214與其各別晶圓級封裝彼此分離。應理解，附圖中所示之截面結構僅用於說明目的。
圖5為示出根據本揭示案之用於製造晶圓級封裝之例示性方法的製程流程圖。在此實施例中，製造半導體裝置之方法開始於提供第一及第二模製板之步驟510，所述第一及第二模製板配置成形成具有複數個凹陷的模製結構。在一些實施例中，另外之模製板可與第一及第二模製板一起使用以形成具有複數個凹陷的模製結構。在一些實施例中，下一步驟520包含在第一及第二模製板之間分配模製化合物。在一些此類實施例中，可以在第一及第二模製板之間提供離型膜。在一些實施例中，下一步驟530可包含將模製板集合在一起，以便在由模製板界定之模腔中模製所述模製化合物。在一些此類實施例中，在將模製板集合在一起之前，可將離型膜置放在模製化合物與模製板中之至少一者之間。
在一些實施例中，下一步驟540可包含凝固模製化合物，藉此形成成框部件，所述成框部件包括界定成框部件中之複數個凹陷之複數個成框結構。在一些此類實施例中，模製化合物可包括環氧樹脂。在一些此類實施例中，模製化合物之凝固可包含例如使用熱及/或按壓來固化環氧樹脂。
在一些實施例中，下一步驟550可包含在成框部件的各別凹陷內將複數個晶粒黏合到成框部件，使得各複數個晶粒至少部分地由複數個成框結構中之至少一者包圍。在一些實施例中，各晶粒可包含具有各別主動表面及至少一個各別積體電路區域。在一些實施例中，各晶粒亦可以包括矽。在一些實施例中，下一步驟560可包含在成框部件之晶粒及成框結構上形成再分佈層（RDL），藉此產生多晶粒面板。在一些此類實施例中，RDL層可包含電連接到各別晶粒之導電結構。在一些此類實施例中，RDL之形成可包含在晶粒及其各別相鄰之成框結構之間的凹陷中形成介電結構。在一些實施例中，步驟560可包含一旦不再需要由過量成框材料提供之機械支撐，就從晶粒中背側移除成框部件之過量材料。在一些實施例中，下一步驟570可包含沿成框結構切割多層面板以獲得個別分開半導體裝置。
熟習此項技術者將容易地觀察到，可在保留本發明之教示之同時對裝置及方法進行多種修改及更改。因此，上述揭示內容應被解釋為僅受所附申請專利範圍之範圍及界限之限制。
100‧‧‧晶粒
102‧‧‧黏合層
104‧‧‧載體基板
106‧‧‧封裝材料
108‧‧‧RDL層
110‧‧‧接觸結構
202‧‧‧第一模製板
204‧‧‧第二模製板
205‧‧‧離型膜
206‧‧‧模製化合物
207‧‧‧突起部
208‧‧‧成框部件
210‧‧‧成框結構
212‧‧‧凹陷
214‧‧‧半導體晶粒
215‧‧‧黏合層
216‧‧‧RDL
218‧‧‧介電結構
220‧‧‧成框部分
222‧‧‧凸塊
510‧‧‧步驟
520‧‧‧步驟
530‧‧‧步驟
540‧‧‧步驟
550‧‧‧步驟
560‧‧‧步驟
570‧‧‧步驟
圖1A-1E示出了用於製造具有再分佈層（RDL）之半導體封裝之典型方法的示意性橫截面圖。
圖2A-2D示出了根據本揭示案之實施例之用於製造晶圓級封裝之例示性方法的示意性橫截面圖。
圖3示出了根據本揭示案之實施例之成框部件的實施例的平面圖。
圖4示出了圖2D之部分4的放大圖。
圖5示出了根據本揭示案之用於製造晶圓級封裝之例示性方法的製程流程圖。

Claims (20)

  1. 一種製造一半導體裝置之方法，其包括： 提供配置成形成具有複數個凹陷之一模製結構之第一及第二模製板； 在所述第一及第二模製板之間分配一模製化合物； 將所述第一及第二模製板集合在一起，以在所述第一及第二模製板之間模製所述模製化合物； 凝固所述模製化合物，藉此形成一成框部件，所述成框部件包括在所述成框部件中界定所述複數個凹陷之複數個成框結構； 將複數個晶粒黏合到所述成框部件之各別凹陷內之所述成框部件，使得所述複數個晶粒中之每一者至少部分地由所述複數個成框結構中之至少一者包圍，其中各晶粒具有一各別主動表面及至少一個各別積體電路區域； 在所述成框部件之所述晶粒及成框結構上形成一再分佈層（RDL），藉此產生一多晶粒面板，其中所述RDL之所述形成包含在所述晶粒中之每一者及各別相鄰成框結構之間的所述複數個凹陷中形成介電結構；及 沿所述複數個成框結構切割所述多層面板以獲得個別分開半導體裝置。
  2. 如申請專利範圍第1項所述之方法，其中所述模製化合物包括一環氧樹脂。
  3. 如申請專利範圍第2項所述之方法，其中所述模製化合物之所述凝固包含固化所述環氧樹脂。
  4. 如申請專利範圍第1項所述之方法，其更包括在所述第一及第二模製板之間提供一離型膜，使得在將所述第一及第二模製板集合在一起之前，所述離型膜在所述模製化合物與所述第一及第二模製板中之至少一者之間。
  5. 如申請專利範圍第1項所述之方法，其中所述成框部件之所述複數個凹陷被配置在所述成框部件之一第一側上，並且其中所述方法更包括從所述成框部件之一第二側移除所述成框部件之材料，所述第二側與所述成框部件之所述第一側相對。
  6. 如申請專利範圍第1項所述之方法，其中所述複數個晶粒中之每一者包括矽。
  7. 如申請專利範圍第1項所述之方法，其中所述RDL層包含電連接到各別晶粒之導電結構。
  8. 一種製造一半導體裝置之方法，其包括： 提供複數個模製板，所述複數個模製板配置成形成具有一第一及第二凹陷之一模製結構； 使用所述複數個模製板使一模製化合物成形； 凝固所述模製化合物，藉此形成一成框部件，所述成框部件包括在所述成框部件中界定所述第一及第二凹陷之複數個成框結構； 將第一及第二晶粒分別黏合到所述成框部件之所述第一及第二凹陷內之所述成框部件，使得所述第一及第二晶粒中之每一者至少部分地由所述複數個成框結構中之至少一者包圍，其中所述第一及第二晶粒中之每一者具有一各別主動表面及至少一個各別積體電路區域； 在所述成框部件之所述第一及第二晶粒及成框結構上形成一再分佈層（RDL），藉此產生一多晶粒面板，其中所述RDL之所述形成包含在所述第一及第二晶粒中之每一者及各別相鄰成框結構之間在所述第一及第二凹陷中形成介電結構；及 沿所述複數個成框結構切割所述多層面板以獲得個別分開半導體裝置。
  9. 如申請專利範圍第8項所述之方法，其中所述模製化合物包括一環氧樹脂。
  10. 如申請專利範圍第9項所述之方法，其中所述模製化合物之所述凝固包含固化所述環氧樹脂。
  11. 如申請專利範圍第8項所述之方法，其更包括鄰近所述複數個模製板中之至少一者提供一離型膜，使得在所述模製化合物之所述成形之前，所述離型膜在所述模製化合物與所述複數個模製板中之所述至少一者之間。
  12. 如申請專利範圍第8項所述之方法，其中所述成框部件之所述第一及第二凹陷被配置在所述成框部件之一第一側上，並且其中所述方法更包括從所述成框部件之一第二側移除所述成框部件之材料，所述第二側與所述成框部件之所述第一側相對。
  13. 如申請專利範圍第8項所述之方法，其中所述第一及第二晶粒中之每一者包括矽。
  14. 如申請專利範圍第8項所述之方法，其中所述RDL層包含電連接到所述第一及第二晶粒中之至少一者之導電結構。
  15. 一種半導體裝置，其包括： 一晶粒，其包括一主動表面及至少一個積體電路區域； 一成框結構，其鄰近所述晶粒； 一介電結構，其至少部分地介於所述晶粒及所述成框結構；及 一再分佈層（RDL），其在所述晶粒上、在所述成框結構上及在所述介電結構上，其中所述RDL電連接到所述晶粒。
  16. 如申請專利範圍第15項所述之半導體裝置，其中所述成框結構包括一模製化合物。
  17. 如申請專利範圍第16項所述之半導體裝置，其中所述模製化合物包括一環氧樹脂。
  18. 如申請專利範圍第17項所述之半導體裝置，其中所述晶粒包括矽。
  19. 如申請專利範圍第15項所述之半導體裝置，其中所述RDL至少包括一介電層及在所述介電層中之金屬特徵。
  20. 如申請專利範圍第19項所述之半導體裝置，其中所述金屬特徵中之至少一者電連接到所述晶粒。
TW108104681A 2018-03-29 2019-02-11 不使用載體之模腔扇出封裝及其製造方法 TWI856007B (zh)

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