TW201941420A - 具有縮小像素尺寸之微顯示器及其形成方法 - Google Patents

具有縮小像素尺寸之微顯示器及其形成方法 Download PDF

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TW201941420A
TW201941420A TW108105687A TW108105687A TW201941420A TW 201941420 A TW201941420 A TW 201941420A TW 108105687 A TW108105687 A TW 108105687A TW 108105687 A TW108105687 A TW 108105687A TW 201941420 A TW201941420 A TW 201941420A
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伊霍爾 瓦采克
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Abstract

本發明提供一種垂直堆疊像素電路，其包含一上矽層上用於驅動一像素之一高電壓裝置及一下矽層上之低電壓電路(諸如矩陣定址電路、資料儲存電路及均勻性補償電路)。該上矽層及該下矽層上之該電路經由一矽穿通路而電連接。此獨特配置允許用於驅動一像素之該高電壓裝置實體定位於該下矽層中之較多數目個低電壓裝置之頂部上以達成總像素發射面積之一實質縮小。該垂直堆疊像素電路尤其適合於有機發光二極體微顯示器。

Description

具有縮小像素尺寸之微顯示器及其形成方法
本發明大體上係關於顯示器，且更特定言之，本發明係關於具有超小像素大小之有機發光二極體(OLED)微顯示器。
建構用於諸如虛擬實境(VR)之應用以增強使用者體驗之具有超小像素大小之一顯示器受到越來越多關注。既有頭戴式顯示器(HMD)系統之一常見問題係使用者在長時間使用之後感到不適(歸因於視覺輻輳調節衝突(VAC))。在克服VAC之各種提出解決方案中，最全面的預期為光場顯示器。
在光場方法中，各像素包括多個子像素，其等之各者發射定向光。在任何特定視角處，僅一個(或極少數)子像素促成自該方向所看之影像之感知解析度。因此，一光場顯示器之所需解析度隨真實深度感知所需之方向數目而增加。
為達成適合於一特定像素解析度之定向發射，足夠多之子像素必須納入像素面積以導致需要一非常小子像素面積。在一些應用中，需要小至2 mm×2 mm之一子像素面積。
使用習知矽背板技術，最小子像素面積限於為約4 mm×4 mm (16 mm2 之一面積)。此主要歸因於在像素電路中使用操作OLED所需之＞5V電晶體。另外，在像素單元中用於儲存訊框週期之持續時間內之驅動位準之電容器可佔據高達50%之單元面積。像素電晶體及儲存電容器兩者無法透過縮放來縮小，因為其需要之最小尺寸由支援＞5V操作所需之崩潰電場確定。
如上文所論述，縮小OLED像素電路之一限制因數係建構於一習知平面矽晶片上之組件所需之面積。因此，無法使用既有平面矽晶片製造技術來達成在一側上具有僅數微米之像素之基於OLED之微顯示器。
本發明之一目的係至少解決上述問題及/或缺點且至少提供下文將描述之優點。
限制微顯示器之像素大小縮小之一因數係使用習知平面矽晶片技術來製造其組件之事實。
本發明藉由使用三維(3D)組裝程序而非用於標準矽晶圓製造中之平面處理中所使用之兩個維度建構像素電路來提供繞過此限制之一方式。本發明之三維(3D)像素電路需要比習知像素電路小之實體空間。因此，本發明能夠製造具有比先前微顯示器高之像素密度之基於OLED之微顯示器。
本發明之一實施例係一種垂直堆疊電路，其包括：一下部分，其包括至少一低電壓電晶體；及一上部分，其安置於該下部分上方，包括至少一高電壓電晶體；其中該上部分及該下部分經由一單一電連接件而電連接。
本發明之另一實施例係一種垂直堆疊像素電路，其包括：一下部分，其包括至少一低電壓電晶體；及一上部分，其安置於該下部分上方，包括至少一有機發光二極體(OLED)及經組態以驅動該至少一OLED之像素驅動電路；其中該上部分及該下部分經由一單一電連接件而電連接。
本發明之另一實施例係一種形成一垂直堆疊像素電路之方法，其包括：提供一第一矽基板；使至少低電壓電路及至少一通路形成於該第一矽基板上；提供一第二矽基板；使高電壓電路及至少一通路形成於該第二矽基板上；將該第二矽基板附接於該第一矽基板之頂部上，其中該第二矽基板上之該至少一通路與該第一矽基板上之該至少一通路對準以形成一矽穿通路，且其中該低電壓電路及該高電壓電路經由該矽穿通路而電連接；及在該第二矽基板上製造至少一有機發光二極體。
相關案例之聲明
本申請案主張2018年2月20日申請之美國臨時申請案第62/632,920號之優先權，該案之全部揭示內容以引用的方式併入本文中。
在本發明之系統及方法之各種實施例之以下詳細描述中，闡述諸多特定細節以提供一或多個實施例之各種態樣之一透徹理解。然而，可在無此等特定細節之部分或全部之情況下實踐一或多個實施例。在其他例項中，未詳細描述熟知方法、程序及/或組件以免不必要地使實施例之態樣不清楚。
儘管已揭示較佳實施例，但熟習技術者將自展示及描述說明性實施例之以下詳細描述明白本發明之系統及方法之其他實施例。應意識到，在完全不背離本發明之精神及範疇之情況下，以下揭示內容能夠在各種明顯態樣中修改。此外，參考或未參考本發明之一特定實施例不應被解譯為限制本發明之範疇。
圖1係使用一習知矽製程來形成之不同大小之像素電路100、102及104之示意圖。各像素電路包含5個電晶體及1個電容器106。像素電路100、102及104之實體尺寸分別為15 mm×5 mm、9.6 mm×3.2 mm及8.1 mm×2.7 mm。
主要藉由縮小儲存電容器106之面積來達成像素電路100、102及104之像素面積之漸進縮小。在8.1 mm×2.7 mm像素電路104中，儲存電容器106之大小係用於該大小像素之最小可接受值。使用習知製造技術難以(若非不可能)進一步縮小像素大小。
本發明實現具有包含小至2 mm×2 mm (4 mm2 之一面積)或更小之小子像素面積之像素之一OLED微顯示器。陣列中之各像素包含像素電路及OLED材料之區域，其中像素電路及OLED材料經由一3D矽組裝程序來整合於一基板上。
一3D像素經製造以分割於在一上矽層上用於驅動OLED之一單一高電壓裝置與位於一下矽層上之一低電壓裝置群組及一溝渠電容器之間。此獨特配置允許大高電壓裝置實體定位於下矽層中之較多數目個低電壓裝置之頂部上以達成總像素發射面積之一實質縮小。就此電路組態而言，可使用諸如一DRAM製程之先進矽技術來實施下矽層功能，其亦具有允許一垂直溝渠電容器用於資料儲存以藉此進一步縮小像素面積尺寸之益處。如本文中所使用，術語「高電壓裝置」或「高電壓電晶體」係指經設計以大於約3伏特之電壓操作之一裝置或電晶體，且術語「低電壓裝置」或「高電壓電晶體」係指經設計以約3伏特或更低之電壓操作之一裝置或電晶體。
根據本發明之一說明性實施例，圖2係一垂直堆疊像素電路200之一示意圖且圖3係垂直堆疊像素電路200之一電路圖。
像素電路200包含製造於一上矽層203上之一上部分202及製造於一下矽層205上之一下部分204。上部分202包含一高電壓驅動電晶體206 (適宜為一5伏特驅動電晶體)及一OLED208。組成部分202之裝置較佳製造於一薄化矽晶圓上，該薄化矽晶圓包含在各像素處用於實現至下部分204之電路之一電連接之矽穿通路(TSV) 214。
下部分204係製造於一下矽層205上且包含矩陣定址電路、資料儲存電路及均勻性補償電路之一低電壓像素選擇子電路。資料儲存電路較佳包含適宜為一溝渠電容器之一儲存電容器210。矩陣定址電路較佳包含適宜為一切換電晶體之一選擇開關212。均勻性補償電路較佳包含低電壓電晶體(圖中未展示)，其用於產生至輸入資料之一局部校正信號以確保像素之間的相同亮度效能，不管不同像素之間的驅動電晶體206及/或OLED 208之程序或老化相關變動如何。組成下部分204之所有裝置係以比上部分202低之一電壓(適宜為約1 V)操作且較佳使用一高密度縮放矽程序來製造。
因此，像素電路200分割成上部分202處之一驅動電晶體206 (例如一5伏特電晶體)及下部分204處之一低電壓(例如1伏特)裝置群組，其中僅需要一單一連接點(TSV 214)來電連接各像素之上部分202及下部分204。因為在此設計中下部分204係以一低電壓操作，所以其可易於縮放且可使用常用於DRAM晶片中之一溝渠結構來將下部分204處之儲存電容器210建構於一非常小面積中。像素電路200尤其適合於實施具有包含小至2 mm×2 mm (4 mm2 之一面積)或更小之小子像素面積之像素之一OLED微顯示器，其中各子像素由一各自像素電路200實施。
圖4係展示像素電路200之操作信號值的一曲線圖。「VAnode」表示OLED之陽極側之電壓，「VCathode」表示OLED之陰極側之電壓，「IOLED」表示通過OLED之電流，「VOLED」表示跨OLED之電壓，且「VDrive」表示施加於驅動電晶體206之閘極之電壓。
圖5係根據本發明之一說明性實施例之利用3D像素電路200之一OLED微顯示器之一製造方法之一流程圖。使用矽製程來單獨製造上部分204及下部分202。
關於下部分202，在步驟300中提供一矽晶圓305。在步驟310中，在矽晶圓上製造用於多個下部分202之CMOS裝置及將實現各完成像素電路200中之TSV 214之頂部通路開口。
關於上部分204，在步驟320中提供一矽晶圓325。在步驟330中，在矽晶圓上製造用於多個上部分204之CMOS裝置及將實現各完成像素電路200中之TSV 214之頂部通路開口。在步驟340中，機械拋光矽晶圓以將矽晶圓之厚度減小(薄化矽晶圓)至較佳小於20 mm以實現TSV 214。
在步驟350中，將含有下部分202之矽晶圓及含有上部分204之矽晶圓對準及接合。較佳地，藉由使用一低溫熱壓縮程序接合用於TSV 214中之超細節距銅對銅金屬來接合矽晶圓。本技術中已知之用於3D晶圓接合之特殊原位對準相機可用於晶圓對準。在步驟360中，在上部分204上製造OLED。可藉由使用本技術中已知之用於製造OLED之蒸鍍及沈積技術來製造OLED。接著，在步驟370中，切割組合晶圓以產生多個OLED顯示面板，OLED接著組裝至一顯示封裝中。
上述實施例及優點僅供例示且不應被解釋為限制本發明。本發明之描述意在說明，而非限制申請專利範圍之範疇。熟習技術者將明白諸多替代、修改及變動。可在不背離本發明之精神及範疇之情況下作出各種改變。
100‧‧‧像素電路
102‧‧‧像素電路
104‧‧‧像素電路
106‧‧‧電容器
200‧‧‧垂直堆疊像素電路
202‧‧‧上部分
203‧‧‧上矽層
204‧‧‧下部分
205‧‧‧下矽層
206‧‧‧驅動電晶體
208‧‧‧有機發光二極體(OLED)
210‧‧‧儲存電容器
212‧‧‧選擇開關
214‧‧‧矽穿通路(TSV)
300‧‧‧步驟
305‧‧‧矽晶圓
310‧‧‧步驟
320‧‧‧步驟
325‧‧‧矽晶圓
330‧‧‧步驟
340‧‧‧步驟
350‧‧‧步驟
360‧‧‧步驟
370‧‧‧步驟
將參考以下圖式來詳細描述本發明，在圖式中，相同元件符號係指相同元件，其中：
圖1係使用一習知矽製程來形成之不同大小之像素電路之示意圖；
圖2係根據本發明之一說明性實施例之一垂直堆疊像素電路之一示意圖；
圖3係根據本發明之一說明性實施例之圖2之垂直堆疊像素電路之一電路圖；
圖4係展示根據本發明之一說明性實施例之圖2及圖3之像素電路之操作信號值的一曲線圖；及
圖5係根據本發明之一說明性實施例之利用圖2及圖3之像素電路之一OLED微顯示器之一製造方法之一流程圖。

Claims (26)

  1. 一種垂直堆疊電路，其包括： 一下部分，其包括至少一低電壓電晶體；及 一上部分，其安置於該下部分上方，包括至少一高電壓電晶體； 其中該上部分及該下部分經由一電連接件而電連接。
  2. 如請求項1之電路，其中該高電壓電晶體包括經設計以大於3伏特之一電壓操作之一電晶體。
  3. 如請求項1之電路，其中該下部分及該上部分形成於各自矽層上。
  4. 如請求項3之電路，其中該電連接件包括一矽穿通路。
  5. 如請求項1之電路，其中該上部分進一步包括至少一有機發光二極體(OLED)。
  6. 如請求項1之電路，其中該電路之一長度及寬度小於4 mm×4 mm。
  7. 一種垂直堆疊像素電路，其包括： 一下部分，其包括至少一低電壓電晶體；及 一上部分，其安置於該下部分上方，包括至少一有機發光二極體(OLED)及經組態以驅動該至少一OLED之像素驅動電路； 其中該上部分及該下部分經由一電連接件而電連接。
  8. 如請求項7之像素電路，其中該下部分包括矩陣定址電路、資料儲存電路及均勻性補償電路。
  9. 如請求項7之像素電路，其中該像素驅動電路包括至少一高電壓電晶體。
  10. 如請求項8之像素電路，其中該矩陣定址電路包括一選擇開關且該資料儲存電路包括一儲存電容器。
  11. 如請求項10之像素電路，其中該儲存電容器包括一溝渠電容器。
  12. 如請求項7之像素電路，其中該下部分及該上部分形成於各自矽層上。
  13. 如請求項7之像素電路，其中該電連接件包括一矽穿通路。
  14. 如請求項12之像素電路，其中將含有該下部分之該矽層及含有該上部分之該矽層接合在一起。
  15. 如請求項12之像素電路，其中該像素電路之一長度及寬度小於4 mm×4 mm。
  16. 一種微顯示器，其包括複數個子像素，其中各子像素包括如請求項7之像素驅動電路。
  17. 一種形成一垂直堆疊像素電路之方法，其包括： 提供一第一矽基板； 在該第一矽基板上形成至少低電壓電路及至少一通路； 提供一第二矽基板； 在該第二矽基板上形成高電壓電路及至少一通路； 將該第二矽基板附接於該第一矽基板之頂部上，其中該第二矽基板上之該至少一通路與該第一矽基板上之該至少一通路對準以形成一矽穿通路，且其中該低電壓電路及該高電壓電路經由該矽穿通路而電連接；及 在該第二矽基板上製造至少一有機發光二極體。
  18. 如請求項17之方法，其中該低電壓電路包括矩陣定址電路、資料驅動電路及均勻性補償電路。
  19. 如請求項17之方法，其中該矩陣定址電路包括一選擇開關且該資料儲存電路包括一儲存電容器。
  20. 如請求項19之像素電路，其中該儲存電容器包括一溝渠電容器。
  21. 如請求項17之方法，其中該高電壓電路包括像素驅動電路。
  22. 如請求項21之方法，其中該像素驅動電路包括至少一高電壓電晶體。
  23. 如請求項17之方法，其進一步包括：在將該第二矽基板附接至該第一矽基板之前，薄化該第二矽基板。
  24. 如請求項23之方法，其中該第二矽基板經薄化使得其厚度小於20 mm。
  25. 如請求項17之方法，其進一步包括：使用複數個該垂直堆疊像素電路來製造一微顯示器。
  26. 如請求項17之方法，其中該像素電路之一長度及寬度小於4 mm×4 mm。
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