TW201940759A - Method for producing silicon wafer - Google Patents
Method for producing silicon wafer Download PDFInfo
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- TW201940759A TW201940759A TW108107771A TW108107771A TW201940759A TW 201940759 A TW201940759 A TW 201940759A TW 108107771 A TW108107771 A TW 108107771A TW 108107771 A TW108107771 A TW 108107771A TW 201940759 A TW201940759 A TW 201940759A
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- dry etching
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 37
- 239000010703 silicon Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000005498 polishing Methods 0.000 claims abstract description 121
- 238000001312 dry etching Methods 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 24
- 239000004744 fabric Substances 0.000 claims description 6
- 230000007547 defect Effects 0.000 abstract description 42
- 235000012431 wafers Nutrition 0.000 description 36
- 230000000052 comparative effect Effects 0.000 description 18
- 238000012545 processing Methods 0.000 description 14
- 238000000227 grinding Methods 0.000 description 7
- 239000002245 particle Substances 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 229920003169 water-soluble polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mechanical Engineering (AREA)
- Plasma & Fusion (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Drying Of Semiconductors (AREA)
- Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
Description
本發明係關於一種矽晶圓的製造方法。The invention relates to a method for manufacturing a silicon wafer.
使用矽的半導體裝置隨著其細微化的進展，對於作為基板的矽晶圓，尋求兼顧更細微的表面缺陷的抑制及高程度的平坦度。如第5圖所示，一般而言，矽晶圓係將藉由例如柴氏（CZ）法而提拉的單晶棒予以切片後，進行研光等輪磨之後，進行多段拋光而製作（參考專利文獻1）。With the advancement of miniaturization of semiconductor devices using silicon, for silicon wafers as substrates, it is sought to achieve both finer surface defect suppression and a high degree of flatness. As shown in FIG. 5, in general, a silicon wafer is produced by slicing a single crystal rod that has been pulled by, for example, the CZ method, and then grinding it by grinding, such as lapping, and then polishing it in multiple stages ( Refer to Patent Document 1).
對於表面缺陷的抑制及平坦性而言，晶圓拋光步驟非常地重要。例如，在拋光步驟中會有製造刮痕等的表面缺陷的情況，此缺陷根據拋光條件亦會有具有1μm以上的深度的情況。再者，已知平坦性會根據拋光時的施加於晶圓的壓力分布的不均一性而有所損害。For the suppression of surface defects and flatness, the wafer polishing step is very important. For example, a surface defect such as a scratch may be produced in the polishing step, and the defect may have a depth of 1 μm or more depending on the polishing conditions. Furthermore, it is known that the flatness is impaired by the unevenness of the pressure distribution applied to the wafer during polishing.
一般而言，矽晶圓的拋光係以多段以進行。在此所謂的多段係指使用不同的拋光布及磨粒的粗細度的拋光步驟。一般而言，矽晶圓藉由二段以上的拋光步驟而被加工，隨著段數的進展，使用軟質的拋光布及顆粒細的磨粒。再者，藉由進行多段拋光，使得該拋光步驟所導入的缺陷的深度逐漸變淺。Generally speaking, polishing of a silicon wafer is performed in multiple stages. The so-called multi-stage means a polishing step using different polishing cloths and the thickness of the abrasive particles. In general, silicon wafers are processed by two or more polishing steps. As the number of steps progresses, a soft polishing cloth and fine abrasive particles are used. Furthermore, by performing multiple stages of polishing, the depth of the defects introduced in the polishing step becomes gradually shallower.
在此多段拋光步驟之中，只要沒有滿足「任意的拋光步驟所導入的缺陷的最大深度＜之後的研磨步驟的總加工量」的不等式，任意的拋光步驟所導入的缺陷則會殘留。例如，假定為二段拋光的場合，若第一段所導入的缺陷的最大深度為100nm，第二段的拋光加工量則不得不為100nm以上。假定為三段拋光的場合，若第一段所導入的缺陷的最大深度為100nm，第二段所導入的缺陷的最大深度為10nm，則第二段及第三段的合計加工量必須100nm以上且第三段的合計加工量必須為10nm以上。因此，多段拋光存在有為了防止LLS（Localized light scatters）惡化的加工量的必要條件。In this multi-stage polishing step, as long as the inequality of "the maximum depth of defects introduced by any polishing step <the total processing amount of subsequent grinding steps" is not satisfied, the defects introduced by any polishing step will remain. For example, in the case of two-stage polishing, if the maximum depth of the defect introduced in the first stage is 100 nm, the amount of polishing processing in the second stage must be 100 nm or more. In the case of three-stage polishing, if the maximum depth of the defect introduced in the first stage is 100 nm and the maximum depth of the defect introduced in the second stage is 10 nm, the total processing volume of the second and third stages must be 100 nm or more. And the total processing volume of the third stage must be 10nm or more. Therefore, there is a necessary condition for multi-stage polishing in order to prevent deterioration of LLS (Localized Light Scatters).
另一方面，若以平坦度的觀點考察拋光步驟，則以拋光步驟的段數少者為佳。這是因為，在各拋光步驟中，各自在徑方向的加工量分布之中會出現極大極小點，其與例如SFQR（Sight Front Least Squares Range）的惡化有關連。根據研磨條件，極大極小的位置有所不同，因此拋光步驟愈多則愈會於徑方向出現大量的極大極小點，而損及平坦度。
［先前技術文獻］
［專利文獻］On the other hand, if the polishing step is considered from the viewpoint of flatness, it is preferable that the number of steps in the polishing step is small. This is because, in each polishing step, a local minima point appears in the processing amount distribution in the radial direction, which is related to, for example, deterioration of SFQR (Sight Front Least Squares Range). Depending on the polishing conditions, the maximum and minimum positions are different. Therefore, the more polishing steps, the more the maximum and minimum points appear in the radial direction, which will damage the flatness.
[Previous Technical Literature]
[Patent Literature]
［專利文獻1］日本特開2008-205147號公報[Patent Document 1] Japanese Patent Laid-Open No. 2008-205147
［發明所欲解決之問題］
為了平坦度改善而期望使拋光步驟減少，但是減少拋光步驟會使加工量不足，前拋光步驟中所產生的缺陷即使經過最終拋光步驟也會殘留，而導致表面缺陷（LLS缺陷）增加。[Problems to be solved by the invention]
In order to improve the flatness, it is desirable to reduce the number of polishing steps. However, reducing the number of polishing steps will result in insufficient processing volume. Defects generated in the previous polishing step will remain even after the final polishing step, resulting in increased surface defects (LLS defects).
本發明係為了解決上述問題，目的在於提供一種矽晶圓的製造方法，即使在削減拋光步驟的同時也能抑制表面缺陷的增加並且改善平坦度。
［解決問題之技術手段］In order to solve the above problems, the present invention aims to provide a method for manufacturing a silicon wafer, which can suppress an increase in surface defects and improve flatness even when the polishing step is reduced.
[Technical means to solve problems]
為了達成上述課題，本發明提供一種矽晶圓的製造方法，係於粗拋光步驟與精拋光步驟之間包含乾式蝕刻步驟，其中在該乾式蝕刻步驟之中，以0.3μm/min以下的蝕刻速率將該粗拋光步驟後的矽晶圓予以進行乾式蝕刻。In order to achieve the above-mentioned subject, the present invention provides a method for manufacturing a silicon wafer, which includes a dry etching step between a rough polishing step and a fine polishing step, wherein an etching rate of 0.3 μm / min or less is included in the dry etching step. The silicon wafer after the rough polishing step is dry-etched.
若為如此的矽晶圓的製造方法，即使在削減拋光步驟的同時也能抑制表面缺陷的增加並且改善平坦度。With such a method for manufacturing a silicon wafer, it is possible to suppress an increase in surface defects and improve flatness even when the polishing step is reduced.
再者，此時進行該乾式蝕刻步驟之前的該粗拋光步驟係為雙面拋光步驟為佳。Furthermore, the rough polishing step before the dry etching step is preferably a double-side polishing step.
再者，進行該乾式蝕刻步驟之後的該精拋光步驟係為單面拋光步驟為佳。Furthermore, the fine polishing step after the dry etching step is preferably a single-sided polishing step.
進一步，在該粗拋光步驟之中，使用較在該精拋光步驟中所使用的研磨布為更高硬度的研磨布為佳。Further, in the rough polishing step, it is preferable to use an abrasive cloth having a higher hardness than the abrasive cloth used in the fine polishing step.
以如同上述的條件製造矽晶圓，能夠更抑制表面缺陷的增加並且改善平坦度。
［對照先前技術之功效］By manufacturing a silicon wafer under the conditions described above, it is possible to further suppress the increase in surface defects and improve the flatness.
[Contrast with the effect of the prior art]
如同以上，若為本發明的矽晶圓的製造方法，即使在削減拋光步驟的同時也能抑制表面缺陷的增加並且改善平坦度。As described above, according to the method for manufacturing a silicon wafer of the present invention, it is possible to suppress an increase in surface defects and improve flatness even when the polishing step is reduced.
如同上述，尋求即使在削減拋光步驟的同時亦能夠抑制表面缺陷的增加並且改善平坦度的矽晶圓的製造方法的開發。As described above, the development of a method for manufacturing a silicon wafer capable of suppressing the increase in surface defects and improving the flatness even while reducing the number of polishing steps has been sought.
為了不讓表面缺陷增加而削減拋光步驟，必須不進行拋光並且將在前一步驟中產生的缺陷除去。於是本發明人等著眼於：在矽晶圓的多段拋光之中，將第一段的粗拋光步驟及最終精拋光步驟以外的任意的拋光步驟予以替換成蝕刻，特別是乾式蝕刻。In order to reduce the polishing step without increasing surface defects, it is necessary to not perform polishing and remove the defects generated in the previous step. Therefore, the present inventors have focused on replacing any rough polishing step other than the final fine polishing step with an etching, especially a dry etching, in the multi-stage polishing of a silicon wafer.
然而，乾式蝕刻的速率一旦過快則對表面的電漿損傷會增加，離子損傷會被導入至深處，再者，微粗糙會惡化等，導致後續必須大量的拋光加工量。於是，本發明人等反覆努力研究的結果，發現了若為規定的蝕刻速率的範圍，即使削減拋光步驟也能抑制表面缺陷的增加並且改善粗糙度，進而完成了本發明。However, if the rate of dry etching is too fast, plasma damage to the surface will increase, ionic damage will be introduced into the depth, and further, micro-roughness will deteriorate, resulting in a large amount of subsequent polishing processing. As a result, the present inventors have worked hard to find out that if the etching rate is within a predetermined range, it is possible to suppress the increase in surface defects and improve the roughness even if the polishing step is reduced, thereby completing the present invention.
亦即，本發明為一種矽晶圓的製造方法，係於粗拋光步驟與精拋光步驟之間包含乾式蝕刻步驟，其中在該乾式蝕刻步驟之中，以0.3μm/min以下的蝕刻速率將該粗拋光步驟後的矽晶圓予以進行乾式蝕刻。That is, the present invention is a method for manufacturing a silicon wafer, which includes a dry etching step between the rough polishing step and the fine polishing step. In the dry etching step, the dry etching step is performed at an etching rate of 0.3 μm / min or less. The silicon wafer after the rough polishing step is dry-etched.
以下針對本發明詳細地說明，但是本發明並非限定於這些。The present invention is described in detail below, but the present invention is not limited to these.
［矽晶圓的製造方法］
關於本發明矽晶圓的製造方法，參考圖式而說明。第1圖係表示本發明的矽晶圓的製造方法的一範例的流程圖。
將藉由例如柴氏（CZ）法而提拉的單晶棒予以切片後，進行研光、輪磨，之後經過以下所說明的粗拋光步驟、乾式蝕刻步驟及精拋光步驟而製造矽晶圓。結晶提拉步驟、切片步驟、研光及輪磨步驟沒有特別限定，能夠使用過往習知的方法。[Manufacturing method of silicon wafer]
A method for manufacturing the silicon wafer of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing an example of a method for manufacturing a silicon wafer according to the present invention.
A single crystal rod pulled by, for example, the CZ method is sliced, polished, and ground, and then subjected to the rough polishing step, dry etching step, and fine polishing step described below to produce a silicon wafer. . The crystal pulling step, the slicing step, the polishing, and the wheel grinding step are not particularly limited, and a conventionally known method can be used.
＜粗拋光步驟＞
由於乾式蝕刻沒有粗糙度的改善能力，在本發明之中，在乾式蝕刻步驟之前設置粗拋光步驟以改善特別是長波長的粗糙度。＜ Rough polishing step ＞
Since dry etching does not have the ability to improve roughness, in the present invention, a rough polishing step is provided before the dry etching step to improve the roughness, especially at long wavelengths.
對輪磨步驟後的晶圓，進行為了將表背面予以鏡面化的粗拋光步驟。表背面的鏡面化可進行一次至數次雙面拋光，亦可進行表背一次至數次單面拋光。自生產性的觀點來看，進行雙面拋光（雙面同時拋光）為佳。若不進行此拋光，則長波長的粗糙度會惡化。The wafer after the wheel grinding step is subjected to a rough polishing step for mirror-finishing the front and back surfaces. The mirror surface of the back surface can be polished once or several times on both sides, and the back surface can also be polished once or several times on one side. From the viewpoint of productivity, it is preferable to perform double-side polishing (simultaneous polishing on both sides). If this polishing is not performed, the long-wavelength roughness will be deteriorated.
此粗拋光步驟及以下所說明的精拋光步驟，能夠依照使用樹脂襯墊及含有磨粒的研磨漿的習知的拋光方法以進行，拋光劑能夠為含有作為磨粒的矽酸膠及鹼之物。This rough polishing step and the fine polishing step described below can be performed in accordance with a conventional polishing method using a resin pad and an abrasive slurry containing abrasive particles, and the polishing agent can be a material containing silicic acid gum and alkali as abrasive particles. Thing.
＜乾式蝕刻步驟＞
接著，為了不使粗糙度惡化並且除去在雙面拋光步驟（粗拋光步驟）中產生的缺陷，將粗拋光步驟後的晶圓洗淨及乾燥，之後進行乾式蝕刻。洗淨及乾燥的方法沒有特別限定，以過往習知的方法進行即可。＜ Dry etching step ＞
Next, in order not to deteriorate the roughness and remove defects generated in the double-side polishing step (rough polishing step), the wafer after the rough polishing step is washed and dried, and then dry etching is performed. The method of washing and drying is not particularly limited, and it may be performed by a conventionally known method.
蝕刻有使用酸及鹼的濕式蝕刻與使用電漿氣體的乾式蝕刻兩種，但是濕式蝕刻的選擇性大，會使缺陷巨大化。另一方面，乾式蝕刻的等向性強，因而適合不使缺陷變大且平均地除去表面，故在本發明之中使用乾式蝕刻。There are two types of etching: wet etching using acid and alkali, and dry etching using plasma gas. However, the selectivity of wet etching is large, and defects may be enlarged. On the other hand, dry etching is highly isotropic, so it is suitable to remove the surface evenly without making the defects large. Therefore, dry etching is used in the present invention.
本來應以二次拋光（第二段的粗拋光）除去的加工量藉由乾式蝕刻除去，藉此能夠做到在該前步驟（粗拋光步驟）中產生的缺陷的除去。乾式蝕刻為沒有磨粒及襯墊的對晶圓表面的接觸的加工方法，因而原理上不會產生超過100nm的深度缺陷。The amount of processing that should have been removed by the secondary polishing (rough polishing in the second stage) was removed by dry etching, so that defects generated in the previous step (rough polishing step) could be removed. Dry etching is a processing method for contacting the wafer surface without abrasive grains and pads. Therefore, in principle, no depth defects exceeding 100 nm are generated.
乾式蝕刻的加工量係根據雙面拋光步驟（粗拋光步驟）的條件所致的缺陷深度，以0.5μm以上的除去即為充分。乾式蝕刻係使用電漿氣體而僅於晶圓的表面進行。自平坦度的觀點來看，不是僅於晶圓表面的部分的區域供給電漿，而是於晶圓全表面供給電漿並且平均地供給為佳。乾式蝕刻的方法沒有特別限定，例如能夠將O2 氣體、CF4 氣體分別以100、500 sccm的流量進行供給。再者，乾式蝕刻中的艙室壓力能夠為40 Pa，輸出能夠為500 W，能夠以常溫進行。另外，本發明之中的「常溫」係指在通常的狀態下的周圍溫度，通常為15~30℃的範圍的溫度，典型而言為25℃。The processing amount of the dry etching is based on the depth of the defect caused by the conditions of the double-side polishing step (rough polishing step), and it is sufficient to remove it by 0.5 μm or more. Dry etching is performed only on the surface of the wafer using plasma gas. From the viewpoint of flatness, it is not preferable to supply the plasma only to a part of the surface of the wafer, but to supply the plasma to the entire surface of the wafer and supply it evenly. The method of dry etching is not particularly limited, and for example, O 2 gas and CF 4 gas can be supplied at a flow rate of 100 and 500 sccm, respectively. In addition, the chamber pressure during dry etching can be 40 Pa, the output can be 500 W, and it can be performed at normal temperature. The "normal temperature" in the present invention means the ambient temperature in a normal state, and is usually a temperature in the range of 15 to 30 ° C, and typically 25 ° C.
本發明的矽晶圓的製造方法的乾式蝕刻步驟之中，蝕刻速率必須為0.3μm/min以下。蝕刻速率高於0.3μm/min的場合，對晶圓表面的電漿損傷會增加，離子損傷會被導入至深處，再者，微粗糙會惡化等，導致後續必須大量的拋光加工量。另一方面，蝕刻速率以0.1μm/min以上為佳。若在此範圍，能夠效率佳地進行矽晶圓的蝕刻。In the dry etching step of the method for manufacturing a silicon wafer of the present invention, the etching rate must be 0.3 μm / min or less. When the etching rate is higher than 0.3 μm / min, plasma damage to the wafer surface will increase, ion damage will be introduced to the deep, and micro-roughness will worsen, resulting in a large amount of subsequent polishing processing. On the other hand, the etching rate is preferably at least 0.1 μm / min. Within this range, etching of a silicon wafer can be performed efficiently.
＜精拋光步驟＞
乾式蝕刻沒有除去微粗糙的能力，再者雖然不像拋光般但是會於表面製造淺度缺陷（微小缺陷）。因此，最後，為了除去微粗糙及微小缺陷，而進行再次拋光（精拋光）。精拋光步驟能夠為單面拋光步驟。此精拋光步驟中使用硬度較乾式蝕刻前的拋光步驟為柔軟的樹脂襯墊及磨粒以進行為佳。在此，本發明之中的「硬度」係指邵氏A硬度。＜ Fine polishing step ＞
Dry etching does not have the ability to remove micro-roughness. Moreover, although it is not like polishing, it will create shallow defects (micro defects) on the surface. Therefore, finally, in order to remove micro-roughness and minute defects, re-polishing (fine polishing) is performed. The fine polishing step can be a single-sided polishing step. In this fine polishing step, it is better to use a softer resin pad and abrasive particles for the polishing step before the dry etching. Here, the "hardness" in the present invention means a Shore A hardness.
若為如同上述的本發明的矽晶圓的製造方法，即使削減拋光步驟也能夠抑制LLS缺陷的增加並且達成平坦度的改善。According to the method for manufacturing a silicon wafer of the present invention as described above, even if the polishing step is reduced, the increase in LLS defects can be suppressed and the flatness can be improved.
［實施例］
以下利用實施例及比較例而具體地說明本發明，但是本發明並非限定於這些。[Example]
Hereinafter, the present invention will be specifically described using examples and comparative examples, but the present invention is not limited to these.
［實施例一至三、比較例一至四］
如第2圖所示，假定為對輪磨步驟後的晶圓（直徑：300mm）進行三段的拋光步驟（二段粗拋光步驟及一段精拋光步驟）的流程（比較例一），並且對將其第二段的粗拋光步驟予以替換成乾式蝕刻步驟的效果進行了驗證。[Examples 1-3, Comparative Examples 1-4]
As shown in FIG. 2, it is assumed that the wafer (diameter: 300 mm) after the wheel grinding step is subjected to a three-stage polishing step (two rough polishing steps and one fine polishing step) (Comparative Example 1), and The effect of replacing the second rough polishing step with a dry etching step was verified.
拋光加工量依序為5μm、1μm、10nm。單純地將沒有進行第二段的粗拋光步驟的流程定為比較例二，將替換第二段的粗拋光步驟而導入乾式蝕刻並且除去1μm的流程定為比較例三、四及實施例一至三。如下列表1所示，比較例三、四及實施例一至三的蝕刻速率並不相同。另外，實施例及比較例的粗拋光步驟皆以雙面拋光進行，精拋光步驟皆以單面拋光進行。The polishing processing amounts were sequentially 5 μm, 1 μm, and 10 nm. The flow of the rough polishing step without performing the second stage is simply referred to as Comparative Example 2. The flow of introducing dry etching and removing 1 μm in place of the rough polishing step of the second stage is referred to as Comparative Examples 3 and 4, and Examples 1 to 3. . As shown in Table 1 below, Comparative Examples 3 and 4 and Examples 1 to 3 have different etching rates. In addition, the rough polishing steps of the examples and comparative examples are performed by double-sided polishing, and the fine polishing steps are performed by single-sided polishing.
再者，各拋光步驟之中，研磨布係使用樹脂襯墊，研磨漿係使用於矽酸膠添加氨及水溶性高分子聚合物之物，而定盤及研磨頭的轉速為30 rpm。Furthermore, in each polishing step, the polishing cloth is made of resin pads, and the polishing slurry is used for the addition of ammonia and water-soluble polymer to the silica gel, and the rotation speed of the fixed plate and the grinding head is 30 rpm.
蝕刻速度以外的乾式蝕刻條件如下列所示。
艙室壓力 40Pa
艙室溫度 常温
輸出 500W
O2
氣體流量 100sccm
CF4
氣體流量 500sccmThe dry etching conditions other than the etching rate are shown below.
Cabin pressure 40Pa
Cabin temperature normal temperature output 500W
O 2 gas flow 100sccm
CF 4 gas flow 500sccm
【表1】
進行了精拋光步驟後的各矽晶圓的平坦性及缺陷評估。作為平坦性的評估，藉由使用KLA Tencor公司製的WaferSight而測定SFQR的最大值的SFQRmax以進行，作為缺陷評估，藉由使用KLA Tencor公司製的SP3而測定LLS缺陷的個數以進行。
再者，比較例一的粗拋光步驟二及實施例一的乾式蝕刻步驟之中的加工量形狀，使用KLA Tencor公司製的WaferSight測定而評估。The flatness and defect evaluation of each silicon wafer after the fine polishing step were performed. As the evaluation of flatness, SFQRmax of the maximum value of SFQR was measured by using WaferSight made by KLA Tencor, and as the defect evaluation, the number of LLS defects was measured by using SP3 made by KLA Tencor.
In addition, the shape of the processing amount in the rough polishing step 2 of Comparative Example 1 and the dry etching step of Example 1 was evaluated using WaferSight measurement made by KLA Tencor.
實施例一至三及比較例一至四的SFQRmax及LLS缺陷數的結果表示於第3圖。另外，SFQRmax及LLS缺陷數，係將一般方法的比較例一定為100而相對表示。比較例二中，SFQRmax改善。這被認為是由於粗拋光步驟二之中惡化量消除的緣故。另一方面，與比較例一相比，LLS缺陷大幅度惡化。這被認為是在粗拋光步驟一中造成的缺陷無法僅以精拋光步驟三的加工量除去的原因。在比較例三、四之中，儘管有使用乾式蝕刻而進行充分的蝕刻，LLS缺陷依然增加。這被認為是蝕刻速率高所導致的電漿損傷的原因。另一方面，在蝕刻速率壓制在0.3μm/min以下的實施例一至三之中，未見LLS缺陷的增加，並且由於削減拋光步驟的緣故，SFQRmax亦為良好。The results of SFQRmax and the number of LLS defects in Examples 1 to 3 and Comparative Examples 1 to 4 are shown in FIG. 3. In addition, the SFQRmax and the number of LLS defects are relatively expressed by comparing a comparative example of a general method to 100. In Comparative Example 2, SFQRmax improved. This is considered to be due to the elimination of the deterioration amount in the rough polishing step 2. On the other hand, compared with Comparative Example 1, the LLS defect was significantly worsened. This is considered to be the reason why the defects caused in the rough polishing step 1 cannot be removed by the processing amount of the fine polishing step 3 alone. In Comparative Examples 3 and 4, LLS defects increased even though sufficient etching was performed using dry etching. This is considered to be the cause of plasma damage caused by a high etching rate. On the other hand, in Examples 1 to 3 in which the etching rate was suppressed to 0.3 μm / min or less, no increase in LLS defects was observed, and SFQRmax was also good because the polishing step was reduced.
再者，如第4圖所示，比較例一的粗拋光步驟二之中的加工形狀不穩定，在此步驟之中平坦性受到損失，相對於此，實施例一的乾式蝕刻步驟之中，加工形狀為平坦，表示了平坦性的惡化停留在最小限度。In addition, as shown in FIG. 4, the machining shape in the rough polishing step 2 of the comparative example 1 is unstable, and the flatness is lost in this step. In contrast, in the dry etching step of the first embodiment, The processed shape is flat, indicating that deterioration in flatness is kept to a minimum.
此外，本發明並不限定於上述的實施例。上述實施例為舉例說明，凡具有與本發明的申請專利範圍所記載之技術思想實質上同樣之構成，產生相同的功效者，不論為何物皆包含在本發明的技術範圍內。The present invention is not limited to the embodiments described above. The above embodiment is an example, and anyone who has substantially the same structure as the technical idea described in the patent application scope of the present invention and produces the same effect is included in the technical scope of the present invention no matter what.
無no
［第1圖］係表示本發明的矽晶圓的製造方法的一範例的流程圖。[FIG. 1] A flowchart showing an example of a method for manufacturing a silicon wafer of the present invention.
［第2圖］係用於說明實施例及比較例的流程圖。 [Fig. 2] A flowchart for explaining examples and comparative examples.
［第3圖］係比較實施例及比較例的矽晶圓的平坦性及表面缺陷的圖。 [Fig. 3] It is a figure showing the flatness and surface defects of the silicon wafers of the comparative examples and comparative examples.
［第4圖］係表示比較例一的粗拋光步驟二及實施例一的乾式蝕刻步驟之中的加工量形狀的圖。 [Fig. 4] Fig. 4 is a diagram showing a shape of a processing amount in the rough polishing step 2 of the comparative example 1 and the dry etching step of the first embodiment.
［第5圖］係表示過往的矽晶圓的製造方法的一範例的流程圖。 [FIG. 5] A flowchart showing an example of a conventional method for manufacturing a silicon wafer.
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