TW201933961A - Circuit board structure and manufacturing method thereof - Google Patents

Abstract

A circuit board structure including an insulating layer, a first circuit layer, a second circuit layer, a conductive via, a capacitor dielectric layer, a dielectric layer and a redistribution layer is provided. The first circuit layer includes a first capacitor electrode. The capacitor dielectric layer is disposed on the first capacitor electrode. The dielectric layer covers the first circuit layer and the capacitor dielectric layer. The redistribution layer includes a redistribution circuit disposed on the dielectric layer, a first conductive blind via disposed in the dielectric layer and connected to the first circuit layer, and a second capacitor electrode disposed in the dielectric layer. Two ends of the second capacitor electrode are respectively in contact with the capacitor dielectric layer and the redistribution circuit. The second capacitor electrode, the capacitor dielectric layer and the first capacitor electrode form a capacitor. A method of manufacturing a circuit board structure has been proposed.

Description

Circuit board structure and manufacturing method thereof

The present invention relates to a circuit board structure and a method of fabricating the same, and more particularly to a circuit board structure having a capacitor and a method of fabricating the same.

As the demand for electronic products is toward higher functionality, higher signal transmission speed, and higher density of circuit components, the more powerful the functions of integrated circuit chips, the more the number of passive components used for consumer electronics. . Moreover, when electronic products emphasize lightness and shortness, how to accommodate a large number of electronic components in a limited configuration space has become a technical bottleneck that electronic assembly operators urgently need to solve and overcome. In order to solve this problem, the packaging technology is gradually moving toward the system integration phase of the System in Package (SIP), especially the multi-Chip Module (MCM) package. Among them, embedded active components and embedded technology become key technologies. By embedding the components, the package volume can be greatly reduced, and more high-functional components can be placed to increase the layout area of the substrate surface, thereby achieving the purpose of thinning the electronic product.

Commonly used buried passive capacitive components are Metal-Insulator-Metal Capacitor (MIM Capacitor) and Metal-Oxide-Metal Capacitor (MOM Capacitor), commonly known as For sandwich capacitors. However, in the fabrication of the aforementioned buried passive capacitive element, the two metal electrodes constituting the capacitor and the insulator/oxidant located between the two metal electrodes are defined by at least three masks having a specific pattern. As such, it is complicated to manufacture and requires a lot of cost, and may result in a decrease in yield. Therefore, in the fabrication of a circuit board structure with embedded passive components, how to simplify the manufacturing process and improve the production efficiency and yield, and further reduce the volume of the circuit board structure, and reduce the manufacturing cost, which has become the current The problem that I want to solve.

The invention provides a circuit board structure and a manufacturing method thereof, which can reduce the overall thickness of the package structure and can improve the production efficiency and the yield, and can reduce the manufacturing cost.

The invention provides a circuit board structure comprising an insulating layer, a first circuit layer, a second circuit layer, a conductive via, a capacitor dielectric layer, a dielectric layer and a redistribution circuit layer. The insulating layer has a first surface and a second surface opposite the first surface. The first circuit layer is on the first surface of the insulating layer. The first circuit layer includes a first capacitor electrode. The second circuit layer is on the second surface of the insulating layer. The conductive via penetrates through the insulating layer to electrically connect the first wiring layer and the second wiring layer. The capacitor dielectric layer is on the first capacitor electrode of the first circuit layer. The dielectric layer covers at least a portion of the first circuit layer and a portion of the capacitive dielectric layer. The redistribution circuit layer includes a redistribution circuit, a first conductive blind via, and a second capacitor electrode. The redistribution line is on the dielectric layer. The first conductive blind via is located within the dielectric layer and connects the first circuit layer to the redistribution line. The second capacitor electrode is located within the dielectric layer. The second capacitor electrode has opposite first and second ends, the first end is in contact with the capacitor dielectric layer, and the second end is in contact with the redistribution line. The second capacitor electrode, the capacitor dielectric layer and a portion of the first circuit layer form a capacitor.

In an embodiment of the invention, the first projection of the first end on the first surface is smaller than the orthographic projection of the second end on the first surface.

In an embodiment of the invention, the total contract of the thickness of the second capacitor electrode and the thickness of the capacitor dielectric layer is slightly equal to the thickness of the first conductive via.

In an embodiment of the invention, the second capacitor electrode has a sidewall connected to the first end and the second end, and the sidewall is a slope.

In an embodiment of the invention, the circuit board structure further includes a plurality of second conductive vias and a plurality of third conductive vias. The second conductive via and the third conductive via are located in the insulating layer, and a portion of the first circuit layer, a portion of the second circuit layer, the second conductive vias and the third conductive vias are formed in a spiral form through the insulating layer A three-dimensional inductor.

In an embodiment of the invention, the circuit board structure further includes a plurality of conductive terminals. The conductive terminal is disposed on the redistribution circuit layer and electrically connected to the redistribution circuit layer.

The manufacturing method of the circuit board structure of the present invention comprises the following steps. Provide an insulation layer. The insulating layer has a first surface and a second surface opposite the first surface. Forming a first circuit layer, a second circuit layer and at least one conductive via. The first circuit layer is on the first surface of the insulating layer, and the first circuit layer includes a first capacitor electrode. The second circuit layer is on the second surface of the insulating layer. The conductive via penetrates through the insulating layer to electrically connect the first wiring layer and the second wiring layer. A capacitor dielectric layer is formed on the first circuit layer to cover a portion of the first circuit layer. A dielectric layer is formed on the first circuit layer and the capacitor dielectric layer. The dielectric layer has a first opening and a second opening, wherein the first opening exposes a portion of the first wiring layer, and the second opening exposes a portion of the capacitive dielectric layer. A redistribution circuit layer is formed on the first circuit layer. The redistribution circuit layer includes a redistribution circuit, a first conductive blind via, and a second capacitor electrode. The redistribution line is on a dielectric surface of the dielectric layer. The first conductive blind hole is located in the first opening and connects the first circuit layer and the redistribution line. The second capacitor electrode is located in the second opening and is in contact with the capacitor dielectric layer. The second capacitor electrode, the capacitor dielectric layer and the first capacitor electrode form a capacitor.

In an embodiment of the invention, the first conductive via hole and the second capacitor electrode are simultaneously formed by the same process.

In an embodiment of the invention, forming the repeating wiring layer described above includes the following steps. Forming a patterned photoresist layer on the dielectric layer and the first circuit layer to expose the first opening and the second opening. A conductive material is formed on the dielectric layer and the first circuit layer. The conductive material is filled in the first opening, the second opening, and the patterned photoresist layer, wherein a portion of the conductive material filled in the first opening constitutes a first conductive blind via, and a portion of the conductive material filled in the second opening constitutes a second capacitor electrode. The patterned photoresist layer is removed to form a redistribution line.

In an embodiment of the invention, forming the repeating wiring layer described above includes the following steps. A conductive material is formed on the dielectric layer and the first circuit layer. The conductive material covers the dielectric surface of the dielectric layer and fills the first opening and the second opening, wherein a portion of the conductive material filled in the first opening constitutes a first conductive blind via, and a portion of the conductive material filled in the second opening constitutes a first Two capacitor electrodes. A portion of the conductive material overlying the dielectric surface of the dielectric layer is removed to form a redistribution line.

In an embodiment of the invention, the method for fabricating the circuit board structure further includes the following steps. A plurality of conductive terminals are disposed on the redistribution circuit layer. The conductive terminal is electrically connected to the redistribution circuit layer.

Based on the above, the present invention forms part of the first circuit layer and the second capacitor electrode on the redistribution circuit layer to form two electrodes of the buried capacitor. In this way, in the manufacturing process of the circuit board structure with the buried capacitor, the manufacturing process can be simplified, the manufacturing efficiency and the yield can be improved, and the manufacturing cost of the circuit board structure can be reduced. Moreover, the capacitance of the capacitor can be further adjusted by adjusting the overlapping area of the second capacitor electrode and the first wiring layer. Therefore, in the process of manufacturing the capacitor, it also has a large process desire.

The above described features and advantages of the invention will be apparent from the following description.

The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the embodiments of the invention. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only directions referring to the additional schema. Therefore, the directional terminology used is for the purpose of illustration and not limitation. Also, in the following embodiments, the same or similar elements will be given the same or similar reference numerals.

1A through 1G are schematic cross-sectional views showing a manufacturing process of a circuit board structure in accordance with an embodiment of the present invention. Fig. 1H is an enlarged view of a region R in Fig. 1G. Figure 1I is a top plan view of the region R of Figure 1G. For the sake of clarity, in FIG. 1I, a portion of the mold layer or member is omitted.

The manufacturing method of the circuit board structure 100 of this embodiment includes the following steps. First, referring to FIG. 1A, an insulating layer 111 is provided, wherein the insulating layer 111 includes a through hole 111c, a first surface 111a, and a second surface 111b, and the first surface 111a and the second surface 111b are opposed to each other. The through hole 111c penetrates through the insulating layer 111 to communicate the first surface 111a and the second surface 111b. In this embodiment, the through hole 111c penetrating the insulating layer 111 can be formed, for example, by mechanical drilling or laser drilling. Of course, the embodiment is merely for illustration, and the present invention does not limit the manner in which the through hole 111c is formed.

In this embodiment, the insulating layer 111 may include a core layer, and the core layer may include a polymer glass fiber composite substrate, a glass substrate, a ceramic substrate, or a polyimide (PI) glass fiber composite substrate, but the present invention Not limited to this. In other embodiments, the insulating layer 111 may be a dielectric layer having a single layer or a plurality of dielectric materials, or a single layer or a multilayer wiring board having an outer layer and a buried material.

Next, referring to FIG. 1B, a first wiring layer 112 may be formed on the first surface 111a of the insulating layer 111, and a second wiring layer 113 may be formed on the second surface 111b of the insulating layer 111. Specifically, the manufacturing method of the first circuit layer 112 and the second circuit layer 113 may include, for example, the following steps. The conductive material may be formed on the first surface 111a and the second surface 111b of the insulating layer 111 by other suitable processes such as a deposition process and/or an electroplating process. Further, the conductive material may be further filled in the through hole 111c of the insulating layer 111 and covered with the side wall of the through hole 111c to form a conductive through hole 114 having a conductive property. Subsequently, the conductive material covering the first surface 111a and the second surface 111b of the insulating layer 111 may be patterned by, for example, a lithography and etching process to form the first wiring layer 112 and the second wiring layer 113, respectively. . In the present embodiment, the conductive material covers only the side walls of the through hole 111c to constitute the hollow conductive via hole 114, but the present invention is not limited thereto. In other embodiments, the conductive material may fill the through hole 111c to form a solid conductive via 114.

In the embodiment illustrated in FIG. 1B, the number of conductive vias 114 is exemplified by one, but the invention is not limited thereto.

Next, referring to FIG. 1B, after the first wiring layer 112 is formed, the capacitor dielectric layer 120 may be formed on the first wiring layer 112, and the capacitor dielectric layer 120 covers a portion of the first wiring layer 112. The material of the capacitor dielectric layer 120 may include aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon oxide (SiO ₂ ), tantalum nitride (Si _{3 ).} N ₄ ) hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), lanthanum oxide (La ₂ O ₃ ), other similar metal oxide materials, metal nitride materials or other suitable High-k material.

Next, referring to FIG. 1C, after forming the capacitor dielectric layer 120, a dielectric layer 130 is formed. The material of the dielectric layer 130 may include an organic material, a photosensitive dielectric material, a resin sheet (Prepreg), an inorganic material (for example: cerium oxide, cerium nitride, cerium oxynitride, other suitable materials, or at least two materials described above). Stacked layers), or other suitable dielectric materials. Taking the organic dielectric material as an example, the first surface 111a and the second surface of the insulating layer 111 may be applied by a coating method, a viscosity method, a Sol-Gel method or a pressing method or other suitable processes. An organic dielectric material is formed on 111b, and then cured by a photopolymerization or baking process depending on the properties of the organic dielectric material to form the dielectric layer 130. Taking an inorganic dielectric material as an example, an inorganic dielectric material may be formed on the first surface 111a and the second surface 111b of the insulating layer 111 by a deposition process or other suitable process, and the formed dielectric layer 130 may be covered. The first circuit layer 112, the capacitor dielectric layer 120, and the second circuit layer 113.

In this embodiment, the dielectric constant of the capacitor dielectric layer 120 can be greater than the dielectric constant of the dielectric layer 130 to form a capacitor 10 composed of the capacitor dielectric layer 120 having the above material (shown in FIG. 1G). There is a preferred capacity, but the invention is not limited thereto.

Next, referring to FIG. 1D, a plurality of openings 131, 132 are formed from the dielectric surface 130a of the dielectric layer 130. Taking the dielectric layer 130 formed of an organic material as an example, the openings 131, 132 may be formed by lithography, etching, drilling, or other suitable processes. In another embodiment, the dielectric layer 130 formed of a photosensitive dielectric material is exemplified, and the openings 131, 132 may be formed by a lithography process of exposure and development. In another embodiment, the dielectric layer 130 formed of an inorganic material is taken as an example, and the opening can be formed by a lithography and etching process. As such, the sidewalls of the openings 131, 132 may be substantially non-concave contoured surfaces. As shown in FIG. 1D, in the present embodiment, the sidewalls of the openings 131, 132 may be a slope on a section perpendicular to the first surface 111a, but the invention is not limited thereto.

In the embodiment, the opening may include the first opening 131 and the second opening 132. The first opening 131 extends from the dielectric surface 130a of the dielectric layer 130 toward the first wiring layer 112 to expose a portion of the first wiring layer 112. The second opening 132 extends from the dielectric surface 130a of the dielectric layer 130 toward the capacitive dielectric layer 120 to expose a portion of the capacitive dielectric layer 120. In this embodiment, the first opening 131 and the second opening 132 may be formed by a similar process. Taking the first opening 131 and the second opening 132 formed by the etching process as an example, the first opening 131 is the first circuit layer 112 as an etching stop layer, and the second opening 132 is a capacitor The electrical layer 120 acts as an etch stop layer. In this way, the production process can be simplified and the production efficiency and yield can be improved. In FIG. 1D, the number of the first openings 131 and/or the second openings 132 is exemplified, but the invention is not limited thereto.

Next, referring to FIG. 1E, the first conductive layer 141 can be selectively formed on the dielectric surface 130a of the dielectric layer 130 and in the openings 131, 132. In other words, the first conductive layer 141 is conformal with the dielectric layer 130. In this embodiment, the first conductive layer 141 is, for example, a seed layer formed by sputtering, and the common seed layer has a titanium layer and/or a copper layer, or a chemical formed by, for example, electroless plating. Copper layer. However, the actual material of the seed layer depends on the conductive material that will be subsequently filled into the first opening 131 and the second opening 132.

Next, referring to FIG. 1F, a redistribution wiring layer 150 is formed on the first wiring layer 112, and the redistribution wiring layer 150 may include a redistribution wiring 151, a first conductive blind via hole 152, and a second capacitor. Electrode 153. Specifically, the method of fabricating the redistribution wiring layer 150 may, for example, use a semi-additive method, including the following steps. First, a patterned photoresist layer (not shown) may be formed on the first conductive layer 141 by a lithography process, and the patterned photoresist layer exposes a portion of the first conductive layer 141, and the patterned photoresist layer does not overlap. An opening 131 and a second opening 132 expose the first opening 131 and the second opening 132. Then, for example, a patterned second conductive layer 142 formed of a conductive material may be formed on the first conductive layer 141 exposed by the patterned photoresist layer by electroplating. The second conductive layer 142 covers at least a portion of the first conductive layer 141 exposed by the patterned photoresist layer, and the second conductive layer 142 is further filled into the first opening 131 (shown in FIG. 1E ) and the second opening 132 (shown In FIG. 1E), the first conductive via 152 and the second capacitor electrode 153 are respectively formed to cover the first conductive layer 141 in the first opening 131 and the second opening 132. Then, the photoresist layer may be removed by plasma ashing or etching, and the second conductive layer 142 is used as the mask removing portion of the first portion not covered by the second conductive layer 142. The conductive layer 141 forms a redistribution line 151 on the second wiring layer 113.

In other embodiments, the redistribution wiring layer may also be formed on the second wiring layer 113 by a method similar to that described above (such as deposition, lithography, and etching processes of the subtractive method).

Specifically, the method of fabricating the redistribution wiring layer 150 may also include the following steps, for example. First, a second conductive layer 142 formed of a conductive material may be entirely formed on the first conductive layer 141 by electroplating. The second conductive layer 142 covers at least the first conductive layer 141, and the second conductive layer 142 is further filled into the first opening 131 (shown in FIG. 1E) and the second opening 132 (shown in FIG. 1E) to cover the first An opening 131 and a first conductive layer 141 in the second opening 132 to form a first conductive via 152 and a second capacitor electrode 153, respectively. Then, a patterned photoresist layer (not shown) may be formed on the second conductive layer 142 to remove the exposed conductive material by an etching process or the like, that is, a portion of the second conductive layer 142 is removed to form a redistributed line. 151. Finally, the patterned photoresist layer is removed by plasma ashing or etching. Also, the second conductive layer 142 is used as a mask to remove a portion of the first conductive layer 141 that is not covered by the second conductive layer 142.

In terms of structure, the first conductive layer 141 and the second conductive layer 142 filled in the first opening 131 (shown in FIG. 1D ) may constitute a first conductive blind hole 152 and fill the second opening 132 (shown in The first conductive layer 141 and the second conductive layer 142 in FIG. 1D) may constitute the second capacitor electrode 153, and the first conductive via 152 and the second capacitor electrode 153 are electrically separated from each other. The remaining portion of the first conductive layer 141 and the second conductive layer 142 on the dielectric surface 130a of the dielectric layer 130 may constitute a redistribution line 151, and the first conductive via 152 and the second capacitor electrode 153 may be correspondingly The redistribution line 151 is electrically connected to other mold layers or members. In this embodiment, the first conductive via 152 and the second capacitor electrode 153 can be formed by the same process. In this way, the manufacturing process can be simplified and the production efficiency and yield can be improved, and the two masking mask processes are not required, which can reduce the manufacturing cost.

Moreover, since the first conductive via 152 / the second capacitor electrode 153 is filled with a conductive material (eg, the first conductive layer 141 and the second conductive layer 142 ) into the first opening 131 / the second opening 132 . Therefore, the shape of the first conductive blind via 152 / the second capacitive electrode 153 substantially coincides with the shape of the corresponding first opening 131 / second opening 132. For example, the sidewall 155 of the first conductive via 152 / the second capacitor electrode 153 may be substantially a surface having no relief profile. In this embodiment, the sidewall 155 of the first conductive via 152 / the second capacitor electrode 153 may be a slope on a section perpendicular to the first surface 111 a, but the invention is not limited thereto.

In addition, in the process of forming the second capacitor electrode 153, the capacitor dielectric layer 120 is used as an etch stop layer, and the second capacitor electrode 153 is a conductive material (eg, the first conductive layer 141 and the second conductive layer 142). Filled into the second opening 132. Therefore, as shown in FIG. 1I, on the first surface 111a (eg, the paper surface of FIG. 1I), the projected area of the second capacitor electrode 153 on the first surface 111a is smaller than that of the capacitor dielectric layer 120 on the first surface 111a. The projected area, and the projected area of the capacitive dielectric layer 120 on the first surface 111a is smaller than the projected area of the first circuit layer 112 on the first surface 111a. Moreover, the first end 153a of the second capacitor electrode 153 in contact with the capacitor dielectric layer 120 has a smaller surface on the first surface 111a than the second end 153b where the second capacitor electrode 153 is in contact with the redistribution line 151. Orthographic projection.

In terms of circuit, the second capacitor electrode 153, the capacitor dielectric layer 120, and a portion of the first circuit layer 112 overlapping the second capacitor electrode 153/capacitor dielectric layer 120 may constitute a capacitor 10. In general, the capacitance of the capacitor 10 is related to the overlapping area of the two capacitor electrodes constituting the capacitor 10 (eg, the second capacitor electrode 153 constituting the capacitor 10 and the first capacitor electrode 112a). As shown in FIG. 1I, in the present embodiment, the projected area of the second capacitor electrode 153 on the first surface 111a (eg, the paper surface of FIG. 1I) is smaller than the projected area of the first circuit layer 112 on the first surface 111a. . Therefore, the capacitance of the capacitor 10 can be further adjusted by adjusting the opening area of the second opening 132 (shown in FIG. 1D) to adjust the overlapping area of the second capacitor electrode 153 and the first wiring layer 112. As a result, a large process margin is also produced in the fabrication of the capacitor 10 having a specific capacitance.

Next, referring to FIG. 1G, after the redistribution wiring layer 150 is formed, the protective layer 160 may be formed on the first surface 111a and/or the second surface 111b, and the protective layer 160 may expose a portion of the redistribution line 151. A connection pad 154 is defined. The protective layer 160 may be a solder mask or a dry film, but the invention is not limited thereto. The connection pad 154 may have a conductive terminal 171 thereon to electrically connect the redistribution wiring layer 150 to other film layers or components through the corresponding conductive terminals 171. In addition, in some embodiments, the connection pad 154 may further have a plating layer 170 plated with a metal layer or an alloy layer of nickel, palladium, gold or the like to enhance the bonding force between the connection pad 154 and other film layers or elements.

After the above process, the fabrication of the semiconductor package structure of the present embodiment can be substantially completed. Referring to FIG. 1G and FIG. 1H , the circuit board structure 100 of the present embodiment includes a circuit substrate 110 , a capacitor dielectric layer 120 , a dielectric layer 130 , and a redistribution circuit layer 150 . The circuit substrate 110 includes an insulating layer 111, a first wiring layer 112, a second wiring layer 113, and at least one conductive via 114. The insulating layer 111 has a first surface 111a and a second surface 111b opposite to the first surface 111a. The first wiring layer 112 is on the first surface 111a of the insulating layer 111. The second wiring layer 113 is on the second surface 111b of the insulating layer 111. The conductive vias 114 extend through the insulating layer 111 to electrically connect the first wiring layer 112 and the second wiring layer 113. The capacitor dielectric layer 120 is located on the first wiring layer 112 of the circuit substrate 110. The dielectric layer 130 covers a portion of the first wiring layer 112 and a portion of the capacitor dielectric layer 120. The redistribution wiring layer 150 includes a redistribution wiring 151, a first conductive blind via 152, and a second capacitor electrode 153. The redistribution line 151 is located on the dielectric layer 130. The first conductive via 152 is embedded in the dielectric layer 130 and connected to the first circuit layer 112. The second capacitor electrode 153 is embedded in the dielectric layer 130. The second capacitor electrode 153 has an opposite first end 153a and a second end 153b. The first end 153a is in contact with the capacitor dielectric layer 120, and the second end 153b is overlapped with the rewiring. Road 151 is in contact. The second capacitor electrode 153, the capacitor dielectric layer 120, and a portion of the first wiring layer 112 form a capacitor 10.

Since one of the electrodes constituting the capacitor 10 may be part of the first wiring layer 112, and the second capacitor electrode 153 constituting the other electrode of the capacitor 10 may be the same as other blind vias on the redistribution wiring layer 150. (eg, the first conductive blind via 152) is formed in a manner and/or step. Therefore, in terms of the process, the two electrodes constituting the capacitor 10 can be formed together in the step of forming other mold layers/members (for example, forming the other wiring holes on the first wiring layer 112 or the redistribution wiring layer 150). . In this way, the manufacturing process can be simplified, the production efficiency and the yield can be improved, and the manufacturing cost of the circuit board structure 100 can be reduced.

In this embodiment, the first conductive via 152 and the second capacitor electrode 153 are formed in the same manner, and the capacitance of the capacitor 10 can be adjusted by adjusting the size of the second capacitor electrode 153. In this way, the production process can be simplified and the production efficiency and yield can be improved. In addition, by the above-described formation manner, the total contract of the thickness T1 of the second capacitor electrode 153 and the thickness T2 of the capacitor dielectric layer 120 can be made slightly equal to the thickness T3 of the first conductive via 152.

In this embodiment, the insulating layer 111 may be a core layer, and the material of the core layer may be different from the material of the capacitor dielectric layer 120 and/or the dielectric layer 130. The material of the core layer may include a polymer glass fiber composite material, a glass substrate, a ceramic substrate, a polyimide (PI) glass fiber composite substrate, or other similar hard dielectric materials. In other words, the wiring board structure 100 of the present embodiment may be a core wiring board structure having a core layer, but the present invention is not limited thereto. In other embodiments, the material of the insulating layer 111 is the same as or similar to the material of the dielectric layer 130. That is, the insulating layer 111 can be a general dielectric layer. Thus, the circuit board structure 100 can be a coreless ( Coreless) circuit board structure, which may be formed, for example, by forming the above-mentioned capacitor 10 and/or other laminated film layers on opposite surfaces of the carrier board, and then removing the carrier board to form two independent coreless lines. Board structure 100.

2 is a partial top plan view showing a circuit board structure in accordance with a second embodiment of the present invention. In particular, FIG. 2 may be a top view similar to region R in FIG. 1G. The circuit board structure 200 of the present embodiment is similar to the circuit board structure 100 of the previous embodiment, and the main difference between the circuit board structure 200 and the circuit board structure 100 is that it is located on the first surface 111a (eg, the paper surface of FIG. 2). The projected shape of the edge 251a of the redistribution line 251 on the second capacitive electrode 153 may have a similar and corresponding projection shape corresponding to the first end 153a and/or the second end 153b.

Figure 3 is a partial top plan view showing a circuit board structure in accordance with a third embodiment of the present invention. In particular, FIG. 3 may be a top view similar to region R in FIG. 1G. The circuit board structure 300 of the present embodiment is similar to the circuit board structure 100 of the previous embodiment, and the main difference between the circuit board structure 300 and the circuit board structure 100 is that on the first surface 111a (eg, the paper surface of FIG. 3), The projected shape of the first end 353a and/or the second end 353b of the second capacitor electrode 353 may have a projection shape similar to that of the capacitor dielectric layer 120, and the projected areas of the first end 353a and the second end 353b are smaller than the capacitor dielectric layer 120. The projected area.

In this embodiment, on the first surface 111a (eg, the paper surface of FIG. 3), the projected shape of the first end 353a, the projected shape of the second end 353b, and the projected shape of the capacitive dielectric layer 120 may be similar. The quadrilateral type, but the invention is not limited thereto.

4A is a partial top plan view showing a circuit board structure in accordance with a fourth embodiment of the present invention. Fig. 4B is a schematic cross-sectional view taken along line A-A' of Fig. 4A. 4C is a partial perspective view of a circuit board structure in accordance with a fourth embodiment of the present invention. Specifically, FIG. 4C is a partial perspective view of one of the three-dimensional inductors in a circuit board structure in accordance with a fourth embodiment of the present invention. In addition, for the sake of clarity, in FIG. 4A, a portion of the mold layer or member is omitted.

The circuit board structure 400 of the present embodiment is similar to the circuit board structure 100 of the previous embodiment, and the main difference between the circuit board structure 400 and the circuit board structure 100 is that the circuit board structure 400 can have a three-dimensional inductance 20.

Please refer to FIG. 4A to FIG. 4C at the same time. In detail, in this embodiment, a plurality of conductive vias 116 and a plurality of conductive vias 118 are further included, and as shown in FIG. 4A and/or FIG. 4C, the first circuit layer 112, the conductive vias 116, and the conductive The via 118 and the second wiring layer 113 may constitute a three-dimensional inductor 20 having a conductive coil. In other words, the conductive coil of the three-dimensional inductor 20 penetrates the insulating layer 111 in a spiral form. In this way, the direction of the flux axis 20a of the inductor 20 can be made parallel to the first surface 111a (i.e., as shown in Fig. 4A).

In this way, passive components (eg, capacitor 10 and inductor 20) having different properties can be buried and integrated into the circuit board structure 400, and the volume of the circuit board structure 400 can be reduced.

In summary, the present invention forms part of the first circuit layer and the second capacitor electrode on the redistribution circuit layer to form two electrodes of the buried capacitor. In this way, in the manufacturing process of the circuit board structure with the buried capacitor, the manufacturing process can be simplified, the manufacturing efficiency and the yield can be improved, and the manufacturing cost of the circuit board structure can be reduced. Moreover, the capacitance of the capacitor can be further adjusted by adjusting the overlapping area of the second capacitor electrode and the first wiring layer. Therefore, in the process of manufacturing the capacitor, there is also a large process margin.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400‧‧‧ circuit board structure

10‧‧‧ Capacitance

20‧‧‧Inductance

20a‧‧‧Magnetic axis

110‧‧‧Line substrate

111‧‧‧Insulation

111a‧‧‧ first surface

111b‧‧‧second surface

111c‧‧‧through hole

112‧‧‧First line layer

112a‧‧‧First Capacitance Electrode

113‧‧‧Second circuit layer

114‧‧‧Electrical through holes

116‧‧‧ Conductive through hole

118‧‧‧ Conductive through hole

120‧‧‧Capacitive dielectric layer

130‧‧‧Dielectric layer

130a‧‧‧Dielectric surface

131‧‧‧First opening

132‧‧‧second opening

141‧‧‧First conductive layer

142‧‧‧Second conductive layer

150‧‧‧Re-distribution layer

151, 251‧‧‧Re-route

251a‧‧‧ edge

152‧‧‧First conductive blind hole

153, 353‧‧‧second capacitor electrode

155‧‧‧ side wall

153a, 353a‧‧‧ first end

153b, 353b‧‧‧ second end

154‧‧‧Connecting mat

160‧‧‧Protective layer

170‧‧‧ plating

171‧‧‧Electrical terminals

T1, T2, T3‧‧‧ thickness

R‧‧‧ area

1A to 1G are schematic cross-sectional views showing a manufacturing process of a wiring board structure in accordance with a first embodiment of the present invention. Fig. 1H is an enlarged view of a region R in Fig. 1G. Figure 1I is a top plan view of the region R of Figure 1G. 2 is a partial top plan view showing a circuit board structure in accordance with a second embodiment of the present invention. Figure 3 is a partial top plan view showing a circuit board structure in accordance with a third embodiment of the present invention. 4A is a partial top plan view showing a circuit board structure in accordance with a fourth embodiment of the present invention. Fig. 4B is a schematic cross-sectional view taken along line A-A' of Fig. 4A. 4C is a partial perspective view of a circuit board structure in accordance with a fourth embodiment of the present invention.

Claims (11)

A method for fabricating a circuit board structure includes: providing an insulating layer having a first surface and a second surface opposite to the first surface; forming a first wiring layer, a second wiring layer, and at least one conductive via The first circuit layer is located on the first surface of the insulating layer, and the first circuit layer includes a first capacitor electrode, the second circuit layer is located on the second surface of the insulating layer, and the at least one a conductive via extending through the insulating layer to electrically connect the first circuit layer and the second circuit layer; forming a capacitor dielectric layer on the first circuit layer to cover a portion of the first capacitor electrode; Forming a dielectric layer on the first circuit layer and the capacitor dielectric layer, the dielectric layer having a first opening and a second opening, wherein the first opening exposes a portion of the first circuit layer, and the The second opening exposes a portion of the capacitor dielectric layer; and a redistribution circuit layer is formed on the first circuit layer, the redistribution circuit layer includes a redistribution line, a first conductive blind hole and a second capacitor electrode, The redistributed line a first conductive via is located in the first opening and connected to the first circuit layer and the redistribution line, and the second capacitor electrode is located in the second opening and is on a dielectric surface of the dielectric layer The capacitor dielectric layer is in contact with each other, and the second capacitor electrode, the capacitor dielectric layer and the first capacitor electrode form a capacitor. The method for fabricating a circuit board structure according to claim 1, wherein the first conductive blind via and the second capacitor electrode are simultaneously formed by the same process. The method for fabricating a circuit board structure according to claim 1, wherein the step of forming the redistribution circuit layer comprises: forming a patterned photoresist layer on the dielectric layer and the first circuit layer, exposing the a first opening and the second opening; forming a conductive material on the dielectric layer and the first circuit layer, the conductive material filling the first opening, the second opening, and the patterned photoresist layer, wherein Filling the portion of the first opening with the conductive material to form the first conductive blind via, and filling a portion of the second opening with the conductive material to form the second capacitor electrode; and removing the patterned photoresist layer to form The redistributed line. The method for fabricating a circuit board structure according to claim 1, wherein the step of forming the redistribution circuit layer comprises: forming a conductive material on the dielectric layer and the first circuit layer, the conductive material covering the The dielectric surface of the dielectric layer fills the first opening and the second opening, wherein a portion of the conductive material that fills the first opening forms the first conductive blind via and fills the portion of the second opening The conductive material constitutes the second capacitor electrode; and a portion of the conductive material covering the dielectric surface of the dielectric layer is removed to form the redistribution line. The method for fabricating a circuit board structure according to claim 1, further comprising: arranging a plurality of conductive terminals on the redistribution circuit layer, wherein the conductive terminals are electrically connected to the redistribution circuit layer. A circuit board structure comprising: an insulating layer having a first surface and a second surface opposite to the first surface; a first circuit layer on the first surface of the insulating layer, the first circuit layer a first capacitor electrode; a second circuit layer on the second surface of the insulating layer; a first conductive via extending through the insulating layer to electrically connect the first circuit layer and the second circuit layer a capacitor dielectric layer on the first capacitor electrode of the first circuit layer; a dielectric layer covering at least a portion of the first circuit layer and a portion of the capacitor dielectric layer; and a redistribution circuit layer, The first conductive via is located on the dielectric layer and is connected to the first circuit layer and the second conductive via is disposed on the dielectric layer. Re-distributing the circuit, the second capacitor electrode is located in the dielectric layer, wherein the second capacitor electrode has opposite first ends and second ends, the first end is in contact with the capacitor dielectric layer, the second end Contacting the redistribution line, and the second The capacitor electrode, the capacitor dielectric layer and the first capacitor electrode form a capacitor. The circuit board structure of claim 6, wherein the front projection of the first end on the first surface is smaller than the orthographic projection of the second end on the first surface. The circuit board structure of claim 6, wherein the total contraction of the thickness of the second capacitor electrode and the thickness of the capacitor dielectric layer is slightly equal to the thickness of the first conductive via hole. The circuit board structure of claim 6, wherein the second capacitor electrode has a side wall connected to the first end and the second end, and the side wall is a slope. The circuit board structure of claim 6, further comprising a plurality of second conductive vias and a plurality of third conductive vias, located in the insulating layer, and a portion of the first circuit layer, a portion of the first The two circuit layers, the second conductive vias and the third conductive vias are spirally formed through the insulating layer to form a three-dimensional inductor. The circuit board structure of claim 6, further comprising: a plurality of conductive terminals disposed on the redistribution circuit layer and electrically connected to the redistribution circuit layer.