TW201932933A - Display panel - Google Patents

Abstract

A display panel includes pixel array and gate driving circuit. The pixel array consists of multiple pixel units. The pixel array includes multiple gate lines, multiple data lines and multiple sub pixels. The sub pixels respectively electrically connected with one of the gate lines and one of the data lines. The width of each of the sub pixels in the extending direction of the gate lines is larger than the width of each of the sub pixels in the extending direction of the data lines. Each of the pixel units includes two gate lines, three data lines, and six sub pixels. The gate driving circuit is disposed in the pixel array.

Description

Display panel

The present invention relates to a display panel, and more particularly to a display panel in which a gate drive circuit is located in a pixel array.

Gate on Array (GOA) refers to a technique in which a gate driving circuit is directly formed on an active device array substrate in place of an external driving chip when a panel is fabricated.

In general, the gate drive circuit is disposed outside the display area of the panel and is located at the border of the panel. However, the gate drive circuit typically occupies a large portion of the frame area. If the gate drive circuit can be moved into the display area, it is bound to greatly reduce the frame area design and increase the display area. Therefore, it is necessary to improve the existing gate drive circuit substrate technology.

The invention provides a display panel capable of reducing the area occupied by the gate driving circuit in the panel frame area.

The display panel of the present invention includes a pixel array and a gate driving circuit. A pixel array is composed of a plurality of pixel units. The pixel array includes a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels. The plurality of sub-pixels are electrically connected to one of the gate lines and one of the data lines. The width of the sub-pixel in the extending direction of the gate line is greater than the width of the sub-pixel in the extending direction of the data line. Each of the pixel units includes two gate lines, three data lines, and six sub-pixels. The gate drive circuit is located in the pixel array.

At least one object of the present invention is to provide a gate drive circuit in a pixel array. According to this, the technical effect of reducing the cost and greatly reducing the frame can be obtained.

The above described features and advantages of the invention will be apparent from the following description.

1 is a top plan view of a display panel in accordance with an embodiment of the present invention.

Referring to FIG. 1 , the display panel 100 of the present embodiment includes a display area AR and a non-display area NR , wherein the non-display area NR is located on one side of the display area AR or the non-display area NR surrounds the display area AR. In other words, the non-display area NR can be located on one side of the display area AR, and can be adjusted according to different needs. For example, the non-display area NR is surrounded by the display area AR. When applied to the rectangular display area, the non-display area NR may be located on one side, two sides, three sides or four sides of the display area AR; In the non-rectangular display area or the circular display area, the non-display area NR may be adjacent to the display area AR, and a part of the periphery or all of the periphery forming the display area AR is a non-display area NR. In general, a Gate on Array (GOA) is usually fabricated on the non-display area NR of the display panel, for example, at a position of the bezel. However, in the embodiment of the invention, the gate driving circuit is disposed in the display area AR. Hereinafter, how to set the gate driving circuit in the display area AR will be described.

In detail, the display panel 100 of the present embodiment may include a pixel array disposed in the display area AR. The arrangement of the pixel arrays can be, for example, two different embodiments of FIGS. 2A and 2B.

2A is a schematic view showing the arrangement of pixel arrays according to an embodiment of the invention.

As shown in FIG. 2A, the pixel array 10 is located in the display area AR of FIG. 1, and the pixel array 10 is composed of a plurality of repeatedly arranged pixel units PX1 to PX4. The pixel array 10 includes a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels. The pixel units PX1~PX4 respectively include two gate lines, three data lines, and six sub-pixels. In FIG. 2A, a pixel unit in which four pixels are repeatedly arranged in the pixel unit PX1, the pixel unit PX2, the pixel unit PX3, and the pixel unit PX4 will be described. It should be noted, however, that display panel 100 should actually include more repeating pixel units.

In FIG. 2A, the first to sixth data lines D1 to D6 are sequentially arranged, and the first to fourth scanning lines G1 to G4 are sequentially arranged. The pixel unit PX1 includes a first data line D1, a second data line D2, a third data line D3, a first gate line G1, and a second gate line G2, and the pixel unit PX2 includes a fourth data line D4. The fifth data line D5, the sixth data line D6, the first gate line G1, and the second gate line G2, the pixel unit PX3 includes a first data line D1, a second data line D2, and a third data line D3, The three gate line G3 and the fourth gate line G4, the pixel unit PX4 includes a fourth data line D4, a fifth data line D5, a sixth data line D6, a third gate line G3, and a fourth gate line G4. There is no gate line or data line between adjacent ones of the pixel units PX1 to PX4.

In the present embodiment, the arrangement of the pixel unit PX2, the pixel unit PX3, and the pixel unit PX4 is similar to that of the pixel unit PX1, and therefore, only the pixel unit PX1 is taken as a representative.

The pixel unit PX1 includes first to sixth sub-pixels SPX1 to SPX6. Each of the first to sixth sub-pixels SPX1 to SPX6 includes a switching element T and a pixel electrode PE, and the pixel electrode PE is electrically connected to the switching element T.

In this embodiment, the widths of the first to sixth sub-pixels SPX1 to SPX6 in the extending direction E2 of the first to fourth gate lines G1 to G4 are greater than the first to sixth sub-pixels SPX1 to SPX6. The width of the first to sixth data lines D1 to D6 in the extending direction E1. For example, the width of the switching element T and the pixel electrode PE in the extending direction E2 of the first to fourth gate lines G1 G G4 is greater than the switching element T and the pixel electrode PE in the first to sixth data lines D1~ The width of D6 in the direction of extension E1. In detail, taking the second sub-pixel SPX2 as an example, the second sub-pixel SPX2 is defined by the first gate line G1, the second gate line G2, the first data line D1, and the second data line D2. . The width of the second sub-pixel SPX2 in the extending direction E2 is, for example, about the maximum spacing between the first data line D1 and the second data line D2, and the width of the second sub-pixel SPX2 in the extending direction E1 is, for example, approximately The maximum spacing between the first gate line G1 and the second gate line G2. In the present embodiment, the widths of the first to sixth sub-pixels SPX1 to SPX6 in the extending direction E2 are approximately the same, and the widths of the first to sixth sub-pixels SPX1 to SPX6 in the extending direction E1 are approximately the same. In this embodiment, the width of the sub-pixel in the extension direction E2 is greater than the width of the extension direction E1, and is suitable for application to an elongated display device, such as a display device for an interior mirror. Etc., but the invention is not limited thereto.

In the pixel unit PX1 of the embodiment, the first to sixth sub-pixels SPX1 to SPX6 are electrically connected to one of the gate lines and one of the data lines, respectively. Specifically, the switching elements T of the first sub-pixel SPX1 are electrically connected to the first gate line G1 and the first data line D1, respectively. The switching elements T of the second sub-pixel SPX2 are electrically connected to the first gate line G1 and the second data line D2, respectively. The switching elements T of the third sub-pixel SPX3 are electrically connected to the second gate line G2 and the first data line D1, respectively. The switching elements T of the fourth sub-pixel SPX4 are electrically connected to the first gate line G1 and the third data line D3, respectively. The switching elements T of the fifth sub-pixel SPX5 are electrically connected to the second gate line G2 and the second data line D2, respectively. The switching elements T of the sixth sub-pixel SPX6 are electrically connected to the second gate line G2 and the third data line D3, respectively.

In the embodiment of FIG. 2A, the first and second gate lines G1 and G2 are sequentially arranged, and the second sub-pixel SPX2 and the fifth sub-pixel SPX5 are located at the first gate line G1 and the second gate line G2. between. In the embodiment of FIG. 2A, the first to third data lines D1 to D3 are sequentially arranged, and the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are located on the first data line D1 and the first There is no sub-pixel between the two data lines D2 and between the second data line D2 and the third data line D3. In the present embodiment, the pixel units PX1 to PX4 in the pixel array 10 are exemplified by a rectangle, but the invention is not limited thereto. In other embodiments, the shape of the pixel units PX1 P PX4 may also be a V shape. In the present embodiment, the first to fourth gate lines G1 to G4 and the first to sixth data lines D1 to D6 of the pixel units PX1 to PX4 are defined as a straight line, but the present invention does not limit. In other embodiments, the first to fourth gate lines G1 G G4 and/or the first to sixth data lines D1 D D6 defining the pixel units PX1 P PX4 may be zigzag or other shapes.

2B is a schematic diagram showing the arrangement of pixel arrays according to an embodiment of the invention. It is to be noted that the embodiment of FIG. 2B follows the same reference numerals and parts of the embodiment of FIG. 2A, wherein the same or similar elements are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiment, and details are not described herein.

As shown in FIG. 2B, the pixel array 20 is composed of a plurality of repeatedly arranged pixel units PX1, PX2. In the present embodiment, the arrangement of the pixel unit PX2 is similar to that of the pixel unit PX1, and therefore, only the pixel unit PX1 is taken as a representative.

In FIG. 2B, the first to seventh data lines D1 to D7 are sequentially arranged, and the first to fourth scan lines G1 to G4 are sequentially arranged. The pixel unit PX1 includes first to third data lines D1 to D3 and first to fourth gate lines G1 to G4, and the pixel unit PX2 includes fourth to sixth data lines D4 to D6 and first to first Four gate lines G1~G4. There is no gate line or data line between the pixel unit PX1 and the pixel unit PX2.

The pixel unit PX1 includes first to third data lines D1 to D3, first to fourth gate lines G1 to G4, and first to twelfth sub pixels SPX1 to SPX12. The widths of the first to twelfth subpixels SPX1 to SPX12 of the embodiment of FIG. 2B in the extending direction E1 and the extending direction E2 are, for example, approximately the same as the second subpixel SPX2 of the embodiment of FIG. 2A, and no longer Narration.

Each of the first to twelfth subpixels SPX1 to SPX12 includes a switching element T and a pixel electrode PE, and the pixel electrode PE is electrically connected to the switching element T.

In the embodiment of FIG. 2B, the first to twelfth sub-pixels SPX1 to SPX12 are electrically connected to one of the gate lines and one of the data lines, respectively. The first to sixth sub-pixels SPX1 to SPX6 of the embodiment of FIG. 2B are similar to the first to sixth sub-pixels SPX1 to SPX6 of the embodiment of FIG. 2A, and are not described herein again.

The switching elements T of the seventh sub-pixel SPX7 are electrically connected to the third gate line G3 and the second data line D2, respectively. The switching elements T of the eighth sub-pixel SPX8 are electrically connected to the third gate line G3 and the third data line D3, respectively. The switching elements T of the ninth sub-pixel SPX9 are electrically connected to the fourth gate line G4 and the second data line D2, respectively. The switching element T of the tenth sub-pixel SPX10 is electrically connected to the third gate line G3 and the fourth data line D4, respectively, wherein the fourth data line D4 is a component in the pixel unit PX2, and the pixel unit PX2 is adjacent to Pixel element PX1. The switching elements T of the eleventh sub-pixel SPX11 are electrically connected to the fourth gate line G4 and the third data line D3, respectively. The switching elements T of the twelfth sub-pixel SPX12 are electrically connected to the fourth gate line G4 and the fourth data line D4, respectively.

In the embodiment of FIG. 2B, the first to fourth gate lines G1 G G4 are sequentially arranged, and the second sub-pixel SPX2 and the fifth sub-pixel SPX 5 are located at the first gate line G1 and the second gate line G2. Between the eighth sub-pixel SPX8 and the eleventh sub-pixel SPX11 is located between the third gate line G3 and the fourth gate line G4. In the present embodiment, the third sub-pixel SPX3 and the seventh sub-pixel SPX7 of the pixel unit 10 and the sixth sub-pixel SPX6 and the tenth sub-pixel SPX10 do not have a gate line. The first to third data lines D1 to D3 are sequentially arranged, and the seventh sub-pixel SPX7, the eighth sub-pixel SPX8, and the ninth sub-pixel SPX9 are located between the first data line D1 and the second data line D2, and There is no sub-pixel between the second data line D2 and the third data line D3.

3 is a circuit diagram of a drive unit in accordance with an embodiment of the present invention.

Referring to FIG. 3, the front stage input line 140, the rear stage input line 150 and the output line 160 are respectively connected to three gate lines. The power signal line 110 is electrically connected to the voltage VSS, and the voltage VSS is, for example, a voltage supplied by the power supply or a ground voltage.

In the embodiment of FIG. 3, the driving unit includes a first active component M1, a second active component M2, a third active component M3, a fourth active component M4, a fifth active component M5, a sixth active component M6, and a seventh active Element M7, wherein each active element has a control end, a first end and a second end. Specifically, the control end of the first active component M1 is electrically connected to the rear input line 150, and the second end is electrically connected to the power signal line 110. The control terminal of the second active component M2 is electrically connected to the first end of the first active component M1, and the second terminal of the second active component M2 is electrically connected to the power signal line 110. The control end of the third active component M3 is electrically connected to the first end of the second active component M2, the first end is electrically connected to the first end of the first active component M1, and the second end is electrically connected to the power signal Line 110. In addition, the control end of the fourth active component M4 is electrically connected to the first input line 140, and the second end is electrically connected to the first end of the first active component M1. The control terminal of the fifth active component M5 is electrically connected to the second clock signal line 130. The first end is electrically connected to the output line 160, and the second end is electrically connected to the power signal line 110. In addition, the control end of the sixth active component M6 is electrically connected to the first end of the second active component M2, the first end is electrically connected to the output line 160, and the second end is electrically connected to the power signal line 110. In the seventh active component M7, the control terminal is electrically connected to the first end of the first active component M1, and the first end is electrically connected to the first clock signal line 120, and the second end is electrically connected to the output. Line 160.

In this embodiment, the driving unit further includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 is electrically connected to the output line 160 and the first end of the first active device M1. In other words, the first capacitor C1 is formed between the control end of the seventh active device M7 and the second end thereof. The second capacitor C2 is electrically connected to the first clock signal line 120 and the first end of the second active device M2. In other words, the second capacitor C1 can also be formed at the first end and the second end of the seventh active device M7. Between the first ends of the active component M2.

In this embodiment, the first end of the first active component M1, the control end of the second active component M2, the first end of the third active component M3, the second end of the fourth active component M4, and the seventh active component M7 The control terminal and the first capacitor C1 are electrically connected to the signal point Q. In other words, the end points of the active elements can be coupled to each other through the signal point Q. In this embodiment, the first end of the second active component M2, the control end of the third active component M3, the control terminal of the sixth active component M6, and the second capacitor C2 are electrically connected to the signal point P, similarly, the above The end points of the active elements can also be coupled to each other through the signal point P. In some embodiments, the signal point Q and the signal point P can generate a floating signal, such as a floating voltage value (a non-fixed voltage value).

4 is a schematic diagram of an arrangement of a driving unit according to an embodiment of the invention. It should be noted that the embodiment of FIG. 4 follows the component numbers and parts of the embodiment of FIG. 1, FIG. 2A, FIG. 2B and FIG. 3, wherein the same or similar reference numerals are used to denote the same or similar elements, and Description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiment, and details are not described herein.

The gate driving circuit DR is located in the pixel array (including the first to eleventh gate lines G1 to G11, the first to twenty-fifth data lines D1 to D25, and the plurality of sub-pixels SPX). It should be noted that although FIG. 4 only frames one pixel unit PX, it is only used for illustration, and FIG. 4 actually includes a plurality of repeatedly arranged pixel units PX. In addition, the pixel unit PX of FIG. 4 is exemplified by a pixel unit PX including six sub-pixels SPX (such as the pixel array 10 of FIG. 2A), but the invention is not limited thereto. The pixel unit PX may also include twelve sub-pixels SPX (such as the pixel array 20 of FIG. 2B).

In this embodiment, there is no need to set a gate line between the partially adjacent sub-pixels SPX (and/or the pixel unit PX), and a portion of the adjacent sub-pixels SPX (and/or pixel unit PX) There is no need to set the data line. Therefore, the gate driving circuit DR can be correspondingly disposed on the area between the adjacent sub-pixels SPX (and/or the pixel unit PX).

In this embodiment, the gate driving circuit DR includes a plurality of first to seventh active elements M1 to M7 and a plurality of signal lines 100 (thick line segments in FIG. 4, including solid lines, broken lines, and dotted lines). The first to seventh active elements M1 to M7 are disposed between two adjacent pixel units PX and/or between two adjacent sub-pixels SPX, and the plurality of signal lines 100 are disposed adjacent to each other. Between the pixel units PX and/or between two adjacent sub-pixels SPX.

In this embodiment, the gate driving circuit DR includes a first driving unit DR1 and a second driving unit DR2, and the first driving unit DR1 and the second driving unit DR2 respectively include first to seventh active elements M1 to M7 and a plurality of Signal line 100 and a plurality of capacitors C1, C2. The signal line 100 includes a signal line 100A disposed substantially in parallel with the first to twenty-fifth data lines D1 to D25, and a signal line 100B disposed substantially in parallel with the first to eleventh gate lines G1 to G11. In some embodiments, the signal line 100A is formed simultaneously with the data line, and the signal line 100B is formed simultaneously with the gate line, but the invention is not limited thereto. The part of the signal line 100A is electrically connected to the part of the signal line 100B, and the part of the signal line 100A is electrically separated from the part of the signal line 100B. In the present embodiment, the signal line 100, the first to eleventh gate lines G1 to G11, and the first to twenty-fifth data lines D1 to D25 are taken as a straight line, but the invention is not limited thereto. In other embodiments, the signal line 100, the first to eleventh gate lines G1 G G11, and the first to twenty-fifth data lines D1 D D25 may be zigzag or other shapes.

Referring to FIG. 3 and FIG. 4 , the signal line 100 includes a power signal line 110 , a first clock signal line 120 , a second clock signal line 130 , a front stage input line 140 , a rear stage input line 150 , and an output line 160 . The front stage input line 140, the rear stage input line 150 and the output line 160 are respectively connected to three gate lines. The power signal line 110 is electrically connected to the voltage VSS, and the voltage VSS is, for example, a voltage supplied by the power supply or a ground voltage.

In this embodiment, the arrangement relationship between the first to seventh active elements M1 to M7 of the first driving unit DR1 and the arrangement relationship between the first to seventh active elements M1 to M7 of the second driving unit DR2 are mutually Mirrory symmetry. For example, in the first driving unit DR1, the fourth active element M4 is located to the right of the first active element M1 and to the left of the seventh active element M7. However, in the second driving unit DR2, the fourth active element M4 is located to the left of the first active element M1 and to the right of the seventh active element M7. In the first driving unit DR1, the seventh active element M7 is located to the right of the fourth active element M4 and to the left of the fifth active element M5. However, in the second driving unit DR2, the seventh active element M7 is located to the left of the fourth active element M4 and to the right of the fifth active element M5. In the first driving unit DR1, the second active element M2 and/or the third active element M3 are located to the left of the sixth active element M6. However, in the second driving unit DR2, the second active element M2 and/or the third active element M3 are located to the right of the sixth active element M6. It is to be noted that, in the first driving unit DR1 and the second driving unit DR2, the second active element M2 and the third active element M3 are disposed in the same area. Therefore, in this embodiment, the second active element M2 And the third active component M3 is regarded as one body.

From another point of view, in the first driving unit DR1 of FIG. 3, the first active device M1 (and/or the first capacitor C1) and the fourth active device M4 are sequentially included from left to right (and/or The second active component M2, the third active component M3), the seventh active component M7 (and/or the second capacitor C2), the sixth active component M6, and the fifth active component M5 are in the second driving unit DR2 of FIG. The first active component M1 (and/or the first capacitor C1), the fourth active component M4 (and/or the second active component M2, the third active component M3), and the seventh active component are sequentially included from right to left. M7 (and/or second capacitor C2), sixth active element M6, and fifth active element M5. The left side of FIG. 3 is defined, for example, as a side close to the first data line D1, and the right side is defined, for example, as a side close to the twenty-fifth data line D25. In this way, the relative positions of the respective components of the first driving unit DR1 and the relative positions of the components of the second driving unit DR2 are mirror-symmetrical.

Referring to FIG. 4, the first driving unit DR1 and the second driving unit DR2 have their required signal line 100A and signal line 100B between two adjacent sub-pixels SPX. At the same time, please refer to FIG. 2A or FIG. 2B. In the pixel array 10, no data lines or gate lines are provided between the sub-pixels SPX of some adjacent two rows or two columns. Therefore, in this embodiment, the first driving unit DR1 and the second driving unit DR2 can be disposed in the space (the space where the data line or the gate line is not provided), and then the gate driving circuit DR is disposed in the display area AR, Achieve the effect of a narrow border. In this embodiment, the first active device M1, the fourth active device M4, the fifth active device M5, and the seventh active device M7 in the first driving unit DR1 are disposed on the same horizontal line LN1 along the extending direction E2 of the gate line. The second active element M2, the third active element M3, and the sixth active element M6 are disposed on another identical horizontal line LN2 along the extending direction E2 of the gate line.

In this embodiment, the first active device M1, the fourth active device M4, the fifth active device M5, and the seventh active device M7 in the second driving unit DR2 are disposed on the same horizontal line LN3 along the extending direction E2 of the gate line. The second active element M2, the third active element M3, and the sixth active element M6 are disposed on another identical horizontal line LN4 along the extending direction E2 of the gate line.

For example, the setting of "the same horizontal line" means that at least a portion of the active elements of the driving unit are spaces disposed between adjacent two gate lines. Taking the first active component M1, the fourth active component M4, the fifth active component M5, and the seventh active component M7 of the driving unit DR1 of FIG. 4 as an example, the first active component M1 and the fourth active component of the first driving unit DR1 The M4, the fifth active device M5, and the seventh active device M7 are located in a space between the fourth gate line G4 and the fifth gate line G5, and a space thereof may extend along the extending direction E2 of the gate line.

Therefore, in this embodiment, the first active component M1, the fourth active component M4, the fifth active component M5, and the seventh active component M7 of the driving unit DR1 are disposed in the same space, and the second active component M2, the third The active element M3 and the sixth active element M6 are disposed in the same space. The first active element M1, the fourth active element M4, the fifth active element M5, and the seventh active element M7 of the driving unit DR2 are disposed in the same space, and the second active element M2, the third active element M3, and the sixth active element M6 is set in the same space. The same space as described above refers to the space between two adjacent gate lines, and can also be represented by "same horizontal line".

Although the foregoing "same horizontal line" is exemplified by a space disposed between two adjacent gate lines, the present invention is not limited thereto. In some embodiments, the setting of "the same horizontal line" can be exemplified by the arrangement between the sub-pixels SPX of the adjacent two columns. For example, as shown in FIG. 4, "set on the same horizontal line LN1" may be set between the fifth column sub-pixel SPX and the sixth column sub-pixel SPX.

In some embodiments, the shorter the signal line electrically connected to the signal point Q and the signal point P, the better the display panel has. In this embodiment, the first capacitor C1 is disposed adjacent to the first active component M1, for example, between the same four adjacent pixel units PX, and the second active component M2 is disposed adjacent to the third active component M3. For example, it is located between the same four adjacent pixel units PX. Therefore, the signal line electrically connected to the signal point Q and the signal point P can be relatively short.

In some embodiments, the clock signal of the display panel is grouped by 1, 2, 4, 8, or 16. In the embodiment of the present invention, the gate driving circuit DR includes a plurality of driving units, such as the first driving unit DR1 and the second driving unit DR2, and the plurality of driving units may be serially connected to each other to form a multi-stage shift register. A circuit to provide drive signals for each gate line. For example, the gate driving circuit DR includes x driving units, which are respectively the first driving unit DR1, the second driving unit DR2, the third driving unit DR3, ... and so on to the xth driving unit DRx, where x is positive Integer. In some embodiments, the xth gate drive circuit DRx also forms an n-stage shift register circuit, where n is a positive integer. For example, the driving signal of the first-stage gate line (the first gate line G1) is generated by the output line of the first driving unit DR1, and the second driving unit DR2 generates the second-level gate line (the second gate line) G2) driving signal, the third driving unit DR3 generates a driving signal of the third-level gate line (third gate line G3), and so on to the xth driving unit DRx to generate the nth-level gate line (nth The drive signal of the gate line Gn), the x drive units DR can generate up to x different levels of drive signals, but the invention does not specifically limit x equal to n. In the embodiment of FIG. 4, the clock signals are grouped in groups of eight, and the first clock signal 120 of the first driving unit DR1 is electrically connected to the third level (n=3) clock signal HC3, and the first The driving unit DR1 is a driving signal for generating a third-level gate line (third gate line G3), that is, taking n=3 as an example, please also match the circuit diagram of FIG. When the first driving unit DR1 generates a driving signal of the third-level gate line (third gate line G3) (ie, n=3), the output line 160 is electrically connected to the third-level gate line (the third gate) The line G3), the front stage input line 140 is electrically connected to the first stage gate line (the first gate line G1), and the rear stage input line 150 is electrically connected to the seventh level gate line (the seventh gate line G7) The first clock signal line 120 is electrically connected to the third stage clock signal HC3 and the second clock signal line 130 is electrically connected to the seventh stage clock signal HC7. And so on, when the second driving unit DR2 generates the driving signal of the seventh-level gate line (the seventh gate line G7) (ie, n=7), the output line 160 is electrically connected to the seventh-level gate line. (the seventh gate line G7), the front stage input line 140 is electrically connected to the fifth level gate line (the fifth gate line G5), and the rear stage input line 150 is electrically connected to the eleventh level gate line ( The eleventh gate line G11), the first clock signal line 120 is electrically connected to the seventh stage clock signal HC7 and the second clock signal line 130 is electrically connected to the eleventh level clock signal HC11 (ie HC3) ).

In other words, in the embodiment of FIG. 4, the first clock signal line 120 of the first driving unit DR1 can be electrically connected to the second clock signal line 130 of the second driving unit DR2, and the first driving unit DR1 The second clock signal line 130 can be electrically connected to the first clock signal line 120 of the second driving unit DR2.

5A-5D are schematic diagrams showing an arrangement of a driving unit according to an embodiment of the invention. It should be noted that the embodiment of FIGS. 5A to 5D follows the same reference numerals and parts of the embodiment of FIG. 3, wherein the same or similar elements are used to denote the same or similar elements, and the same technical content is omitted. Description. For the description of the omitted part, reference may be made to the foregoing embodiment, and details are not described herein.

Please refer to FIG. 5A to FIG. 5D . FIG. 5A to FIG. 5D are schematic diagrams of different parts in the display panel of the same embodiment, for example. 5A illustrates portions of the first to eleventh gate lines G1 to G11 and the first to twenty-fifth data lines D1 to D25, and FIG. 5B illustrates second to twelfth gate lines G2 to G12. And the portions of the twenty-fifth to forty-ninth data lines D25 to D49, and FIG. 5C shows the third to thirteenth gate lines G3 to G13 and the forty-ninth to seventy-third data lines D49 to D73. The portion of FIG. 5D shows the portions of the fourth to fourteenth gate lines G4 to G14 and the seventy-third to seventy-seventh data lines D73 to D97.

The main difference between the embodiment of FIG. 5A and FIG. 5D and the embodiment of FIG. 4 is that the embodiment of FIG. 4 is an example in which the first driving unit DR1 and the second driving unit DR2 are a group of repeating units, and FIG. 5A to FIG. 5D. In the embodiment, the first to eighth driving units DR1 to DR8 are taken as a group of repeating units, and the different groups of repeating units can be electrically connected to different levels of gate lines, for example.

In the present embodiment, the gate line includes first to fourteenth gate lines G1 to G14 which are sequentially arranged. The output lines 160 of the first, third, fifth, and seventh driving units DR1, DR3, DR5, and DR7 (shown in FIG. 3) are electrically connected to the third to sixth gate lines G3 to G6, respectively. It can be said that the first, third, fifth, and seventh driving units DR1, DR3, DR5, and DR7 respectively generate driving signals of the third to sixth (n=3~n=6) gate lines, the front stage. The input lines 140 (shown in FIG. 3 ) are electrically connected to the first to fourth gate lines G1 G G4 , respectively, and the subsequent input lines 150 (shown in FIG. 3 ) are electrically connected to the seventh to the third Ten gates G7~G10.

The output lines 160 of the second, fourth, sixth, and eighth driving units DR2, DR4, DR6, and DR8 (shown in FIG. 3) are electrically connected to the seventh to tenth gate lines G7 to G10, respectively. It can be said that the fifth to eighth driving units DR5~DR8 respectively generate driving signals of the seventh to tenth (n=7~n=10) gate lines, and the front stage input lines 140 are electrically connected to the fifth. To the eighth gate line G5~G8, the rear stage input line 150 (shown in FIG. 3) is electrically connected to the eleventh to fourteenth gate lines G11~G14, respectively.

In this embodiment, the arrangement relationship between the active elements of the first, third, fifth, and seventh driving units DR1, DR3, DR5, and DR7 is similar, and the second, fourth, sixth, and eighth driving units are similar. The arrangement relationship between the active elements of each of the units DR2, DR4, DR6, and DR8 is similar. The arrangement relationship between the active elements of the first, third, fifth, and seventh driving units DR1, DR3, DR5, and DR7 is respectively associated with the second, fourth, sixth, and eighth driving units DR2, DR4, DR6, and DR8 The active elements are mirror-symmetrical to each other. If the active components of the first to fourth driving units DR1 to DR4 are translated downward and then shifted to the right, the active components of the fifth to eighth driving units DR5 to DR8 can be overlapped. .

FIG. 6 is a schematic diagram of a setting manner of a driving unit according to an embodiment of the invention. It is to be noted that the embodiment of FIG. 6 follows the component numbers and parts of the embodiment of FIG. 3, wherein the same or similar elements are denoted by the same or similar reference numerals, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiment, and details are not described herein.

The main difference between the embodiment of FIG. 6 and the embodiment of FIG. 3 is that the arrangement relationship between the active elements of the first driving unit DR1 of FIG. 3 and the arrangement relationship between the active elements of the second driving unit DR2 are mirror-symmetrical with each other. The arrangement relationship between the active elements of the first driving unit DR1 of FIG. 6 and the arrangement relationship between the active elements of the second driving unit DR2 are substantially the same.

Referring to FIG. 6, the driving unit includes a first driving unit DR1 and a second driving unit DR2. The gate line includes first to eighth gate lines G1 to G8 arranged in order, and the data line includes first to thirty-sixth data lines D1 to D34 arranged in order. The output lines 160 of the first and second driving units DR1 and DR2 (shown in FIG. 4 ) are electrically connected to the third and fourth gate lines G3 and G4 , respectively, and the first and second driving units are also said. DR1 and DR2 respectively generate drive signals for the third and fourth (n=3, n=4) gate lines. The first and second driving units DR1, DR2 are respectively electrically connected to the first and second gate lines G1, G2, respectively, in the input line 140 (shown in FIG. 4). The first and second driving units DR1, DR2 subsequent stage input lines 150 (shown in FIG. 4) are electrically connected to the seventh and eighth gate lines G7, G8, respectively.

In this embodiment, the first driving unit DR1 and the second driving unit DR2 have first to seventh active elements M1 M M7 and capacitors C1 and C2, respectively, and the first to seventh active elements M1 of the first driving unit DR1. The arrangement relationship between the ~M7 and the capacitors C1 and C2 is similar to the arrangement relationship between the first to seventh active elements M1 to M7 and the capacitors C1 and C2 of the second driving unit DR2. For example, in the first driving unit DR1, the active element M4 is located on the right side of the active element M1 and on the left side of the active element M7, and in the second driving unit DR2, the active element M4 is also located on the right side of the active element M1 and the active element The left side of the M7. In the first driving unit DR1, the active element M7 is located to the right of the active element M4 and to the left of the active element M5, and in the second driving unit DR2, the active element M7 is also located to the right of the active element M4 and to the left of the active element M5. In the first driving unit DR1, the active element M2 and/or the active element M3 are located to the left of the active element M6, and in the second driving unit DR2, the active element M2 and/or the active element M3 are also located to the left of the active element M6.

In summary, in some embodiments of the invention, the gate drive circuit is disposed in the pixel array. According to this, the technical effect of reducing the cost and greatly reducing the frame can be obtained. In some embodiments of the present invention, the active components electrically connected to the signal point Q and the signal point P are disposed at adjacent positions, so that the electrical connection to the signal point Q and the signal point P signal line can be relatively short, and the display panel has Better quality.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

1‧‧‧ display panel

10, 20‧‧‧ pixel array

100, 100A, 100B‧‧‧ signal lines

110‧‧‧Power signal line

120‧‧‧First clock signal line

130‧‧‧second clock signal line

140‧‧‧Previous input line

150‧‧‧After input line

160‧‧‧output line

AR‧‧‧ display area

C1, C2‧‧‧ capacitor

D1~D97‧‧‧ data line

DR, DR1~DR8‧‧‧ drive unit

E1, E2‧‧‧ extending direction

G1~G14‧‧‧ gate line

HC‧‧‧ clock signal

LN1~LN4‧‧‧ horizontal line

M1~M7‧‧‧ active components

NR‧‧‧Non-display area

P, Q‧‧‧ signal point

PE‧‧‧ pixel electrode

PX, PX1~PX4‧‧‧ pixel unit

SPX, SPX1~SPX12‧‧‧ sub-pixels

T‧‧‧ switching components

VSS‧‧‧ voltage

1 is a top plan view of a display panel in accordance with an embodiment of the present invention. 2A is a schematic view showing the arrangement of pixel arrays according to an embodiment of the invention. 2B is a schematic diagram showing the arrangement of pixel arrays according to an embodiment of the invention. 3 is a circuit diagram of a drive unit in accordance with an embodiment of the present invention. 4 is a schematic diagram of an arrangement of a driving unit according to an embodiment of the invention. 5A-5D are schematic diagrams showing an arrangement of a driving unit according to an embodiment of the invention. FIG. 6 is a schematic diagram of a setting manner of a driving unit according to an embodiment of the invention.

Claims (11)

A display panel comprising: a pixel array, comprising a plurality of pixel units, the pixel array comprising: a plurality of gate lines and a plurality of data lines; and a plurality of sub-pixels electrically connected to one of the pixels a gate line and one of the data lines, and a width of each of the sub-pictures in the extending direction of the gate lines is greater than a width of each of the sub-pictures in an extending direction of the data lines, wherein each of the pixels The unit includes two gate lines, three data lines, and six sub-pixels; and a gate driving circuit located in the pixel array. The display panel of claim 1, wherein the gate driving circuit comprises a plurality of driving units, each of the driving units comprises a plurality of active components, a plurality of signal lines and a plurality of capacitors, wherein the signal lines One of them is disposed substantially parallel to the data lines or the gate lines. The display panel of claim 2, wherein the signal lines comprise a power signal line, a first clock signal line, a second clock signal line, a front stage input line, and a rear stage input. a line and an output line, wherein the front stage input line, the rear stage input line and the output line are respectively connected to three gate lines. The display panel of claim 3, wherein each of the driving units comprises: a first active component having a control end, a first end and a second end, wherein the control of the first active component The second active end of the first active component is electrically connected to the power signal line; the second active component has a control end, a first end and a second end The control unit of the second active component is electrically connected to the first end of the first active component, and the second end of the second active component is electrically connected to the power signal line; a control end, a first end and a second end, wherein the control end of the third active component is electrically connected to the first end of the second active component, and the first end of the third active component is electrically connected to a first end of the first active component, and a second end of the third active component is electrically connected to the power signal line; a fourth active component has a control end, a first end and a second end, Wherein the control end of the fourth active component and the first The first end of the active component is electrically connected to the front input line, the second end of the fourth active component is electrically connected to the first end of the first active component, and a fifth active component has a control terminal. a first end and a second end, wherein the control end of the fifth active component is electrically connected to the second clock signal line, and the first end of the fifth active component is electrically connected to the output line, and the The second active end of the fifth active component is electrically connected to the power signal line; a sixth active component has a control end, a first end and a second end, wherein the control end of the sixth active component is electrically connected The first end of the second active component is electrically connected to the output line, and the second end of the sixth active component is electrically connected to the power signal line; The active component has a control end, a first end and a second end, wherein the control end of the seventh active component is electrically connected to the first end of the first active component, and the first end of the seventh active component Electrically connected to the first clock signal line, and the seventh active element The second end of the device is electrically connected to the output line. The display panel of claim 4, wherein each of the driving units further comprises: a first capacitor electrically connected to the output line and the first end of the first active component; and a second capacitor And electrically connected to the first clock signal line and the first end of the second active component. The display panel of claim 4, wherein the first active component, the fourth active component, the fifth active component, and the seventh active component in one of the driving units are along the gate lines The extending direction is disposed on the same horizontal line, and the second active component, the third active component, and the sixth active component are disposed on another identical horizontal line along the extending direction of the gate lines. The display panel of claim 1, wherein the pixel units comprise a first data line, a second data line, a third data line, a first gate line, and a second a gate line and first to sixth sub-pixels, wherein the first sub-pixel is electrically connected to the first gate line and the first data line, respectively, the second sub-pixel and the first gate respectively The second sub-pixel is electrically connected to the second gate line and the first data line, and the fourth sub-pixel and the first gate line are respectively electrically connected And the third data line is electrically connected, the fifth sub-pixel is electrically connected to the second gate line and the second data line, respectively, the sixth sub-pixel and the second gate line and the The third data line is electrically connected, wherein the second sub-pixel and the fifth sub-pixel are located between the first gate line and the second gate line, and the first sub-pixel, the second The sub-pixel and the third sub-pixel are located between the first data line and the second data line. The display panel of claim 7, wherein the pixel units further include a third gate line, a fourth gate line, and seventh to twelfth sub-pixels, and the The seventh sub-pixels are electrically connected to the third gate line and the second data line, and the eighth sub-pixel is electrically connected to the third gate line and the third data line, respectively, the ninth sub-pixel The pixels are electrically connected to the fourth gate line and the second data line, and the tenth sub-pixel is electrically connected to the third gate line and a fourth data line, respectively, the eleventh sub-picture The fourth sub-pixel is electrically connected to the fourth gate line and the fourth data line, respectively, wherein the eighth sub-picture is electrically connected to the fourth gate line and the fourth data line, wherein the eighth sub-picture And the eleventh sub-pixel is located between the third gate line and the fourth gate line, and the seventh sub-pixel, the eighth sub-pixel, and the ninth sub-pixel are located in the first Between a data line and the second data line. The display panel as described in claim 7 or 8, wherein the gate driving circuit comprises a plurality of active components and a plurality of signal lines, the active components being disposed between two adjacent pixel units The plurality of signal lines are disposed between two adjacent pixel units or between two adjacent sub-pixels. The display panel of claim 1, wherein the gate circuit comprises a first driving unit and a second driving unit, and the first driving unit and the second driving unit respectively have a plurality of active components. And the arrangement relationship between the active elements of the first driving unit is the same as the arrangement relationship between the active elements of the second driving unit. The display panel of claim 1, wherein the gate circuit comprises a first driving unit and a second driving unit, and the first driving unit and the second driving unit respectively have a plurality of active elements And the arrangement relationship between the active elements of the first driving unit and the arrangement relationship between the active elements of the second driving unit are mirror-symmetrical to each other.