JP2008040327A - Matrix type electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a matrix type electro-optical device capable of writing data into pixels within writing time even when wiring resistance and wiring capacity are increased, and minimizing the occupied area of an extension circuit in a panel. <P>SOLUTION: The matrix type electro-optical device comprises: a plurality of timing signal lines GWRT extended along a row direction X; a plurality of pixels 50, 52; a timing signal line driver 18 for supplying timing signals from one-ends of the plurality of timing signal lines; and a plurality of buffer circuits 30 which are respectively inserted and connected to the plurality of timing signals. Each of the plurality of timing signal lines is divided into N (N is an integer ≥3) divided timing signal lines GWRT1 to GWRTN and each of the plurality of buffer circuits 30 has (N-1) buffers 32 in total each of which is connected in series between two adjacent divided timing signal lines in the row direction out of N divided timing signals. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a matrix type electro-optical device in which pixels are arranged in a matrix.

  The FPD (Flat Panel Display) market is growing year by year because it is thinner than conventional displays. The size of the FPD has been increased, and 40-inch prototypes have been announced for OLED (Organic Light Emitting Display) following liquid crystal and plasma display.

  As the FPD becomes larger, the wiring distance in the panel becomes longer, signal propagation delay due to wiring resistance and wiring capacitance cannot be ignored, and data writing time to the pixel is shortened. Therefore, in a pixel at a distance away from the driver, a situation occurs in which data cannot be written within the data writing time.

  Conventionally, as a method for solving this type of problem, it is conceivable to form scanning lines and data signal lines with a material having good conductivity. However, it is awaiting the development of such materials and cannot be an essential solution.

  Next, there is a method of driving scanning lines and data signal lines from both sides of the panel. However, since the drivers are arranged on both sides, the circuit area increases, the panel cost increases, and the power consumption increases.

Furthermore, there is one that sequentially increases the writing time in accordance with the geometric distance from the driver (Patent Document 1). However, if the writing time itself is shortened due to an increase in the size of the panel, the increase in the writing time is also limited by itself.
JP 2004-325808 A

  An object of the present invention is to provide a matrix type electro-optical device capable of writing data to a pixel within a writing time even if wiring resistance and wiring capacity increase with an increase in the size of a panel.

  Another object of the present invention is to provide a matrix type electro-optical device that minimizes the area occupied by the additional circuit in the panel.

  The matrix type electro-optical device according to the present invention includes a plurality of rows of timing signal lines extending in the row direction, a plurality of columns of data signal lines extending in the column direction, and at least each of the plurality of rows of timing signal lines. A plurality of pixels connected to each one of the plurality of data signal lines and a timing signal line driver for supplying a timing signal from one end of the plurality of rows of timing signal lines, Each of the plurality of rows of timing signal lines, and each of the plurality of rows of timing signal lines includes a plurality of buffer circuits that are respectively inserted and connected to each of the plurality of rows of timing signal lines. Is divided into N (N is an integer greater than or equal to 3) divided timing signal lines, and each of the plurality of buffer circuits is adjacent in the row direction among the N divided timing signal lines. And having each two one by one serially connected meter between the (N-1) pieces of buffers.

  In the present invention, the timing signals propagated to each of the plurality of rows of timing signal lines are shaped by a total of (N−1) buffers that are connected in series. Therefore, the waveform rounding of the timing signal can be suppressed even at a position away from the timing signal line driver, and the luminance variation within the panel surface can be reduced.

In the present invention, the plurality of pixels include a plurality of pixel rows commonly connected to each one of the plurality of rows of timing signal lines, and each of the plurality of pixel rows is divided into N row blocks,
The timing signal line driver side is adjacent to the K-th row block in the row direction counting from the timing signal line driver side (K is an integer satisfying 1 ≦ K ≦ N−1) in the column direction. And the Kth buffer is arranged in the row direction.

  In this case, the buffer does not have to be arranged at a position adjacent to the Nth row block in the row direction and counted in the column direction from the timing signal line driver, and the buffer is saved in a space-saving pixel. Can be placed close to.

  In the present invention, the total number of the timing signal lines in the plurality of rows is an even number, and when each of the two pixel rows adjacent in the column direction is an inter-pixel row region, each of the buffer circuits among the plurality of buffer circuits. Each of the two buffer circuits corresponding to the two pixel rows can be arranged in common in the odd-numbered inter-pixel row region. Thereby, the buffers can be arranged in a concentrated manner by effectively using the odd-numbered pixel row regions.

  In the present invention, in each of the two buffer circuits arranged in the odd-numbered inter-pixel row region, (N−1) buffers can be arranged in the same row. This can suppress an increase in circuit area in the column direction. Preferably, each of the (N-1) buffers includes a plurality of transistors, and all the transistors constituting the (N-1) buffers are arranged in the same row. You can also. In this way, the buffer can be arranged in a space of one transistor in the column direction.

  In the present invention, each of the (N−1) buffers includes a plurality of transistors, and the plurality of transistors constituting the (N−1) buffers are positioned in the column direction. You may arrange | position over two different lines. In this way, the buffer can be arranged in a space for two transistors in the column direction.

  In the present invention, each of the plurality of pixels may include a write transistor connected to one of the plurality of columns of data signal lines and selected by one of the plurality of rows of timing signal lines. That is, it is suitable for an active electro-optical device, but the present invention can also be applied to a passive matrix electro-optical device. This is because the timing signal delay problem is common to not only the active matrix type but also the passive matrix type.

  In the present invention, each of the plurality of pixels is connected to a light emitting element, a driving transistor connected to a power supply line to control a current flowing in the light emitting element, the writing transistor, and the driving transistor. And a storage capacitor for holding a gate voltage. That is, it is suitable for a voltage programming light emitting device.

  In the present invention, the plurality of transistors, the write transistor, and the drive transistor constituting the (N-1) buffers can be formed of the same conductivity type transistor. In this way, the well structure is shared between the buffer region and the pixel region, and a space-saving design is possible.

  In the present invention, each of the plurality of rows of timing signal lines includes first to Mth timing signal lines (M is an integer of 2 or more), and each pixel arranged in the pixel row includes 1st to Mth timing signal lines are commonly connected, and each of the first to Mth timing signal lines has the N divided timing lines divided at different positions in the row direction. , Out of the N divided timing signal lines, a total of (N−1) buffers can be provided, each connected in series between each two adjacent in the row direction. That is, the timing signal line is not limited to one type.

  In the present invention, the first timing signal line is a scanning signal line, the second timing signal line is a threshold compensation control signal line, and the Mth timing signal line is a light emission control signal line. Each of the plurality of pixels is connected to a light emitting element, one of the plurality of columns of data signal lines, a write transistor selected by one of the plurality of rows of timing signal lines, and a power supply line. A driving transistor for controlling a current flowing through the light emitting element, a holding capacitor connected to the writing transistor and the driving transistor and holding a gate voltage of the driving transistor, and the threshold compensation control signal line. A compensation transistor for diode-connecting the drive transistor and a light-emitting element connected in series, It may include an operation to be the light emission control transistor. As an example having a plurality of timing signal lines, a light emitting device capable of compensating a threshold value of a driving transistor can be given.

  In the present invention, a power supply line for supplying a power supply voltage to the plurality of buffer circuits is provided, and the power supply line connected to the drive transistor can also be used as the power supply line. In this way, the power supply line routed to the pixel region can be omitted, and a space-saving design is possible.

  In the present invention, each one of the plurality of pixels is configured by at least three sub-pixels that realize color gradation, and each of the at least three sub-pixels includes one of the plurality of rows of timing signal lines and the plurality of timing signal lines. Connected to one of the data signal lines in a plurality of columns, the three sub-pixels are arranged in different columns along the column direction, and the same color is arranged at intervals in the row direction. A stripe arrangement can be used.

  In this case, the one pixel is composed of four sub-pixels, and each of the (N−1) buffers includes four transistors, and each one of the four transistors includes one of the four sub-pixels. You may arrange | position in the position adjacent to the said row direction with respect to each one. In this way, the timing signal can be buffered for each pixel.

  In the present invention, the color gradation can be realized not only in the stripe arrangement but also in the delta arrangement or the mosaic arrangement. In any case, each of the plurality of transistors included in each of the (N−1) buffers can be disposed at a position facing one subpixel in the column direction.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention. In the following drawings, the same reference numerals have the same meaning.

(Principle of the present invention)
FIG. 1 is a configuration diagram of an OLED (Organic Light Emitting Display) to which the present invention is applied. When a video signal is input, the main control circuit 10 controls video data to the data driver control circuit 12 and gate driver control. A timing signal is transmitted to the circuit 16. The data driver control circuit 12 controls driving of the data driver 14 based on the video data, and the gate driver control circuit 16 controls driving of the gate driver 18 based on the timing signal.

  The organic EL panel 20 is provided with a plurality of rows of gate lines (timing signal lines in a broad sense) 22 extending along the row direction X and a plurality of columns of data signal lines 24 extending along the column direction Y. A pixel 26 connected to each one of the plurality of rows of gate lines 22 and each of the plurality of columns of data signal lines 24 is provided.

  In FIG. 1, a timing signal (gate signal or scanning signal) is transmitted from the gate driver 18 at the left end of the panel 20, and the timing signal input from the left end of the panel 20 propagates through the gate line 22 and reaches the right end of the panel 20. To do.

  Here, one gate line 22 shown in FIG. 1 can be shown as an equivalent circuit shown in FIG. For example, in the large-sized panel 20 of 30 inch class, although depending on the panel specifications such as the thickness and material of the gate line 22, as shown in FIG. 2, an RC circuit (20 Next, the wiring resistance R of the gate line 22 is typically 20 kΩ, and the wiring capacitance C is 140 pF.

  In the RC circuit (20th order) shown in FIG. 2, how much the waveform changes was simulated. The input waveform was a rectangular wave with an amplitude of 15 V and a period of 16 μm.

  FIG. 3 shows the simulation result. It can be seen that the input waveform is a rectangular wave, but the rounding of the waveform increases as the number of RC stages becomes higher. Table 1 below shows the ratio of the pulse width of 90% (13.5 V) or more at each stage to the input waveform.

  As is clear from Table 1, it can be seen that the section with a pulse width of 90% or more is shorter in the later stage. Due to such a wiring delay of the gate line 22, the writing time is insufficient and the luminance variation in the panel surface is caused accordingly.

  In the present invention, a buffer circuit 30 is inserted in the gate line 22 as shown in FIG. In FIG. 4, a total of 19 buffers 32 are connected in series to the gate line 22, one buffer 32 between each stage of the 20-stage RC circuit.

  Next, the result of simulating the rounding of the waveform in the circuit of FIG. 4 in the same manner as FIG. 3 is shown in FIG. As is apparent from FIG. 5, the waveform at each stage is almost similar to the rectangular wave that is the input wave, and it is understood that the waveform rounding is small even at the final stage. Table 2 below shows the ratio of the pulse width of 90% (13.5 V) or more at each stage with respect to the input waveform in the circuit of FIG. 4 in comparison with the results in Table 1.

  Thus, it has been found that by inserting the buffer circuit 30 into the gate line 22, the pulse width period of 90% or more is improved by nearly 30% at the RC stage of the final stage.

  As described above, in the present invention, it was confirmed that insertion of the buffer circuit 30 in the gate line 22 improves the rounding of the timing signal waveform and the variation in the timing signal waveform within the panel 20. Hereinafter, the arrangement of the buffer circuit 30 will be described.

(First embodiment)
In the present embodiment, as shown in FIG. 6, one pixel 26 is formed of R (Red), G (Green), and B (Blue) sub-pixels 26 R, 26 G, and 26 B adjacent in the row direction X. This is applied to the organic EL panel 20 having a so-called stripe-type color filter 40 in which the respective colors R, G, B corresponding to the RGB sub-pixels 26R, 26G, 26B are arranged along the column direction Y.

  FIG. 7 shows the first and second pixel rows 50 and 52 connected to the two gate lines GWRT connected to the gate driver 18 in the panel 20 shown in FIG. Each of the first and second pixel rows 50 and 52 is divided into N (N is an integer of 3 or more) row blocks 1 to N. Each row block has 12 sub-pixels (= 4 pixels) in this embodiment.

  Each of the two gate lines GWRT connected to the first and second pixel rows 50 and 52 corresponds to N divided gate lines (divided scanning lines in a broad sense) GWRT1 corresponding to N row blocks. Divided into GWRTN. In each of the first and second pixel rows 50 and 52, one buffer circuit 30 is connected in series between each two adjacent N rows of gate lines GWRT <b> 1 to GWRTN in the row direction X. A total of (N-1) buffers 32-1, 32-2,..., 32- (N-1) are connected.

  In the present embodiment, at a position adjacent to the row block K arranged in the row direction X in the row direction X (K is an integer satisfying 1 ≦ K ≦ N−1) in the column direction Y from the gate driver 18 side. The K-th buffer 32-K is arranged in the row direction X from the gate driver 18 side, and in the column direction Y with the row block N arranged in the row direction N from the gate driver 18 side. In adjacent positions, no buffer is arranged. This is because the K-th buffer 32-K is arranged on the upstream side of the gate driver 18 with respect to the (K + 1) -th row block (K + 1), thereby improving the wiring efficiency. Unless there is a particular reason, the same number (12 in the present embodiment) of sub-pixels can be arranged in the row block 1 to the row block (N−1) except the last row block N. When the total number of sub-pixels in the direction is not divisible by the number N of row blocks, the number of sub-pixels arranged in the last row block N is reduced. Therefore, the space at the position facing the last row block N in the column direction Y may become narrow, and it is not always possible to secure a space in which the buffer 32 can be arranged. For this reason as well, the buffer 32 is not disposed at a position facing the last row block N in the column direction Y.

  FIG. 8 shows the row block 1 of the first pixel row 50 shown in FIG. Each of the sub-pixels 26R, 26G, and 26B constituting one pixel 26 has a voltage programming type two-transistor configuration. In other words, each subpixel is connected to the organic EL element (light-emitting element in a broad sense) EL and the data signal line VDT, and the writing is made of, for example, an N-type transistor selected by connecting the gate to the divided gate line GWRT1 in common. The current flowing through the organic EL element EL connected to the transistor T1 and the power supply line VEL is controlled. For example, it has a drive transistor T2 made of a P-type transistor and a storage capacitor C that holds the gate voltage of the drive transistor T2.

  On the other hand, the buffer 32-1 is composed of two CMOS inverters CMOS1 and CMOS2. The CMOS inverter CMOS1 has a P-type transistor 60 and an N-type transistor 62 connected in series between the inverter power supply line VBF and the ground power supply line GND. Similarly, the CMOS inverter CMOS2 includes a P-type transistor 64 and an N-type transistor 66 connected in series between the inverter power supply line VBF and the ground power supply line GND.

  Here, the four transistors 60-66 constituting the buffer 32-1 are aligned in the same row at a position facing the row block 1 of the first pixel row 50 in the column direction Y. In the first pixel row 50, the buffers 32-2 to 32- (N-1) are similarly arranged in the other row blocks 1 to (N-1). That is, each of the four transistors 60-66 constituting the buffers 32-1 to 32- (N-1) is arranged in the same row. For this reason, since the buffer circuit 30 added in each pixel row only needs to have an area for one transistor in the column direction Y, the buffer circuit 30 is not necessarily increased in area. Can be added.

  9A to 9C show the positional relationship between the four transistors 60-66 and the row block 1 constituting the buffer 32-1. FIG. 9A shows the same layout as FIG. 8, the transistor 60 is the G sub-pixel of the first pixel, the transistor 62 is the B sub-pixel of the first pixel, the transistor 64 is the G sub-pixel of the second pixel, and the transistor 66 is arranged at a position adjacent to the B sub-pixel of the second pixel in the column direction Y, respectively. Not limited to this, the relationship between the four transistors 60-66 and each sub-pixel is arbitrary. In FIG. 9B, four transistors 60-66 are arranged in a left-aligned manner adjacent to the three RGB subpixels of the first pixel and the R subpixel of the second pixel. In FIG. 9C, four transistors 60-66 are arranged at regular intervals in a region adjacent to the row block 1 in the column direction Y.

  9D differs from FIGS. 9A to 9C in that the four transistors 60-66 included in the buffer 32-1 are arranged across two rows whose positions are different in the column direction. ing. In FIG. 9D, the transistors 60 and 62 are arranged at different positions in the column direction Y, and the transistors 64 and 66 are arranged in the same row as the transistors 62. If there is enough space in the panel 20, the arrangement shown in FIG.

  Further, the number of sub-pixels arranged in one row block is not limited to twelve. As long as a space for arranging a buffer circuit in an area adjacent to one row block in the Y direction can be secured, the number is Can be set arbitrarily.

(Second Embodiment)
The total number of gate lines connected to the gate driver 18 is generally an even number. In the second embodiment, as shown in FIG. 10, between two pixel rows adjacent in the column direction Y (five pixel rows 50, 52, 54, 56, and 58 in FIG. 10). When the region 70 is used, each of the two buffer circuits 30 used for each of the two pixel rows is arranged in common to the odd-numbered inter-pixel row regions 70-1 and 70-3. That is, it is not necessary to arrange the buffer circuit 30 in the even-numbered pixel row regions 70-2, 70-4,.

  In the present embodiment, the number of subpixels arranged in one row block is, for example, 18 (for 6 pixels). Also in this case, a buffer 32 is provided to face one row block, and four transistors constituting the buffer 32 are arranged. When each of the four transistors 60 to 66 is arranged adjacent to one subpixel in the column direction Y, an empty space remains in an area adjacent to one row block in the Y direction. Using this empty space, a buffer 32 for a row block of another pixel row adjacent in the column direction Y is arranged. Therefore, in the present embodiment, each of the two buffer circuits 30 arranged in the odd-numbered inter-pixel row region can arrange (N−1) buffers 32 in the same row. More specifically, each (N-1) buffer 32 includes a plurality of, for example, four transistors 60-66, and all the transistors constituting each (N-1) buffer 32 are arranged in the same row. Can be aligned.

  In this way, even if the number of sub-pixels in one row block is increased, a buffer for two row blocks adjacent in the column direction Y to the odd-numbered pixel row inter-regions 70-1, 70-3,. 32 can be arranged, so that the transistors forming the buffer 32 can be arranged relatively densely. Therefore, manufacturing variations of transistors can be reduced.

  In the second embodiment, as shown in FIG. 9D described above, four transistors 60-66 constituting one buffer 32-1 are arranged over two rows having different positions in the column direction Y. It is suitable for things. In this case, as shown in FIG. 11, each row block 1 of the first and second pixel rows 50 and 52 adjacent in the column direction Y is different in the column direction Y of the inter-pixel row region 70-1. Each of the four transistors 60-66 is arranged in a row. That is, the transistors 62 to 66 connected to the first pixel row 50 and the transistors 60 connected to the second pixel row 52 are arranged in the first row. Transistors 60 connected to the first pixel row 50 and transistors 62 to 66 connected to the second pixel row 52 are arranged in the second row. In this way, the inter-pixel row region 70-1 can be used effectively.

(Third embodiment)
In the third embodiment, as shown in FIG. 12, four sub-pixels of R (Red), G (Green), B (Blue), and W (White) in which one pixel 26 is adjacent in the row direction X are used. 26R, 26G, 26B, 26W, and so-called striped color in which the colors R, G, B, W corresponding to the RGBW sub-pixels 26R, 26G, 26B, 26W are arranged in the column direction Y This is applied to the organic EL panel 20 having the filter 70.

  In this case, the number of subpixels 4 constituting one pixel 26 matches the number of transistors 4 constituting the buffer 32. Therefore, as shown in FIG. 13, each of the four transistors 60 to 66 constituting the buffer 32 is arranged in the column direction Y with respect to each of the four subpixels 26R, 26G, 26B, and 26W. It can arrange | position to an adjacent position. That is, the buffer 32 can be configured in a region adjacent to one pixel 26 in the column direction Y. In this way, the buffer 32 can be connected for each pixel 26 at the maximum.

  In addition, as another example in which one pixel 26 is configured by four sub-pixels, in particular, when the present invention is applied to a liquid crystal device, one using four-color sub-pixels in which cyan is added to three colors of RGB is cited. Can do.

(Fourth embodiment)
In FIG. 14, unlike the first to third embodiments, one pixel 80 has a four-transistor configuration that can perform Vth compensation. That is, in one sub-pixel 80, in addition to the organic EL element EL, the write transistor T1, the drive transistor T2, and the storage capacitor C shown in FIG. It has a transistor T4. The compensation transistor T3 is turned on in a threshold compensation period (for example, one horizontal scanning period before the writing period) for compensating for a variation in the threshold voltage Vth of the drive transistor T2, and the drive transistor T2 is turned on by the on-state. The diode is connected, and the gate voltage of the drive transistor T2 (charge voltage of the storage capacitor C) is converged to a voltage value (VEL−Vth) reflecting the threshold voltage Vth of the drive transistor T2. In the write period after the compensation transistor T3 is turned off, the write transistor T1 is turned on, and the charge voltage of the storage capacitor C is shifted by the data voltage from the data signal line VDT. When the write transistor T1 is turned off and the light emission control transistor T4 is turned on, the drive transistor T2 having the storage capacitor C connected to the gate passes a current controlled according to the data voltage to the organic EL element EL, and the organic EL element EL emits light. Is done.

  In such a sub-pixel 80, in addition to the gate line GWRT described above, a threshold compensation control signal line GVTH connected to the gate of the compensation transistor T3, and a light emission control signal connected to the gate of the light emission control transistor T4. Line GEL is required. Since the threshold compensation control signal line GVTH and the light emission control signal line GEL are commonly connected to one pixel row in the same manner as the gate line GWRT, a signal propagation delay occurs as in the gate line GWRT.

  Therefore, in the present embodiment, as shown in FIG. 15, the threshold compensation control signal line GVTH is divided into the divided threshold compensation control signal line GVTH1, as in the case where the gate line GWRT is divided into the divided gate lines GWRT1-GWRTN. , GVTH2,..., And the emission control signal line GEL is also divided into divided emission control signal lines GEL1, GEL2,. Then, buffers 34-1, 34-2,... Are arranged between two divided threshold compensation control signal lines (for example, GVTH1, GVTH2) adjacent in the row direction X. Similarly, buffers 36-1, 36-2,... Are arranged between two divided light emission control signal lines (for example, GEL1, GEL2) adjacent in the row direction X.

  In this embodiment, as shown in FIG. 15, for example, 6 sub-pixels (2 pixels) are referred to as a row unit block 90, and three buffers are provided in an area adjacent to each of the three row unit blocks 90 in the column direction Y. 32-1, 34-1 and 36-1 are arranged. In FIG. 15, a buffer 34-1 for the gate line GWRT is arranged in a region adjacent to the first row unit block 90-1 located on the gate driver 18 side in the column direction Y. In a region adjacent to the second row unit block 90-2 in the column direction Y, a buffer 34-1 for the threshold compensation control signal line GVTH is disposed. In the region adjacent to the third row unit block 90-3 in the column direction Y, a buffer 36-1 for the light emission control signal line GEL is arranged. Thereafter, the buffers 32, 34, and 36 are arranged in the order of the buffers 32, 34, and 36 in correspondence with the subsequent row unit block 90.

  For this reason, the gate line GWRT, the threshold compensation control signal line GVTH, and the light emission control signal line GEL have different division positions. This will be described based on the difference in position at which the pixel row 50 is made into a row block every three timing control lines. That is, the row blocking of the pixel row 50 is different for each gate line GWRT, threshold compensation control signal line GVTH, and light emission control signal line GEL. The gate line GWRT, the threshold compensation control signal line GVTH, and the light emission control signal line GEL are divided between the row blocks unique to the gate line GWRT, the threshold compensation control signal line GVTH, and the light emission control signal line GEL, respectively. Has been.

  First, as shown in FIG. 15, the first row unit block 90-1 is divided into the first row block 1 and the second to fourth row unit blocks 90-2. ˜90-4 becomes the second row unit block 2, and thereafter, three row unit blocks are grouped into a set.

  Next, as shown in FIG. 15, the first and second row unit blocks 90-1 and 90-2 are arranged in the first row block 1 as shown in FIG. The third to sixth row unit blocks 90-3 to 90-6 become the second row unit block 2, and thereafter, the three row unit blocks are grouped into a set.

  Finally, in the row blocking of the pixel row 50 with respect to the light emission control signal line GEL, the first to third row unit blocks 90-1 to 90-3 are the first row block 1, as shown in FIG. Thereafter, the block is divided into a set of three row unit blocks.

  Note that none of the buffers 32, 34, 36 is arranged in the last row block N in the pixel row 50 as described above.

  Also in this embodiment, the forms shown in FIGS. 6 and 9A to 12 can be applied.

(Fifth embodiment)
The fifth embodiment is a modification of the first to fourth embodiments. FIG. 16 shows a modification of FIG. In FIG. 16, the power supply line VBF connected to the drive transistor T2 is also used as the power supply line VBF for the plurality of buffers 32 configuring the buffer circuit 30 shown in FIG. That is, in FIG. 16, voltage VEL = voltage VBF. Thereby, the number of power supply lines supplied to the pixels and buffers can be greatly reduced. In order to turn on the P-type transistor 60, voltage VBF> voltage GWRT may be satisfied.

  Further, in FIG. 16, the ground power supply wiring GND connected to the buffer 32 shown in FIG. 8 is also omitted, and instead connected to the counter substrate potential GND connected to the organic EL element EL. As a result, the ground power supply wiring GND need not be routed along the column direction Y in the pixel formation region as shown in FIG. Note that the embodiment of FIG. 16 can be similarly applied to an embodiment in which one pixel has four transistors as shown in FIG.

  FIG. 17 is a modification of the buffer 32 shown in FIG. One CMOS inverter CMOS1 constituting the buffer 32 shown in FIG. 17 includes a resistor R1 and an N-type transistor 68 connected in series between the power supply line VBF and the ground power supply line GND, and the other CMOS inverter CMOS2 includes The resistor R2 and the N-type transistor 69 are connected in series between the power supply line VBF and the ground power supply line GND. That is, no P-type transistor is used. Further, in FIG. 17, a write transistor T1, a drive transistor T2, and a reset transistor T3 are arranged in each subpixel 100, and these three transistors T1 to T3 are also formed by N-type transistors. Therefore, all the transistors included in the buffer 32 and the subpixel 100 can be formed with the same conductivity type. As a result, the well structure of the buffer 32 and the sub-pixel 100 is simplified, and a space-saving design is possible. The embodiment shown in FIG. 17 can be similarly applied to an embodiment in which one subpixel has a two-transistor configuration or a four-transistor configuration as shown in FIG.

  FIG. 18 shows a modification of FIG. In FIG. 18, the arrangement of the four transistors 60 to 66 constituting the buffer 32 is changed. That is, the P-type transistors 60 and 64 are arranged adjacent to each other in the row direction X, and the N-type transistors 62 and 66 are arranged adjacent to each other in the row direction X. In this way, transistors of the same conductivity type are arranged adjacent to each other, so that a common power supply line can be used between the transistors of the same conductivity type. However, compared with FIG. 8, the amount of wiring routed in the row direction X direction in the buffer 32 increases.

  FIG. 19 shows a color filter 110 different from FIG. In FIG. 19, three RGB sub-pixels 26R, 26G, and 26B constituting one pixel 26 are arranged in two adjacent pixel rows in the column direction Y, and three sub-pixels 26R, 26G, and 26B are triangular. It is located at the apex of The color filter 110 has a delta arrangement in which the three primary colors are arranged at positions facing the vertexes of the triangle.

  FIG. 20 shows the filter 120 because it is further different from FIGS. The three RGB sub-pixels 26R, 26G, and 26B constituting one pixel 26 are arranged in two adjacent pixel rows in the column direction Y, and the three sub-pixels 26R, 26G, and 26B are on two right angles. positioned. The color filter 120 has a mosaic arrangement in which the three primary colors are arranged at positions facing the two right-angled sides.

  The color filters 110 and 120 shown in FIGS. 19 and 20 can be used in the above-described embodiments in place of the stripe-arranged color filter 40 shown in FIG. 6, but the embodiments shown in FIGS. Is not applicable.

  As described above, the embodiments of the present invention have been described in detail. However, those skilled in the art can easily understand that many modifications can be made without departing from the novel matters and effects of the present invention. . Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term anywhere in the specification or the drawings.

  For example, according to the present invention, as shown in FIG. 5, a rectangular wave as a timing signal, which is a buffer output, causes a phase delay toward the later stage. Therefore, the supply timing of the data signal output from the data driver 14 can be delayed in accordance with the phase delay of the rectangular wave.

  The matrix type electro-optical device to which the present invention is applied is not limited to the above-described OELD, but can be applied to other various liquid crystal devices such as FPDs, plasma displays, micromirror devices, and the like. Or a light valve. Similarly to the above-described OELD, the liquid crystal device can be applied to an active matrix liquid crystal device having a switching element such as a writing transistor (pixel selection transistor) or a diode, a storage capacitor, and a liquid crystal element in each pixel. The present invention can also be applied to a passive matrix type electro-optical device.

  Furthermore, it goes without saying that the buffer circuit used in the present invention can be replaced by other known buffer circuits in addition to the above-described pair of CMOS inverters or transistors in which one of the transistors is replaced by a resistor.

  In addition, in order to realize color gradation with organic EL, in addition to the case where a single color light source is used to produce a three color light source using a color filter as described above, a known three color coating method (materials for all three colors) is used. You can also.

It is a figure which shows FPD of organic EL to which this invention is applied. It is RC equivalent circuit schematic of the gate line shown in FIG. It is a characteristic view which shows the delay simulation of RC circuit in the comparative example which does not have a buffer circuit. It is RC equivalent circuit schematic which shows the principle of this invention which provided the buffer circuit. It is a characteristic view which shows RC delay simulation which concerns on embodiment of this invention which has a buffer circuit. It is a figure which shows the RGB stripe type color filter to which this invention is applied. It is a circuit diagram which shows the connection of the buffer circuit which concerns on the 1st Embodiment of this invention. It is a figure which shows the connection state of the buffer connected to the 1st row block shown in FIG. FIG. 9A to FIG. 9D are diagrams illustrating a transistor arrangement example of a buffer connected to the first row block. FIG. 10 is a diagram showing a second embodiment of the present invention, in which transistors constituting each buffer for the first and second pixel rows are commonly arranged in an odd-numbered inter-pixel row region. It is the figure which has arrange | positioned the transistor to two rows which differ in a column direction in the area between odd-numbered pixel rows. It is a figure which shows the RGBW stripe type color filter used for the 1st Embodiment of this invention. FIG. 4 is a diagram in which each one of four transistors constituting one buffer is adjacent to each of four sub-pixels constituting one pixel in the column direction. It is a circuit diagram which shows the 3rd Embodiment of this invention applied to the pixel which has a 4 transistor structure which can perform Vth compensation. FIG. 15 is a diagram showing buffer connections for the three timing signal lines shown in FIG. 14. FIG. 9 is a diagram illustrating a modification of the embodiment of FIG. 8 and illustrating an embodiment in which a pixel driving power source is also used as a buffer power source. It is a figure which shows the modification of embodiment of FIG. 14, and shows embodiment which comprised the buffer with two transistors. It is a figure which shows the further modification of embodiment of FIG. 8, and shows embodiment which changed arrangement | positioning of 4 transistors which comprise a buffer. It is a figure which shows the color filter of a delta arrangement | sequence. It is a figure which shows the color filter of a mosaic arrangement | sequence.

Explanation of symbols

10 main control circuit, 12 data driver control circuit, 14 data driver,
16 gate driver control circuit, 18 gate driver (scan line driver),
20 panels, 22 gate lines (scanning lines), 24 data signal lines, 26 pixels,
30 buffer circuit, 32, 32-1, ... 32- (N-1) buffer,
40 RGB stripe color filter, 50,52 pixel rows,
60-69 transistor, 70 pixel inter-line region,
70-1, 70-3 odd-numbered inter-pixel row regions,
70-2, 70-4 Even-numbered pixel row area,
26R, 26G, 26B, 26W, 80, 100 subpixels, 90 row unit block,
110 delta color filter, 120 mosaic color filter,
C holding capacitor, CMO1, 2 CMOS inverter, EL organic EL element,
T1 write transistor, T2 drive transistor, T3 compensation transistor,
T4 light emission control transistor,
GWRT gate line (timing signal line, first timing signal line),
GVTH threshold compensation control signal line (second timing signal line),
GEL light emission control signal line (Mth timing signal line),
VDT data signal line, VEL power supply line, VBF power supply line

Claims (17)

Multiple rows of timing signal lines extending along the row direction;
A plurality of columns of data signal lines extending along the column direction;
A plurality of pixels each connected to at least one of the plurality of rows of timing signal lines and each of the plurality of columns of data signal lines;
A timing signal line driver for supplying a timing signal from one end of the plurality of rows of timing signal lines;
A plurality of buffer circuits each inserted and connected to one of each of the plurality of rows of timing signal lines, and provided one by one to each of the plurality of rows of timing signal lines;
Have
Each of the plurality of rows of timing signal lines is divided into N (N is an integer of 3 or more) divided timing signal lines,
Each of the plurality of buffer circuits has a total of (N−1) buffers connected in series between two of the N divided timing signal lines adjacent to each other in the row direction. A matrix type electro-optical device. In claim 1,
The plurality of pixels include a plurality of pixel rows commonly connected to each one of the plurality of rows of timing signal lines, and each of the plurality of pixel rows is divided into N row blocks,
From the timing signal line driver side to a position adjacent to the K-th row block in the row direction counting from the timing signal line driver side (K is an integer satisfying 1 ≦ K ≦ N−1) in the column direction. The Kth buffer is arranged in the row direction, and the buffer is not arranged in a position adjacent to the Nth row block in the row direction in the column direction counted from the timing signal line driver. A matrix type electro-optical device. In claim 2,
The total number of the timing signal lines in the plurality of rows is an even number,
When a region between two pixel rows adjacent in the column direction is an inter-pixel row region,
Of the plurality of buffer circuits, each of the two buffer circuits corresponding to each of the two pixel rows is commonly disposed in an odd-numbered inter-pixel row region. In claim 3,
Each of the two buffer circuits arranged in the odd-numbered inter-pixel row region has (N-1) buffers arranged in the same row. In claim 4,
Each of the (N-1) buffers includes a plurality of transistors, and all the transistors constituting the (N-1) buffers are arranged in the same row. Matrix type electro-optical device. In claim 4,
Each of the (N-1) buffers includes a plurality of transistors, and the plurality of transistors constituting the (N-1) buffers are arranged in two rows having different positions in the column direction. A matrix type electro-optical device characterized by being arranged over the entire surface. In any one of Claims 1 thru | or 6.
Each of the plurality of pixels includes a writing transistor connected to one of the plurality of columns of data signal lines and selected by one of the plurality of rows of timing signal lines. . In claim 7,
Each of the plurality of pixels is
A light emitting element;
A driving transistor connected to a power supply line to control a current flowing through the light emitting element;
A storage capacitor connected to the write transistor and the drive transistor and holding a gate voltage of the drive transistor;
The matrix type electro-optical device further comprising: In claim 8,
The matrix type electro-optical device, wherein the plurality of transistors, the writing transistor, and the driving transistor constituting the (N-1) buffers are all formed of the same conductivity type transistor. In any one of Claims 1 thru | or 6.
Each of the plurality of rows of timing signal lines includes first to Mth (M is an integer of 2 or more) timing signal lines,
The first to Mth timing signal lines are commonly connected to each pixel arranged in the pixel row,
Each of the first to M-th timing signal lines includes the N divided timing lines divided at different positions in the row direction, and the row of the N divided timing signal lines. A matrix type electro-optical device comprising a total of (N-1) buffers connected in series between each two adjacent in the direction. In claim 10,
The first timing signal line is a scanning signal line, the second timing signal line is a threshold compensation control signal line, the Mth timing signal line is a light emission control signal line,
Each of the plurality of pixels is
A light emitting element;
A write transistor connected to one of the plurality of columns of data signal lines and selected by one of the plurality of rows of timing signal lines;
A driving transistor connected to a power supply line to control a current flowing through the light emitting element;
A storage capacitor connected to the write transistor and the drive transistor and holding a gate voltage of the drive transistor;
A compensation transistor that is turned on by the threshold compensation control signal line to diode-connect the drive transistor;
A light emission control transistor connected in series with the light emitting element and turned on by the light emission control signal line;
A matrix type electro-optical device. In claim 8, 9 or 11,
A matrix type electro-optical device, wherein a power supply line for supplying a power supply voltage to the plurality of buffer circuits is provided, and the power supply line connected to the driving transistor is also used as the power supply line. In any one of Claims 1 to 12,
Each pixel of the plurality of pixels includes at least three sub-pixels that realize color gradation, and each of the at least three sub-pixels includes one of the plurality of rows of timing signal lines and the plurality of columns of data. Connected to one of the signal lines,
The matrix type, wherein the three sub-pixels are arranged in different columns along the column direction and the same color is arranged in the row direction with an interval. Electro-optic device. In any one of Claims 1 to 12,
Each pixel of the plurality of pixels includes three sub-pixels that realize color gradation, and the three sub-pixels are one of the plurality of rows of timing signal lines and one of the plurality of columns of data signal lines. Connected to the book,
The matrix type electro-optical device, wherein the three sub-pixels arranged in two pixel rows adjacent in the column direction have a delta arrangement arranged at a vertex of a triangle. In any one of Claims 1 to 12,
Each pixel of the plurality of pixels includes three sub-pixels that realize color gradation, and the three sub-pixels are one of the plurality of rows of timing signal lines and one of the plurality of columns of data signal lines. Connected to the book,
The matrix type electro-optical device, wherein the three sub-pixels arranged in two pixel rows adjacent in the column direction have a mosaic arrangement arranged on two right-angled sides. In any of claims 13 to 15,
Each of the plurality of transistors included in each of the (N-1) buffers is arranged at a position facing one sub-pixel in the column direction. apparatus. In claim 13,
The one pixel is composed of four sub-pixels,
Each of the (N-1) buffers includes four transistors;
Each of the four transistors is disposed at a position adjacent to each of the four sub-pixels in the column direction.

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