CN109192125B - Array substrate - Google Patents
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- CN109192125B CN109192125B CN201811176911.4A CN201811176911A CN109192125B CN 109192125 B CN109192125 B CN 109192125B CN 201811176911 A CN201811176911 A CN 201811176911A CN 109192125 B CN109192125 B CN 109192125B
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- array substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
Abstract
The invention discloses an array substrate which comprises a display area and a peripheral area. The display area comprises a first display area and a second display area, and further comprises a first scanning driving circuit, a second scanning driving circuit and a plurality of pixel units. The first scanning driving circuit is arranged in the first display area, the second scanning driving circuit is arranged in the peripheral area, and the plurality of pixel units comprise a first group of pixel units and a second group of pixel units. The first group of pixel units are arranged in the first display area, and the second group of pixel units are arranged in the second display area; the first scanning driving circuit is electrically connected to the first group of pixel units, and the second scanning driving circuit is electrically connected to the second group of pixel units.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate.
Background
The display technology is widely applied to the fields of televisions, mobile phones and the like, generally, a source driving chip in a display panel is responsible for receiving image data, caching the image data and converting a digital signal into an analog signal, and finally, the converted signal is transmitted to each data line of the display panel through an output buffer, a scanning driving circuit is responsible for realizing line-by-line scanning, scanning signals which are opened line by line are generated aiming at time sequence control, a pixel switch is controlled to be opened after the scanning signals of each line are loaded to a corresponding gate line, so that the image data enters a storage capacitor of the line of pixels, and finally, the normal display of the image is realized. Currently, the scan driving circuit composed of thin film transistors is generally disposed in the peripheral areas of the left and right sides of the display panel.
With the continuous development of display technology, the display panel not only has higher and higher requirements on display functions, but also gradually increases the requirements on the appearance in order to better adapt to the overall structure and the use requirements of the environment, so that the special-shaped display panel is generated. In short, the special-shaped display panel is a rectangular display panel with cut-away portions (including corner cuts, arc-shaped grooves, etc.) for placing parts such as a camera and a receiver. In order to ensure the display effect of the special-shaped display panel, the existing design avoids the cutting area, and pixel units, driving circuits, gate lines, data lines and the like of the array substrate are rearranged, so that the cost is increased, a large amount of time is consumed, and the market competitiveness is directly influenced.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a special-shaped array substrate capable of sharing a mask with a rectangular array substrate, which not only reduces the cost of design layout, but also directly reduces the time of design layout.
In order to achieve the above object, an array substrate according to an embodiment of the present invention includes a display area and a peripheral area, wherein the display area includes a first display area and a second display area, and further includes a first scan driving circuit, a second scan driving circuit and a plurality of pixel units, the first scan driving circuit is disposed in the first display area, the second scan driving circuit is disposed in the peripheral area, the plurality of pixel units includes a first group of pixel units and a second group of pixel units, the first group of pixel units is disposed in the first display area, and the second group of pixel units is disposed in the second display area; the first scanning driving circuit is electrically connected to the first group of pixel units, and the second scanning driving circuit is electrically connected to the second group of pixel units.
In an embodiment of the array substrate, the display panel further includes a third scan driving circuit disposed in a partial peripheral area corresponding to two sides of the first display area, and the third scan driving circuit is electrically connected to the first group of pixel units respectively.
In an embodiment of the array substrate, the array substrate further includes a plurality of gate lines, the gate lines include a first gate line and a second gate line, the first gate line is disposed in the first display area, the second gate line is disposed in the second display area, the first gate line is respectively connected to the first scan driving circuit and the third scan driving circuit, and the second gate line is connected to the second scan driving circuit.
In an embodiment of the array substrate, the second scan driving circuit is located in a peripheral area of a portion of both sides of the second display area.
In an embodiment of the above array substrate, the first display area is located at one end or two opposite ends of the second display area.
In an embodiment of the array substrate, the first display area includes a through hole, and the through hole may have a closed edge or a non-closed edge.
In an embodiment of the array substrate, the array substrate further includes a plurality of data lines, and each data line includes a step portion, and the step portion is located at a periphery of the through hole.
In an embodiment of the array substrate, the step portion includes a first step portion and a second step portion extending in opposite directions.
In an embodiment of the array substrate, a contour of two sides or a single side edge of the first display area is a circular arc.
In an embodiment of the above array substrate, a contour of another side of the first display area is concave.
In an embodiment of the array substrate, the first group of pixel units includes a first portion of pixel units, a second portion of pixel units, and a third portion of pixel units, wherein the first portion of pixel units or the third portion of pixel units may form an arc shape.
In an embodiment of the array substrate, the first group of pixel units includes a first portion of pixel units, a second portion of pixel units, and a third portion of pixel units, wherein the first portion of pixel units or the third portion of pixel units may form an arc shape, and the second portion of pixel units may form a concave shape.
In an embodiment of the array substrate, the first scan driving circuit is located in the first display region on two sides of the concave shape, or in the first display region between the concave shape and the arc shape.
In an embodiment of the array substrate, the first scan driving circuit is located in the first display region at the periphery of the through hole.
In an embodiment of the array substrate, a width of the first display area is greater than 0mm and less than 15 mm.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention;
FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a first display region of an array substrate according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of a first display region of an array substrate according to an embodiment of the invention;
FIG. 6 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a data line layout of an array substrate according to an embodiment of the present invention;
FIG. 9 is an enlarged partial schematic view of FIG. 8;
fig. 10 is a schematic structural diagram of a data line layout of an array substrate according to an embodiment of the invention.
Wherein the reference numerals
100. 200, 300, 400, 500: array substrate
110. 210, 310, 410: display area
120. 220, 320, 420: peripheral zone
111. 211, 311, 411: a first display region
112. 212, 312, 412: a second display region
130. 230, 330, 430: first scan driving circuit
140. 240, 340, 440: second scanning drive circuit
150. 250: pixel unit
151. 251, 351, 451: first group of pixel units
152. 252, 352, 452: second group of pixel units
260: third scanning drive circuit
170. 270: gate line
171. 271, 371, 471: a first gate line
172. 272, 372, 472: a second gate line
311a, 411a, 511a, 611 a: through hole
311b, 411 b: arc shape
351a, 451 a: first part of pixel unit
351b, 451 b: second part of pixel unit
351c, 451 c: third pixel unit
580. 680: data line
581: first step part
5811: first start end
5812: first end of the tube
582: second step part
5821: second start terminal
5822: second end terminal
681: first end
682: second end
H: width of
Detailed Description
The following detailed description of the embodiments of the present invention with reference to the drawings and specific examples is provided for further understanding the objects, aspects and effects of the present invention, but not for limiting the scope of the appended claims.
Unlike the conventional common rectangular display panel, the special-shaped display panel technology is becoming a focus of attention in the display screen industry, and the array substrate of the embodiment of the invention is specifically an array substrate constituting the special-shaped display panel. As shown in fig. 1, the array substrate 100 of the embodiment of the invention includes a display area 110 and a peripheral area 120, wherein the peripheral area 120 is adjacent to the display area 110, for example, the peripheral area 120 is located at the left and right sides, and the upper and lower sides of the display area 110, but the invention is not limited thereto, and the peripheral area 120 may also be a single-side area of the display area 110.
In the present embodiment, the display area 110 includes a first display area 111 and a second display area 112, and the first display area 111 is located at one end of the second display area 112. As shown in fig. 1, in the present embodiment, the first display area 111 is located above the second display area 112, and the second display area 112 is located in an area below the first display area 111, in other words, the first display area 111 and the second display area 112 distributed up and down form the display area 110 together.
Of course, the first display area 111 may be located at the lower part of the whole display area or other areas in some embodiments, and in another embodiment of the present invention, as shown in fig. 2, the first display area 111 is located at the upper part and the lower part of the whole display area, and the second display area 112 is located at the middle part of the display area, that is, the area between the upper part and the lower part of the first display area 111. However, the present invention is not limited thereto, and in the embodiment different from fig. 1 or fig. 2, the position relationship between the first display area 111 and the second display area 112 may be adjusted according to different reasons such as the use requirement, the process design, and the like.
As shown in fig. 1, generally, the width H of the first display region 111 is greater than 0mm and less than 15 mm. The width H is a distance that the first display region 111 extends downward relative to the top edge of the display region, or a distance that the first display region 111 extends upward relative to the bottom edge of the display region.
Referring to the embodiment shown in fig. 1, the array substrate 100 further includes a first scan driving circuit 130, a second scan driving circuit 140, and a plurality of pixel units 150. The first scan driving circuit 130 is disposed in the first display area 111, and the second scan driving circuit 140 is disposed in the peripheral area 120. The plurality of pixel units 150 includes a first group of pixel units 151 and a second group of pixel units 152, the first group of pixel units 151 is disposed in the first display region 111, and the second group of pixel units 152 is disposed in the second display region 112. The first scan driving circuit 130 is electrically connected to the first group of pixel units 151 disposed in the first display region 111, and the second scan driving circuit 140 is electrically connected to the second group of pixel units 152 disposed in the second display region 112.
Specifically, the second scan driving circuit 140 may be located in the peripheral region 120 of a portion of one side of the second display region 112, or may be located in the peripheral region 120 of portions of two sides of the second display region 112, as shown in fig. 1.
In detail, the array substrate 100 further includes a plurality of gate lines 170, the gate lines 170 include a first gate line 171 and a second gate line 172, the first gate line 171 is disposed in the first display region 111 and connected to the first scan driving circuit 130, and the second gate line 172 is disposed in the second display region 112 and connected to the second scan driving circuit 140. In this embodiment, the first scan driving circuit 130 drives the first group of pixel units 151 disposed in the first display region 111 through the first gate lines 171 to realize normal display of the first group of pixel units 151 in the first display region 111. The second scan driving circuit 140 drives the second group of pixel units 152 disposed in the second display area 112 through the second gate lines 172 to realize normal display of the second group of pixel units 152 in the second display area 112.
It should be noted that the driving manner of the second group of pixel units 152 in the second display area 112 driven by the second scan driving circuit 140 may be a dual-edge single-drive manner, a dual-edge dual-drive manner, and the like, which are all driving manners already applied in the art, and are not the subject of the present invention, and will not be described in detail herein.
In another embodiment of the present invention, as shown in fig. 3, the difference between the embodiment and the embodiment shown in fig. 1 is that the array substrate 200 further includes a third scan driving circuit 260, the third scan driving circuit 260 is disposed in the partial peripheral area 220 corresponding to two sides of the first display area 211, and the third scan driving circuit 260 is electrically connected to the first group of pixel units 251 respectively.
In this embodiment, the first group of pixel units 251 located in the first display region 211 can be driven not only by the first scan driving circuit 230 disposed in the first display region 211, but also by the third scan driving circuit 260 disposed in the peripheral region 220 at two sides of the first display region 211, so as to ensure that the first group of pixel units 251 can normally display.
The first scan driving circuit 230 and the third scan driving circuit 260 sequentially turn on the rows of the first group of pixel units 251 of the first display region 211 through the first gate lines 271, and the second scan driving circuit 240 sequentially turns on the rows of the second group of pixel units 252 of the second display region 212 through the second gate lines 272, so as to implement the display function of the display panel.
In an embodiment of the present invention, as shown in fig. 1 to 3, each of the first gate lines in the first display region is connected to a plurality of scan driving circuits. Therefore, even if the first display area is partially cut and changed from the rectangular display panel to the special-shaped display panel, normal display can still be ensured. In addition, the same mask can be used to manufacture the array substrate for either the rectangular display panel or the irregular display panel, so as to achieve the effect that the display panels of different shapes can share the mask.
Referring to fig. 4 and 5, fig. 4 and 5 are schematic views of a first display region of the special-shaped display panel, respectively. For example, in other embodiments of the present invention, the first display region of the array substrate includes a through hole, the through hole may have a closed edge (as shown in fig. 4) or an unsealed edge (as shown in fig. 5), and the first scan driving circuit is located at the first display region at the periphery of the through hole.
In detail, in the embodiment shown in fig. 4, the first display region 311 includes a through hole 311a, and the through hole 311a includes a closed edge. In addition, the edge contour of both sides of the first display region 311 is the arc shape 311b, but it is needless to say that the edge contour of a single side of the first display region 311 may be the arc shape 311b, and the invention is not limited thereto. In this embodiment, the first scan circuit 330 is located in the pixel unit of the first display region 311 at the periphery of the through hole 311 a. Specifically, in the embodiment, the first group of pixel units 351 in the first display region 311 of the array substrate 300 includes a first portion of pixel units 351a, a second portion of pixel units 351b and a third portion of pixel units 351c, wherein the circular arc shape 311b is formed on the outer contour of the first portion of pixel units 351a and/or the third portion of pixel units 351c, and the through hole 311a is formed on the second portion of pixel units 351 b. In this embodiment, after the through hole 311a and the circular arc 311b are formed, the first pixel unit 351a, the second pixel unit 351b and the third pixel unit 351c can still be driven by the first scanning circuit 330 in the pixel units of the first display region 311 located at the periphery of the through hole 311 a.
Referring to fig. 4 and fig. 6 together, fig. 6 is a schematic view of the special-shaped display panel, that is, fig. 4 is a partially enlarged schematic view of the first display region of fig. 6. As shown in fig. 6, the first display region 311 and the second display region 312 of the array substrate 300 represent different portions of the display region 310, and specifically, the first display region 311 is a portion of the display region of the array substrate having a corner cut and an arc-shaped groove (notch), and may be used to mount components such as a camera and a headphone. The second display area 312 is a portion of the display area of the array substrate without the chamfered, arc-shaped grooves. The first scan driving circuit 330 is disposed in the first group of pixel units 351 of the first display region 311 in the cutting region, and drives the first group of pixel units 351 through the first gate lines 371. The second scan driving circuit 340 is disposed in the peripheral regions 320 on the left and right sides of the second display region 312 in the non-cutting region, and drives the second group of pixel units 352 through the second gate lines 372.
Comparing fig. 1 and fig. 6, after the first display region 111 of the rectangular array substrate 100 shown in fig. 1 is cut, the irregular array substrate 300 shown in fig. 6 is formed, and each pixel unit of the first display region 311 can still be driven by the first scanning circuit 330, that is, even though the cut shapes such as the through hole 311a and the circular arc shape 311b are formed by cutting, the display of each pixel unit of the first display region 311 is not affected, and the array substrate can be normally used. Thus, the rectangular array substrate of the embodiment of the invention can share the photomask with the irregular array substrate.
In detail, in the embodiment of the present invention, after the irregular cutting is performed on the first display region 311, the first display region 311 may still normally display, and the common photomask with the corresponding non-irregular-cut common array substrate is realized, or after the parallel holes are dug, the common photomask with the corresponding non-irregular-cut common array substrate can be realized by only changing the photomask of the second metal layer, so that the time for arranging the substrates and the labor cost are greatly reduced.
In addition, according to the embodiment of the invention, through the arrangement, the cutting mode of the first display area can be designed according to the requirements of different customers, and the problem of the reduction of the penetration rate of the cut first display area can be solved by increasing the light transmission voltage and the like, so that the display effect is integrally ensured.
In another embodiment as shown in fig. 5, the first display area 411 includes a through hole 411a, and the through hole 411a includes an unsealed edge, in detail, a side of the first display area 411 has a concave shape. Similarly, the edge contour of both sides of the first display area 411 is a circular arc shape 411b, and of course, the edge contour of a single side of the first display area 411 may also be a circular arc shape 411b, which is not limited in the present invention. In the present embodiment, the first scan circuit 430 is located in the first display area 411 at the periphery of the through hole 411 a. Specifically, in the embodiment, the first group of pixel units 451 of the first display area 411 of the array substrate 400 includes a first portion of pixel units 451a, a second portion of pixel units 451b and a third portion of pixel units 451c, wherein the circular arc shape 411b is formed on the first portion of pixel units 451a and/or the third portion of pixel units 451c, and the concave through hole 411a is formed on the second portion of pixel units 451 b.
In the embodiment, after the through hole 411a and the circular arc 411b are formed, the first pixel unit 451a, the second pixel unit 451b and the third pixel unit 451c can still be driven by the first scanning circuit 430 in the pixel units of the first display area 411 located at the periphery of the through hole 411 a.
Please refer to fig. 5 and 7, fig. 7 is a schematic diagram of another special-shaped display panel, and fig. 5 is a partially enlarged schematic diagram of the first display region of fig. 7. As shown in fig. 7, the first scan driving circuit 430 is disposed in the first group of pixel units 451 in the first display area 411 of the cutting area, and drives the first group of pixel units 451 through the first gate lines 471. The second scan driving circuit 440 is disposed in the peripheral regions 420 at the left and right sides of the second display region 412 in the non-cutting region, and drives the second group of pixel units 452 through the second gate lines 472.
Comparing fig. 1 and fig. 7, after the first display area 111 of the rectangular array substrate 100 shown in fig. 1 is cut, the irregular array substrate 400 shown in fig. 7 is formed, that is, the cut shapes such as the through hole 411a and the circular arc shape 411b are formed by cutting, each pixel unit of the first display area 411 can still normally display, and the effect that the rectangular array substrate and the irregular array substrate can share a mask is achieved.
Referring to fig. 8, fig. 8 is a layout diagram of data lines around the through hole 511a of the array substrate 500. In the embodiment of fig. 8, the array substrate 500 includes a through hole 511a and a plurality of data lines 580, wherein the through hole 511a is located in a first display region of the display region, the data lines 580 include a step portion, and the step portion is located at the periphery of the through hole 511 a. Specifically, the data line 580 extends in a step manner around the periphery of the through hole 511a to avoid the through hole 511a, so as to avoid being cut when the through hole 511a is formed.
In detail, the step portions include a first step portion 581 and a second step portion 582 with opposite extending directions, so that the data line 580 at the periphery of the through hole 511a includes the first step portion 581 and the second step portion 582, wherein the first step portion 581 is connected to the second step portion 582. As shown, the first step 581 extends in the X direction to H at E, and the second step 582 extends in the opposite direction of the X direction to F at H.
Fig. 9 is a partial detail enlarged structure of fig. 8, in conjunction with fig. 8 and 9. Specifically, the first step portion 581 extends along the X direction and the direction of the through hole 511a, the second step portion 582 extends along the opposite direction of the X direction and the direction of the through hole 511a, that is, for the upper portion E of the through hole 511a shown in the figure, the first step portion 581 extends leftward and downward, the second step portion 582 extends rightward and downward, and the first step portion 581 and the second step portion 582 extend in a stepped manner around the periphery of the through hole 511a and avoid the through hole 511 a.
The first step portion 581 comprises a first starting end 5811 and a first ending end 5812, the second step portion 582 comprises a second starting end 5821 and a second ending end 5822, the first starting end 5811 of the first step portion 581 starts at E and extends in the X direction until the first ending end 5812 of the first step portion 581 extends to H, wherein the first ending end 5812 of the first step portion 581 connects with the second starting end 5821 of the second step portion 582, and then the second starting end 5821 of the second step portion 582 extends in the opposite direction of the X direction until the second ending end 5822 of the bottom portion F.
The structure of the right side of the data line 580 is similar to the structure of the left side described above.
Fig. 10 is a schematic structural diagram of a data line layout of an array substrate according to an embodiment of the invention. In the present embodiment, the data line 680 around the through hole 611a is in an arc layout, and in detail, the data line 680 includes a first end 681 and a second end 682, the data line 680 is in an arc layout from the first end 681 to the second end 682, and the arc data line avoids the through hole 611a to avoid being broken when the through hole 611a is formed. The structure of the right side of the data line 680 is similar to that of the left side described above. In the embodiment, the data lines are in arc-shaped layout, so that the required area is small, and the layout space is saved.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. The utility model provides an array substrate, includes a display area and a border region, the display area includes a first display area and a second display area, its characterized in that still includes:
a first scan driving circuit disposed in the first display region;
the second scanning driving circuit is arranged in the peripheral area; and
the plurality of pixel units comprise a first group of pixel units and a second group of pixel units, the first group of pixel units are arranged in the first display area, and the second group of pixel units are arranged in the second display area;
the first scanning driving circuit is electrically connected to the first group of pixel units, and the second scanning driving circuit is electrically connected to the second group of pixel units.
2. The array substrate of claim 1, further comprising a third scan driving circuit disposed in a portion of the peripheral region corresponding to two sides of the first display region, wherein the third scan driving circuit is electrically connected to the first group of pixel units respectively.
3. The array substrate of claim 2, further comprising a plurality of gate lines, wherein the gate lines include a first gate line and a second gate line, and the first gate line is disposed in the first display region and the second gate line is disposed in the second display region, wherein the first gate line is connected to the first scan driving circuit and the third scan driving circuit, respectively, and the second gate line is connected to the second scan driving circuit.
4. The array substrate of claim 1, wherein the second scan driving circuit is located in the peripheral region of portions on both sides of the second display region.
5. The array substrate of claim 1, wherein the first display area is located at one end or two opposite ends of the second display area.
6. The array substrate of claim 1, wherein the first display area comprises a via, and the via can have a closed edge or an open edge.
7. The array substrate of claim 6, further comprising a plurality of data lines, wherein the data lines comprise a step portion, and the step portion is located at the periphery of the through hole.
8. The array substrate of claim 7, wherein the step portion comprises a first step portion and a second step portion extending in opposite directions.
9. The array substrate of claim 1, wherein the outline of the two sides or the single side edge of the first display region is a circular arc.
10. The array substrate of claim 9, wherein the outline of the other side of the first display area is a concave shape.
11. The array substrate of claim 9, wherein the first group of pixel units comprises a first portion of pixel units, a second portion of pixel units and a third portion of pixel units, wherein the first portion of pixel units or the third portion of pixel units can form the circular arc shape.
12. The array substrate of claim 10, wherein the first group of pixel units comprises a first portion of pixel units, a second portion of pixel units and a third portion of pixel units, wherein the first portion of pixel units or the third portion of pixel units can form the circular arc shape, and the second portion of pixel units can form the concave shape.
13. The array substrate of claim 10, wherein the first scan driving circuit is located in the first display region on both sides of the concave shape or in the first display region between the concave shape and the arc shape.
14. The array substrate of claim 6, wherein the first scan driving circuit is located in the first display area at the periphery of the through hole.
15. The array substrate of claim 1, wherein the width of the first display area is greater than 0mm and less than 15 mm.
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| CN201811176911.4A CN109192125B (en) | 2018-10-10 | 2018-10-10 | Array substrate |
| TW108100247A TWI712018B (en) | 2018-10-10 | 2019-01-03 | Array substrate |
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| CN201811176911.4A CN109192125B (en) | 2018-10-10 | 2018-10-10 | Array substrate |
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| CN107274837A (en) * | 2016-03-31 | 2017-10-20 | 三星显示有限公司 | Display device |
| CN107561806A (en) * | 2017-09-29 | 2018-01-09 | 厦门天马微电子有限公司 | Array base palte and display panel |
| CN108492760A (en) * | 2018-01-15 | 2018-09-04 | 友达光电股份有限公司 | Display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202015014A (en) | 2020-04-16 |
| TWI712018B (en) | 2020-12-01 |
| CN109192125A (en) | 2019-01-11 |
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