TW201921511A - 封裝的半導體裝置 - Google Patents

封裝的半導體裝置

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Publication number
TW201921511A
TW201921511A TW107130545A TW107130545A TW201921511A TW 201921511 A TW201921511 A TW 201921511A TW 107130545 A TW107130545 A TW 107130545A TW 107130545 A TW107130545 A TW 107130545A TW 201921511 A TW201921511 A TW 201921511A
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TW
Taiwan
Prior art keywords
die
region
semiconductor device
package terminal
type
Prior art date
Application number
TW107130545A
Other languages
English (en)
Other versions
TWI662624B (zh
Inventor
石京郁
Original Assignee
美商艾賽斯股份有限公司
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Publication date
Application filed by 美商艾賽斯股份有限公司 filed Critical 美商艾賽斯股份有限公司
Publication of TW201921511A publication Critical patent/TW201921511A/zh
Application granted granted Critical
Publication of TWI662624B publication Critical patent/TWI662624B/zh

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Abstract

一種新穎四端子封裝的半導體裝置在400伏直流（DC）輸出功率因數校正（PFC）升壓轉換器電路中格外有用。在封裝的本體內安裝N通道場效電晶體（NFET）晶粒及快速反轉二極體晶粒，以使得NFET的底側汲極經由晶粒附著片電性耦接至所述反轉二極體的底側P型陽極區。第一端子T1耦合晶粒附著片。第二端子T2耦接至NFET晶粒的閘極。第三端子T3耦接至NFET晶粒的源極。第四端子T4耦接至快速反轉二極體晶粒的頂側陰極電極。由於反轉二極體晶粒的新穎P+型電荷載子提取區，所述封裝的裝置為快速的且在PFC升壓轉換器電路應用中具有低的反向漏電流。

Description

功率因子修正用之封裝的快速反轉二極體
所述實施例是有關於反轉二極體裝置及相關方法。
大多數可商業購得的具有高反向崩潰電壓能力類型的功率二極體（power diode）亦具有N-型底側陰極。可自加利福尼亞州米爾皮塔斯市1590七葉樹大道的艾賽斯（IXYS）公司商業購得的所謂「反轉二極體（inverse diode）」或「反向二極體（reverse diode）」是一罕見例外。該些不尋常的二極體具有包含底側P型陽極區及P型周邊側壁擴散區的P型隔離結構。該些不尋常的二極體相較於其他類型的二極體而言具有幾種優越特性。舉例而言，它們可具有高反向崩潰電壓（breakdown voltage），同時展現出優越的動態穩健性（dynamic robustness）。已在尋求將此種反轉二極體架構擴展到新應用領域中的方式。
一種新穎四端子封裝的半導體裝置具有第一封裝端子T1、第二封裝端子T2、第三封裝端子T3、第四封裝端子T4及封裝本體。在封裝本體內有晶粒附著片、N通道場效電晶體（N-channel field effect transistor，NFET）晶粒及新穎快速恢復反轉二極體裝置晶粒。NFET晶粒及快速恢復反轉二極體晶粒安裝至封裝本體內的晶粒附著片，以使NFET晶粒的底側汲極通過晶粒附著片電性耦接至反轉二極體晶粒的底側P型陽極區。NFET晶粒、快速恢復反轉二極體晶粒及晶粒附著片通常是用一定量的注射模塑包封體（injection molded encapsulant）而包覆模塑（overmold）。第一封裝端子T1耦接至晶粒附著片或者為晶粒附著片的一部分。第二封裝端子T2耦接至NFET晶粒的頂側閘極。第三封裝端子T3耦接至NFET晶粒的頂側源極。第四封裝端子T4耦接至反轉二極體晶粒的頂側陰極電極。
快速恢復反轉二極體晶粒是「反轉二極體」的原因在於其陽極位於所述晶粒的底側上且為P型區，並且其具有P型隔離結構。P型隔離結構將晶粒的中心主動區域與所述四個晶粒側邊緣及所述晶粒的底部半導體表面隔離且分隔開。快速恢復反轉二極體晶粒亦具有以下所有特性：1）在10安培的高電流正向導通狀態下，小於1.5伏的低正向電壓降（Vf ）；2）當反轉二極體晶粒自高電流正向電流狀態切換至-100伏的反向電壓狀態時，小於5安的峰值反向恢復電流（Irr ）；3）至少550伏的反向崩潰電壓（Vbr ）耐受能力；以及4）在450伏靜態反向阻斷狀態下的反向漏電流（Ilk ）小於100微安培。NFET晶粒是具有至少600伏的崩潰電壓（BVDSS ）的平面N通道功率金屬氧化物半導體場效電晶體（metal oxide semiconductor field effect transistor，MOSFET）。所述新穎封裝的半導體裝置當用於400伏直流（direct current，DC）輸出電壓功率因數校正（Power Factor Correction，PFC）升壓轉換器電路中特別有利及便利。
下文在詳細說明中闡述進一步的細節及實施例以及方法。此發明內容並非旨在界定本發明。本發明是由申請專利範圍所界定。
現將詳細參照背景實例及本發明的一些實施例，所述一些實施例的實例示出在附圖中。在以下說明及申請專利範圍中，當稱第一物體設置於第二物體「之上（over）」或第二物體「上（on）」時，應理解所述第一物體可直接位於所述第二物體上或者在所述第一物體與所述第二物體之間可存在中間物體。相似地，本文中使用例如「頂部（top）」、「頂側（topside）」、「上（up）」、「向上（upward）」、「下（down）」、「向下（downward）」、「垂直（vertically）」、「橫向（laterally）」、「側（side）」、「下方（under）」、「背側（backside）」、「底部（bottom）」及「底側（bottomside）」等用語來描述所描述結構的不同部分之間的相對定向，且應理解，所闡述總體結構實際上可在三維空間中以任意方式定向。當以下說明中闡述對晶圓的底部執行加工時，例如（舉例而言）當稱摻質向上擴散時，應理解所述晶圓實際上可在該些加工步驟期間上下翻轉而定向，且可以普通的方式自頂部進行加工。在以下說明中，大體而言，P型矽可被簡單地稱作P型矽，或者更具體而言，其可被稱作P++型矽、P+型矽、P型矽或P-型矽。所述P++、P+、P及P-標識符旨在標識一般粗略意義上的相對摻質濃度範圍。舉例而言，在被闡述為P+型矽的矽與被闡述為P型矽的矽之間的濃度範圍中可存在交疊。P+型矽範圍的最低（bottom）摻質濃度可低於P型矽範圍的最高（top）摻質濃度。在此專利文獻中亦採用相同的方式闡述N型矽（就有時更具體地指稱N+型矽、N型矽或N-型矽而言）。
圖1是根據一種新穎態樣的封裝的半導體裝置1的立體圖。封裝的半導體裝置1包括封裝本體部分2、第一封裝端子T1 3、第二封裝端子T2 4、第三封裝端子T3 5及第四封裝端子T4 6。本體部分2包括晶粒附著片7、N通道場效電晶體（NFET）晶粒8、快速恢復反轉二極體晶粒9、接合線10~16及一定量的注射模塑包封體17。所述一定量的注射模塑塑膠包封體17對NFET晶粒8及快速恢復反轉二極體晶粒9、接合線10~16及晶粒附著片7進行包覆模塑及包封。在此實例中，第一封裝端子T1實際上是晶粒附著片7的延伸。第一封裝端子T1及晶粒附著片7是同一單件衝壓銅片材的部分。該些端子的金屬是引線架（leadframe）的金屬且利用包封體進行的包覆模塑或注射模塑（例如，通過注射模塑聚合樹脂）如在傳統半導體裝置注射模塑封裝製程中進行。
圖2是示出封裝的半導體裝置1內的電路系統的圖。圖2亦示出封裝的半導體裝置1如何在400伏輸出電壓PFC直流交流升壓轉換器18中使用。NFET晶粒8具有頂側閘極及接墊19、頂側源極及接墊20以及底側汲極及接墊21。快速恢復反轉二極體晶粒9具有頂側陰極電極及接墊22以及底側陽極電極及接墊23。NFET晶粒8的頂側閘極19藉由接合線10耦接至封裝端子T2。NFET晶粒8的頂側源極20藉由接合線11-13耦接至封裝端子T3。反轉二極體晶粒9的頂側陰極電極22藉由接合線14~16耦接至第四端子T4。重要的是，NFET晶粒8的底側汲極21與反轉二極體晶粒9的底側陽極端子23均安裝於晶粒附著片7上，進而使得晶粒附著片7將NFET晶粒8的底側汲極21電性耦接至反轉二極體晶粒9的底側陽極端子23。NFET晶粒8及反轉二極體晶粒9可例如直接焊接至晶粒附著片7。
圖2所示PFC直流交流升壓轉換器18具有兩個輸入端子24及25以及兩個輸出端子26及27。升壓轉換器18自AC電源28接收240伏的AC均方根正弦輸入供應電壓（RMS sinusoidal input supply voltage）至輸入端子24及25上。升壓轉換器18將400伏DC電壓輸出至輸出端子26及27上。升壓轉換器18包括全橋整流器（full bridge rectifier），其包含四個二極體29~32、電感器33、封裝的半導體裝置1、控制電路34及輸出電容器35，而它們中的所有者如圖2中所示進行互連。新穎封裝的半導體裝置1的存在有利於製造升壓轉換器18。
NFET晶粒8是具有至少600伏的崩潰電壓（BVDSS ）的N通道平面型功率場效電晶體。反轉二極體晶粒9是所謂「反轉二極體」的原因在於其陽極位於晶粒的底側上且為P型區，並且其具有P型隔離結構。該P型隔離結構將晶粒的中心主動區域與所述四個晶粒側邊緣及所述晶粒的底表面隔離且分隔開。反轉二極體晶粒9亦具有以下所有特性：1）在10安培的高電流正向導通狀態下，小於1.5伏的低正向電壓降（Vf ）；2）當反轉二極體晶粒自高電流正向電流狀態切換至-100伏反向電壓狀態時，小於5安的峰值反向恢復電流（Irr ）；3）至少550伏的反向崩潰電壓（Vbr ）耐受能力；以及4）在450伏靜態反向阻斷狀態下，小於100微安的反向漏電流（Ilk ）。在一個實例中，反轉二極體晶粒9在未於所述晶粒的矽材料中引入額外重組中心的狀態下（例如藉由電子輻射（electron irradiation）、或者藉由包含重金屬原子、或者藉由氫或氦離子植入、或者藉由包含所謂「壽命抑制劑（lifetime killer）」）達成該些效能特性。
圖3是NFET晶粒8的剖面側視圖。N型漂移區36設置於N++型矽基板層及區37上。所述裝置的P本體包括P型本體區部分38及更重摻雜的P+型本體區39。標號40辨認為N+型源極區41。標號42辨認為N型接面場效電晶體（junction FET，JFET）區。標號43辨認為N+型多晶矽閘極。此閘極藉由閘極氧化物45與頂部半導體表面44分隔開。所述閘極之上設置有更多的氧化物46。底側汲極21設置於底部半導體表面47上。頂側源極20設置於氧化物46之上。頂側閘金屬電極19不存在於例示圖的特定剖面中，因此未將其示出。
圖4是述及NFET晶粒8的各種部分的濃度、摻質類型、構成材料、厚度及深度的表。
圖5是反轉二極體晶粒9的剖面側視圖。所述晶粒9具有矩形頂表面、矩形底表面及四個周邊側邊緣。在圖5所示剖面側視圖中繪示出兩個側邊緣48及49。更具體而言，底側P-型矽區50自晶粒的平面底部半導體表面51向上延伸且亦橫向向外延伸至所述晶粒的所有四個周邊側邊緣。如圖5中所示，在底側P-型矽區50上（on）及上方（over）設置N-型矽區52。此種N-型矽區52（其亦被稱作N-漂移區）與底側P-型矽區50為相同的塊狀晶圓材料（bulk wafer material）。N-型矽區52是反轉二極體晶粒的陰極，原因是所述二極體的主要PN接面是底側P-型矽區50的頂部與N-型矽區52的底部之間的接面。N型空乏終止區53自頂部半導體表面54向下延伸至N-型矽區52中。如所繪示的，N+型接觸區自頂部半導體表面54向下延伸且向下延伸至N型空乏終止區53中。在圖5中所示特定剖面中存在三個N+型接觸區55~57。亦存在環形N+型空乏終止區58。如所繪示的，新穎P+型電荷載子提取區59自頂部半導體表面54向下延伸且向下延伸至N型空乏終止區53中。
圖6是P+型電荷載子提取區59及N+型接觸區55~57、環形N+型空乏終止區58以及N型空乏終止區53的俯視圖。圖6所示俯視圖是向下俯視於晶粒的頂部半導體表面上。圖5所示剖面圖是沿圖6所示的剖線A-A'截取。如可自圖6所示俯視圖看出，所述九個N+型接觸區設置成由列與行構成的二維陣列。所述九個N+型接觸區中的每一者被P+型電荷載子提取區59的P+型矽橫向環繞。環形N+型空乏終止區58圍繞P+型電荷載子提取區59的外周邊延伸。所述九個N+型接觸區的深度、環形N+型空乏終止區的深度及P+型電荷載子提取區的深度相似。在此實例中，該些深度處於約0.4微米至約0.6微米範圍內。N型空乏終止區53的深度為約1.6微米，其中此距離是自N-型區52的頂部至P+型電荷載子提取區59的底部量測。N型空乏終止區53被製作成充分厚於P+型電荷載子提取區59，以使在裝置的所期望最大反向阻斷電壓下，主要空乏區（來自區50與區52之間的PN接面）只要到達位於P+型電荷載子提取區59的底部與N型空乏終止區53的N型矽之間的PN接面處的空乏區便不再向上延伸。如所繪示的，P+型浮場環（P+ type floating field ring）63自頂部半導體表面54向下延伸且向下延伸至N-型矽區52中。P+型浮場環63周邊環繞N型空乏終止區53所在之所述晶粒的中心主動區域。
所述晶粒亦具有P型矽周邊側壁區60，自所述晶粒的四個周邊側邊緣橫向向內延伸，進而使得P型矽周邊側壁區60環繞中心N-型矽區52。P型矽周邊側壁區60向下延伸且接合底側P-型矽區50且亦向上延伸至頂部半導體表面54。P型周邊區60與底側P-型矽區50的組合形成所謂「P型隔離結構」（有時亦稱作「P型隔離區」或「P型分隔擴散結構」或「P型分隔擴散區」）。此種結構的P型矽完全地環繞N-型矽區52（既自側面周邊地環繞N-型矽區52，亦自底部在下方完全地環繞N-型矽區52）。在一個實例中，P型分隔擴散結構是藉由以下方式製成：使鋁自頂部半導體表面54向下擴散以形成區60，且利用P型摻質對晶圓的底部進行離子植入並接著藉由雷射退火（laser annealing）活化摻質以形成區50。
關於各種適合的不同P型分隔擴散結構及如何形成它們的附加資訊參見：1）由凱博勞（Kelberlau）等人於2005年8月30日申請、標題為「製作正向及反向阻斷裝置的方法（Method For Fabricating Forward And Reverse Blocking Devices）」的美國專利第7,442,630號；2）由內森·左莫（N. Zommer）於1995年7月31日申請、標題為「製作反向阻斷絕緣閘極雙極電晶體的方法（Method Of Making A Reverse Blocking IGBT）」的美國專利第5,698,454號；3）由柏林及海登堡的施普林格出版（2011）的約瑟夫·魯茨（J. Lutz）等人所著「半導體功率裝置（Semiconductor Power Devices）」第146至147頁；4）由美國加利福尼亞州米爾皮塔斯（95035）的艾賽斯公司發佈、標題為「二極體晶片（Diode Chip）」的資料表DWN 17至18；5）由維索斯基（Wisotzki）等人於2005年11月20日申請、標題為「高電壓裝置的溝槽分隔擴散（Trench Separation Diffusion For High Voltage Device）」的美國專利第9,590,033號；6）由望月（Mochizuki）等人於1980年7月10日申請、標題為「製造具有鋁擴散半導體基板的半導體裝置的方法（Method of Manufacturing Semiconductor Device Having Aluminum Diffused Semiconductor Substrate）」的美國專利第4,351,677號；7）由格林（Green）於2000年8月16日申請、標題為「具有新穎同心周界區段排列的閘流體（Thyristors Having A Novel Arrangement of Concentric Perimeter Zones）」的美國專利第6,507,050號；8）由凱博勞等人於2002年3月13日申請、標題為「正向及反向阻斷裝置（Forward and Reverse Blocking Devices）」的美國專利第6,936,908號；9）由內迪格（Neidig）於2005年3月14日申請、標題為「平面技術中的功率半導體組件（Power Semiconductor Component in the Planar Technique）」的美國專利第7,030,426號；10）由韋拉馬（Veeramma）等人於2003年8月27日申請、標題為「電力裝置的崩潰電壓（Breakdown Voltage For Power Devices）」的美國專利第8,093,652號；11）由德國蘭佩特海姆艾丁森大街15號（D-68623）的艾賽斯半導體有限責任公司於2004年發佈、標題為「平面設計中的快速恢復磊晶二極體、整流器二極體及閘流體晶片（FRED, Rectifier Diode and Thyristor Chips in Planar Design）」的說明；12）由維索斯基等人於2012年2月20日申請、標題為「薄化晶圓的凹陷側上的功率裝置製造（Power Device Manufacture On The Recessed Side Of A Thinned Wafer）」的美國專利第8,716,067號；由韋拉馬於2006年5月11日申請、標題為「用於低頻率及高頻率應用的穩定二極體（Stable Diodes For Low And High Frequency Applications）」的美國專利第8,716,745號。以下文獻中的每一者的整個主題併入本案供參考：1）美國專利第7,442,630號；2）美國專利第5,698,454號；3）美國專利第9,590,033號；4）美國專利第4,351,677號；5）美國專利第6,507,050號；6）美國專利第6,936,908號；7）美國專利第7,030,426號，8）美國專利第8,093,652號；9）美國專利第8,716,067號；10）美國專利第8,716,745號。
如所繪示的，氧化物層61直接設置於頂部半導體表面54上。此種氧化物層61橫向環繞頂部半導體表面的陰極接觸部分。如所繪示的，頂側金屬電極22直接設置於頂部半導體表面54的陰極接觸部分上。頂側金屬電極22是反轉二極體裝置的陰極電極或陰極端子。底側金屬電極23直接設置於晶粒的底部半導體表面51上。此種底側金屬電極23自晶粒側邊緣48至晶粒側邊緣49延伸橫跨整個底部半導體表面51。底側金屬電極23及底側P-型區50較頂側金屬電極22寬得多。底側金屬電極23是反轉二極體裝置的陽極電極或陽極端子。頂側鈍化層62設置於氧化物層61之上，以使鈍化部交疊且覆蓋頂側金屬電極22的周邊邊緣。底部半導體表面51與頂部半導體表面54之間的所有矽區均是塊狀矽晶圓材料。不存在磊晶矽材料（epitaxial silicon material）。
圖7是述及反轉二極體裝置晶粒9的各種部分的摻質濃度、摻質類型及尺寸的表。
圖8是述及包括新穎P+型電荷載子提取區59的圖5所示反轉二極體裝置晶粒9的操作特性的表。表中的資料是使用被稱作新思科技森陶勒斯工作台（Synopsys Sentaurus Workbench，SWB）的裝置模擬器而獲得。圖5至圖7所示反轉二極體的結構最初是使用二維森陶勒斯結構編輯器（Sentaurus Structure Editor，SDE）而定義。所定義結構被接著使用工作台工具套件的裝置模擬器（Sdevice）部分進行模擬。
圖9是示出反轉二極體裝置晶粒9在正向偏壓情況下的操作的剖面圖。圖10以放大的方式示出圖9所示晶粒的一部分。在正向偏壓狀態下，電流自位於底部上的陽極電極23向上流過所述裝置並自位於頂部上的陰極電極22流出。在此期間，在區52及53中存在高濃度的電荷載子。此包括高濃度的電子及高濃度的電洞（hole）。當二極體兩端的電壓極性被迅速反轉至反向阻斷狀態時，該些區52及53中的大量電子及電洞必須在二極體可開始阻斷電流之前以某種方式得到消除。該些電荷載子中的一些電荷載子可由於電子與電洞的重組而得到消除，而其他的電荷載子則可藉由所述電荷載子以反向恢復電流Irr 的形式流出二極體晶粒而得到消除。為減小此種反向恢復電流的峰值大小（peak magnitude），在反轉二極體裝置晶粒9中減小區52及53中的電荷載子在正向偏壓狀態期間的濃度。在正向偏壓狀態下，空乏區64位於P+型電荷載子提取區59與N型空乏終止區53之間的一或多個邊界處。圖10中示出此種空乏區64。空乏區64形成橫跨所述空乏區的電場65。此種電場65的方向由箭頭65指示。恰巧靠近於空乏區64或位於空乏區64的邊界處的電洞由於此種局部化電荷提取電場而在箭頭65所示方向上橫掃空乏區64。圖10中的箭頭67繪示出一個代表電洞68的路徑。當二極體以其正向導通模式進行操作時，電洞的提取是連續的。藉由局部化電荷提取電場65連續地提取電洞，使二極體裝置的區52及53中的電洞在正向偏壓狀態下的濃度降低（相較於在假若不存在P+型電荷載子提取區的情況下原本將呈現出的電洞濃度）。另外，位於附近的經提取之電洞附近的對應電子傾向於被射出。區53及區52中維持電荷中性（charge neutrality），因而電子被自所述裝置的底部逐出。圖10中的箭頭69示出一個此種代表性電子70的路徑。當二極體以其正向導通模式進行操作時，電子的此種流動亦是連續的。電子的流動使所述裝置的區53及52中的電子在正向偏壓狀態下的濃度降低（相較於在假若不存在P+型電荷載子提取區的情況下原本將呈現出的電子濃度）。由於區53及52中的電洞及電子的數目隨之減少，因此當二極體迅速自正向導通狀態切換至反向電壓狀態時被自所述二極體移除的電荷載子較少。
圖11是示出當二極體裝置自正向偏壓狀態切換至反向偏壓狀態時反轉二極體裝置9的操作的剖面圖。圖12以放大的方式示出圖11所示反轉二極體裝置晶粒的一部分。在底側P-型矽區50與N-型矽區52之間的PN接面處存在空乏區71。當二極體裝置兩端的電位反向時，空乏區71擴大。其向下擴大，但會由於N-矽區中的較低濃度而進一步向上擴大。此種空乏區71形成電場72。來自擴大的空乏區71的電洞經由底側P-型矽區50向下朝陽極電極23移動。圖11中的箭頭73代表該些電洞中的一個代表性電洞的路徑。來自擴大的空乏區71的電子經由N-型矽區52向上移動。圖12中的箭頭74代表該些電子中的一個代表性電子的路徑。圖12示出該些逃逸的電子如何在其前往陰極電極22的途中向上穿過N+型接觸區。一旦電荷載子由於擴大的空乏區71而自二極體裝置被移除且一旦區52及53中的過量電荷載子（由於在正向偏壓狀態下的高電荷載子濃度而存在）自二極體裝置被移除，則反向恢復電流Irr 的大小開始降低。二極體裝置隨後以這裡稱作「靜態反向阻斷模式（static reverse blocking mode）」的操作開始運行。在長期靜態狀態下，因二極體裝置兩端的反向極性而流動的反向電流的量（被稱作反向漏電流（Ilk ））為小的。
一種製作快速恢復二極體的傳統方式是減少二極體的電荷載子所在的區中的此種電荷載子的壽命。載子壽命的此種減少可藉由在二極體的中心漂移區中的矽中引入所謂「重組中心」來達成。該些重組中心一般是藉由利用離子植入在矽中形成缺陷及/或藉由將離子或原子沉積至矽晶格（silicon crystal lattice）中而引入。此種重組中心在自正向偏壓狀態切換至反向偏壓狀態的短時間內通常是有益的，乃因此時存在於所述二極體中的一些電子與電洞可重組。若該些電子與電洞重組，則它們無需被以反向恢復電流的形式自所述二極體移除。因此，由於重組中心而造成的電子與電洞的重組用於減小非期望反向恢復電流的大小。然而，在經過此種切換時間之後，且二極體開始以其靜態反向阻斷模式進行操作，矽晶格中的該些重組中心及缺陷是非期望的且可能使二極體洩漏。反向漏電流因此增大（相較於在假若尚未添加重組中心及矽缺陷的情況下原本將存在的反向漏電流而言）。然而，在本發明的反轉二極體裝置晶粒9中，二極體裝置使用P+型電荷載子提取區59以降低電荷載子濃度。因此，無需植入或損壞N-型矽區52的矽來形成壽命抑制劑重組中心。有利地，在N-型矽區52的矽中沒有特別添加的重組中心或「壽命抑制劑」離子或電荷載子陷獲原子。反轉二極體晶粒9因此既展現出良好的反向恢復特性又展現出低的反向漏電流。
圖13是示出在反轉二極體裝置晶粒9的切換期間的二極體電流波形75的波形圖。最初，經由二極體裝置晶粒傳導10安培的正向電流。在此種正向導通時間期間，在二極體兩端存在正向電壓降（Vf ）。接著迅速切換二極體裝置晶粒兩端的電壓極性以使二極體裝置晶粒9阻斷電流。此處將時間Tzz 定義為自當經由二極體的反向恢復電流Irr （當自正向導通狀態轉變至反向阻斷狀態時）第一次降低至負電流時直至所述反向恢復電流重新升高並達到零電流（zero current）為止的時間。反向恢復電流峰值（Irr(PEAK) ）出現在這兩個過零時間（zero crossing time）之間。如圖13中所示，時間Tzz 是在反向換向期（reverse commutation episode）期間反向電流的過零之間的時間間隔。
在反轉二極體裝置晶粒9中沒有磊晶矽。所述裝置的長期動態耐用性（long term dynamic ruggedness）可由於裝置的邊緣終止區中的氧化物/鈍化部介面沒有任何磊晶矽而改善。為製作此種結構，對N-型晶圓執行頂側加工。在頂側鈍化步驟之後，藉由背側研磨（backside grinding）將晶圓薄化。在晶圓的薄化側中植入P型摻質，且藉由雷射退火活化所述P型摻質。在底側金屬化之後，對晶圓進行切割。因此，在所述裝置中沒有磊晶矽。在另一實例中，反轉二極體裝置晶粒不具有磊晶矽。起始材料為P型晶圓。在所述晶圓上生長N-型磊晶矽。在頂側加工及頂側鈍化之後，藉由背側研磨將晶圓薄化。在底側金屬化之後，對晶圓進行切割。圖1所示封裝的半導體裝置1的反轉二極體裝置晶粒9可為任一種構造，只要其包括新穎P+型電荷載子提取區59即可。
藉由利用晶圓薄化，圖5的所得反轉二極體裝置晶粒9的N-型區52的厚度減小至28微米，其中此距離是自底側P-型區50的頂部至N型空乏終止區53的底部量測。N型空乏終止區53的厚度為1.6微米，其中此距離是自N-型區52的頂部至P+型電荷載子提取區59的底部量測。P+型電荷載子提取區59的厚度為0.4微米，其中此距離是自N型空乏終止區53的頂部至頂部半導體表面54量測。在底側P-型區50為3微米厚的情形中，薄化晶圓的總體厚度為33微米，其中此距離是自底部半導體表面51至頂部半導體表面54量測。對於圖2所示功率因數校正（PFC）升壓轉換器應用，僅需要適度的反向崩潰電壓耐受能力。反轉二極體裝置晶粒之較薄的N-型區（位於區53的底部與區50的頂部之間）使二極體裝置晶粒9能夠既具有低的正向電壓Vf 降（在正向導通期間，處於高電流位準）又具有小的峰值反向恢復電流Irr 。在圖2所示PFC升壓轉換器應用的情形中，二極體晶粒9必須耐受約400伏的反向電壓。所述裝置的電壓額定值是其實際崩潰電壓的70%，因而具有恰當額定值的二極體裝置晶粒需具有約550伏的崩潰電壓。但另外，需要另外10%的裕度來達成可製造性（manufacturablity）。因此，圖2所示電路中的反轉二極體裝置晶粒9被製作成具有約550伏的反向擊穿額定值及600伏的目標反向崩潰電壓。對於此種反轉二極體裝置晶粒，在二極體製造期間自晶圓的背側將所述晶圓充分地薄化，進而使得N-型區52的所得厚度為約28微米。藉由此種方式，新穎P+型電荷載子提取區59的優點適用於圖2所示PFC升壓轉換器應用。在PFC升壓轉換器應用的高溫情況下，經由反轉二極體晶粒9的反向漏電流增大。然而，新穎反轉二極體裝置晶粒9在對於二極體晶粒所經歷的切換條件而言維持其「快速」性（低的Irr(PEAK) ）的同時仍具有所期望的低反向漏電流。
關於可如何製作快速恢復反轉二極體晶粒9的附加資訊及細節參見：由石京旭（Kyoung Wook Seok）於2017年8月31日申請、標題為「電荷載子提取反轉二極體（Charge Carrier Extraction Inverse Diode）」、序列號為第15/693,392號的美國專利申請案（所述美國專利申請案的整個主題併入本案供參考）。
儘管以上出於教示目的闡述了一些具體實施例，然而此專利文獻的教示內容具有普適性且不限於上述具體實施例。儘管以上述及其中NFET晶粒及反轉二極體晶粒被安裝至晶粒附著片的實例，然而NFET晶粒及反轉二極體晶粒可被安裝至另一類型的基板。在基板為晶粒附著片的情形中，第一封裝端子可為晶粒附著片的延伸部分。晶粒附著片及第一封裝端子可為同一衝壓金屬件的部分，例如金屬導線架（leadframe）的一部分。在另一實例中，基板是單獨的結構且第一封裝端子電性耦接至所述單獨的結構（例如，藉由接合線）。第一封裝端子亦可結合至所述單獨的結構。封裝本體可包含如上所述的注射模塑塑膠，但其亦可包含另一類型的包封結構及材料。在一些實例中，基板的一部分或表面不被包封體覆蓋而使此部分或表面可更好地散熱。儘管基板未被包封體完全包住，然而所述包封體將NFET及反轉二極體包封於所述基板上。因此，可在不背離申請專利範圍中所述及的本發明的範圍的條件下實踐所述實施例的各種特徵的各種實施例、改動版本及組合。
1‧‧‧封裝的半導體裝置
2‧‧‧本體部分
3‧‧‧第一封裝端子
4‧‧‧第二封裝端子
5‧‧‧第三封裝端子
6‧‧‧第四封裝端子
7‧‧‧晶粒附著片
8、9‧‧‧晶粒
10、11、12、13、14、15、16‧‧‧接合線
17‧‧‧注射模塑包封體
18‧‧‧升壓轉換器
19‧‧‧頂側閘極
20‧‧‧頂側源極
21‧‧‧底側汲極
22‧‧‧陰極電極/金屬電極
23‧‧‧陽極電極/金屬電極
24、25‧‧‧輸入端子
26、27‧‧‧輸出端子
28‧‧‧AC電源
29、30、31、32‧‧‧二極體
33‧‧‧電感器
34‧‧‧薄化晶圓
35‧‧‧輸出電容器
36‧‧‧N型漂移區
37‧‧‧N++型矽基板層及區
38‧‧‧P型本體區部分
39‧‧‧P+型本體區
41‧‧‧N+型源極區
42‧‧‧N型接面場效電晶體（JFET）區
43‧‧‧N+型多晶矽閘極
44‧‧‧頂部半導體表面
45‧‧‧閘極氧化物
46‧‧‧氧化物
47‧‧‧底部半導體表面
48、49‧‧‧側邊緣
50‧‧‧區/底側P-型矽區
51‧‧‧半導體表面
52‧‧‧區/N-型矽區
53‧‧‧區/N型空乏終止區
54‧‧‧頂部半導體表面
55、56、57‧‧‧N+型接觸區
58‧‧‧環形N+型空乏終止區
59‧‧‧P+型電荷載子提取區
60‧‧‧區/P型矽周邊側壁區
61‧‧‧氧化物層
62‧‧‧頂側鈍化層
63‧‧‧P+型浮場環
64‧‧‧空乏區
65‧‧‧電場
67、69、73、74‧‧‧路徑
68‧‧‧電洞
70‧‧‧電子
71‧‧‧空乏區
72‧‧‧電場
75‧‧‧二極體電流波形
A-A'‧‧‧剖線
BVDSS‧‧‧崩潰電壓
Ilk‧‧‧反向漏電流
Irr‧‧‧反向恢復電流
Irr(peak)‧‧‧反向恢復電流峰值
T1‧‧‧第一端子/第一封裝端子
T2‧‧‧第二端子/第二封裝端子
T3‧‧‧第三端子/第三封裝端子
T4‧‧‧第四端子/第四封裝端子
Tzz‧‧‧時間
Vbr‧‧‧反向崩潰電壓
Vf‧‧‧正向電壓降
附圖示出本發明的實施例，在所附圖式中相同的編號指示相同的元件。 圖1是根據一種新穎態樣的封裝的半導體裝置的立體圖。 圖2是繪示出圖1所示封裝的半導體裝置內的電路系統且亦示出圖1所示封裝的半導體裝置如何在PFC交流-直流（AC-to-DC）升壓轉換器電路中使用的圖。 圖3是圖1所示封裝的半導體裝置內的NFET晶粒的剖面側視圖。 圖4是述及圖3所示NFET晶粒的各種部分的濃度、摻質類型、構成材料、厚度及深度的表。 圖5是圖1所示封裝的半導體裝置內的反轉二極體晶粒的剖面側視圖。 圖6是圖5所示反轉二極體裝置晶粒的P+型電荷載子提取區的俯視圖。 圖7是述及圖5所示反轉二極體裝置晶粒的各種部分的濃度、摻質類型、構成材料、厚度及深度的表。 圖8是述及圖5所示反轉二極體裝置晶粒的操作特性的表。 圖9是圖5所示反轉二極體裝置晶粒在正向導通情況下的剖面側視圖。 圖10以放大的方式示出圖9的一部分。 圖11是示出當二極體裝置晶粒兩端的電壓極性自正向導通狀態迅速切換至反向阻斷狀態時圖5所示反轉二極體裝置晶粒的操作的剖面側視圖。 圖12以放大的方式示出圖11所示反轉二極體裝置晶粒的一部分。 圖13是示出時間Tzz 的波形圖。

Claims (20)

  1. 一種封裝的半導體裝置，包括： 第一封裝端子； 晶粒附著片，其中所述晶粒附著片耦接至所述第一封裝端子； N通道場效電晶體（NFET）晶粒，其中所述N通道場效電晶體晶粒具有頂側閘極、頂側源極及底側汲極，其中所述底側汲極安裝至所述晶粒附著片； 反轉二極體晶粒，其中所述反轉二極體晶粒包括： 底側P型矽區，自所述反轉二極體晶粒的底部半導體表面向上延伸，亦橫向向外延伸至所述反轉二極體晶粒的周邊側邊緣； N-型矽區，設置於所述底側P型矽區之上； N型空乏終止區，自所述頂部半導體表面向下延伸且延伸至所述N-型矽區中； P+型電荷載子提取區，自所述頂部半導體表面向下延伸且延伸至所述N型空乏終止區中； N+型接觸區，自所述頂部半導體表面向下延伸且延伸至所述N型空乏終止區中； P型矽周邊側壁區，自所述頂部半導體表面向下延伸至所述N-型矽區中，其中所述P型矽周邊側壁區與所述底側P型矽區接合而形成P型隔離結構，其中所述P型矽周邊側壁區亦橫向環繞所述N-型矽區並將所述N-型矽區與所述反轉二極體晶粒的所述周邊側邊緣分隔開； 頂側陰極電極，設置於所述N+型接觸區上及所述P+型電荷載子提取區上；以及 底側陽極電極，設置於所述反轉二極體晶粒的所述底部半導體表面上，其中所述底側陽極電極安裝至所述晶粒附著片； 第二封裝端子，耦接至所述N通道場效電晶體晶粒的所述頂側閘極； 第三封裝端子，耦接至所述N通道場效電晶體晶粒的所述頂側源極； 第四封裝端子，耦接至所述反轉二極體晶粒的所述頂側陰極電極；以及 一定量的包封體，將所述N通道場效電晶體晶粒與所述反轉二極體晶粒包封於所述第一封裝端子的所述晶粒附著片部分及所述晶粒附著片上。
  2. 如申請專利範圍第1項所述的封裝的半導體裝置，其中所述反轉二極體晶粒在450伏的靜態反向阻斷狀態下具有小於100微安培的反向漏電流（Ilk ）。
  3. 如申請專利範圍第1項所述的封裝的半導體裝置，其中所述第一封裝端子是所述晶粒附著片的延伸，其中所述第一封裝端子及所述晶粒附著片是單件衝壓金屬的兩個部分。
  4. 如申請專利範圍第1項所述的封裝的半導體裝置，其中所述第一封裝端子接合至所述晶粒附著片。
  5. 如申請專利範圍第1項所述的封裝的半導體裝置，其中所述第一封裝端子通過接合線耦接至所述晶粒附著片。
  6. 如申請專利範圍第1項所述的封裝的半導體裝置，其中所述封裝的半導體裝置具有四個且不大於四個封裝端子。
  7. 如申請專利範圍第1項所述的封裝的半導體裝置，其中所述反轉二極體晶粒具有所有以下特性：1）在10安培的高電流正向導通狀態下，小於1.5伏的低正向電壓降（Vf ）；2）當所述反轉二極體晶粒自所述高電流正向電流狀態切換至100伏反向電壓狀態時，小於5安的峰值反向恢復電流（Irr ）；3）至少550伏的反向崩潰電壓（Vbr ）耐受能力；以及4）在450伏的靜態反向阻斷狀態下，小於100微安的反向漏電流（Ilk ）。
  8. 如申請專利範圍第1項所述的封裝的半導體裝置，其中所述N通道場效電晶體晶粒具有至少550伏的崩潰電壓（BVDSS ）。
  9. 一種封裝的半導體裝置，包括： 第一封裝端子； 晶粒附著片，其中所述晶粒附著片耦接至所述第一封裝端子； N通道場效電晶體（NFET）晶粒，其中所述N通道場效電晶體晶粒具有頂側閘極、頂側源極及底側汲極，其中所述底側汲極安裝至所述晶粒附著片； 反轉二極體晶粒，其中所述反轉二極體晶粒具有頂側陰極電極、底側P型矽區及底側陽極電極，其中所述底側陽極電極安裝至所述晶粒附著片，其中所述晶粒附著片將所述N通道場效電晶體的所述底側汲極電性耦接至所述反轉二極體晶粒的所述底側陽極電極； 第二封裝端子，耦接至所述N通道場效電晶體晶粒的所述頂側閘極； 第三封裝端子，耦接至所述N通道場效電晶體晶粒的所述頂側源極； 第四封裝端子，耦接至所述反轉二極體晶粒的所述頂側陰極電極；以及 一定量的包封體，將所述N通道場效電晶體晶粒與所述反轉二極體晶粒包封於所述第一封裝端子的所述晶粒附著片部分及所述晶粒附著片上。
  10. 如申請專利範圍第9項所述的封裝的半導體裝置，其中所述第一封裝端子是所述晶粒附著片的延伸，其中所述第一封裝端子及所述晶粒附著片是單件衝壓金屬的兩個部分。
  11. 如申請專利範圍第9項所述的封裝的半導體裝置，其中所述第一封裝端子接合至所述晶粒附著片。
  12. 如申請專利範圍第9項所述的封裝的半導體裝置，其中所述第一封裝端子通過接合線耦接至所述晶粒附著片。
  13. 如申請專利範圍第9項所述的封裝的半導體裝置，其中所述反轉二極體晶粒具有頂部半導體表面，所述反轉二極體晶粒更包括： N型空乏終止區，自所述頂部半導體表面向下延伸且延伸至N-型矽區中； P+型電荷載子提取區，自所述頂部半導體表面向下延伸且延伸至所述N型空乏終止區中；以及 N+型接觸區，自所述頂部半導體表面向下延伸且延伸至所述N型空乏終止區中，其中所述頂側陰極電極耦接至所述P+型電荷載子提取區與所述N+型接觸區。
  14. 如申請專利範圍第9項所述的封裝的半導體裝置，其中所述反轉二極體晶粒在450伏的靜態反向阻斷狀態下具有小於100微安培的反向漏電流（Ilk ）。
  15. 如申請專利範圍第9項所述的封裝的半導體裝置，其中所述反轉二極體晶粒具有所有以下特性：1）在10安培的高電流正向導通狀態下，小於1.5伏的低正向電壓降（Vf ）；2）當所述反轉二極體晶粒自所述高電流正向電流狀態切換至100伏反向電壓狀態時，小於5安的峰值反向恢復電流（Irr ）；3）至少550伏的反向崩潰電壓（Vbr ）耐受能力；以及4）在450伏的靜態反向阻斷狀態下，小於100微安的反向漏電流（Ilk ）。
  16. 如申請專利範圍第9項所述的封裝的半導體裝置，其中所述封裝的半導體裝置具有四個且不大於四個封裝端子。
  17. 一種封裝的半導體裝置，包括： 第一封裝端子； 基板，具有導電表面，其中所述導電表面耦接至所述第一封裝端子； N通道場效電晶體（NFET）晶粒，其中所述N通道場效電晶體晶粒具有頂側閘極、頂側源極及底側汲極，其中所述底側汲極安裝至所述基板； 用於在正向電壓條件下傳導電流且在反向電壓條件下阻斷電流的構件（means），其中所述構件具有頂側金屬電極及底側金屬電極，其中所述底側金屬電極安裝至所述基板，其中所述構件用於：1）在10安培的正向導通狀態下以小於1.5伏的正向電壓降傳導正向電流；2）自所述正向導通狀態切換至100伏反向電壓狀態而不會傳導大於5安培的反向恢復電流；3）耐受至少550伏的反向電壓而不會受到反向擊穿；以及4）耐受450伏的靜態反向阻斷狀態而不會傳導大於100微安培的反向漏電流； 第二封裝端子，耦接至所述N通道場效電晶體晶粒的所述頂側閘極； 第三封裝端子，耦接至所述N通道場效電晶體晶粒的所述頂側源極； 第四封裝端子，耦接至所述構件的所述頂側金屬電極；以及 一定量的包封體，將所述N通道場效電晶體晶粒與所述構件包封於所述基板上。
  18. 如申請專利範圍第17項所述的封裝的半導體裝置，其中所述第一封裝端子是所述基板的延伸，其中所述第一封裝端子及所述基板是單件衝壓金屬的兩個部分。
  19. 如申請專利範圍第17項所述的封裝的半導體裝置，其中所述第一封裝端子接合至所述基板。
  20. 如申請專利範圍第17項所述的封裝的半導體裝置，其中所述第一封裝端子通過接合線耦接至所述基板。
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