TW201919173A - Contact hole structure mrthod for fabricting the same and applications thereof - Google Patents

Contact hole structure mrthod for fabricting the same and applications thereof Download PDF

Info

Publication number
TW201919173A
TW201919173A TW106139069A TW106139069A TW201919173A TW 201919173 A TW201919173 A TW 201919173A TW 106139069 A TW106139069 A TW 106139069A TW 106139069 A TW106139069 A TW 106139069A TW 201919173 A TW201919173 A TW 201919173A
Authority
TW
Taiwan
Prior art keywords
layer
opening
interlayer dielectric
dielectric layer
metal
Prior art date
Application number
TW106139069A
Other languages
Chinese (zh)
Other versions
TWI641096B (en
Inventor
李岱螢
曾柏皓
李峰旻
林昱佑
許凱捷
Original Assignee
旺宏電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 旺宏電子股份有限公司 filed Critical 旺宏電子股份有限公司
Priority to TW106139069A priority Critical patent/TWI641096B/en
Application granted granted Critical
Publication of TWI641096B publication Critical patent/TWI641096B/en
Publication of TW201919173A publication Critical patent/TW201919173A/en

Links

Abstract

A contact hole structure includes a substrate, an interlayer dielectric (ILD), a contact layer and an insulating capping layer. The ILD is disposed on the substrate and has a first opening. The contact layer is disposed in the ILD and aligns the first opening. The insulating capping layer has a spacer disposed on a first sidewall of the first opening, wherein the spacer contacts to the conductive layer and defines a second opening in the first opening, so as to expose a portion of the conductive layer.

Description

接觸開口結構與製作方法及其應用Contact opening structure and manufacturing method and application thereof
本揭露書是有關於一種積體電路結構及其製作方法與應用。特別是有關於一種接觸開口結構及其製作方法與應用。The disclosure is related to an integrated circuit structure and a manufacturing method and application thereof. In particular, it relates to a contact opening structure and a manufacturing method and application thereof.
隨著積體電路複雜度與特徵尺寸的持續微縮,形成具有高尺寸精度和可靠性的層間接觸結構(圖案)變得越來越困難。如何滿足超大規模積體電路(ultra-large-scale integration circuit)對於層間接觸結構(圖案)之尺寸精度和操作可靠度不斷提高的要求,已經成為業界的一大挑戰。而接觸開口結構與其製作方法,又是製作高尺寸精度和可靠性之層間接觸結構(圖案)的關鍵。As the complexity of the integrated circuit and the feature size continue to shrink, it becomes more and more difficult to form an interlayer contact structure (pattern) with high dimensional accuracy and reliability. How to meet the requirements of the ultra-large-scale integration circuit for the dimensional accuracy and operational reliability of the interlayer contact structure (pattern) has become a major challenge in the industry. The contact opening structure and its fabrication method are the key to making interlayer contact structures (patterns) with high dimensional accuracy and reliability.
因此,有需要提供一種先進的接觸開口結構與製作方法及其應用,來解決習知技術所面臨的問題。Therefore, there is a need to provide an advanced contact opening structure and fabrication method and its application to solve the problems faced by the prior art.
本說明書的一實施例係揭露一種接觸開口結構,此種接觸開口結構,包括:基材、層間介電層、導電層以及絕緣覆蓋層。層間介電層位於基材之上,且具有第一開口。導電層位於層間介電層中,並對準第一開口。絕緣覆蓋層具有位於第一開口之第一側壁上的間隙壁,其中間隙壁與導電層接觸,並在第一開口中定義出一個第二開口,藉以將一部份導電層暴露於外。An embodiment of the present specification discloses a contact opening structure including: a substrate, an interlayer dielectric layer, a conductive layer, and an insulating cover layer. An interlayer dielectric layer is over the substrate and has a first opening. The conductive layer is in the interlayer dielectric layer and is aligned with the first opening. The insulating cover layer has a spacer on the first sidewall of the first opening, wherein the spacer contacts the conductive layer and defines a second opening in the first opening to expose a portion of the conductive layer.
本說明書的另一實施例揭露一種接觸開口結構的製作方法,此方法包括下述步驟:首先提供一個基材,再於基材上形成一個層間介電層。並於層間介電層中形成一個導電層,使至少一部分導電層經由層間介電層中的一個第一開口暴露於外。之後,於層間介電層上形成一個絕緣覆蓋層,並延伸進入第一開口之中。形成一個含金屬緩衝層以覆蓋絕緣覆蓋層。在移除位於層間介電層上方的一部份含金屬緩衝層之後,移除位於第一開口中的一部分絕緣覆蓋層,以使剩餘的絕緣覆蓋層在第一開口的第一側壁上形成間隙壁,而與導電層接觸,藉以在第一開口中定義出一個第二開口,將至少一部份導電層暴露於外。Another embodiment of the present specification discloses a method of fabricating a contact opening structure, the method comprising the steps of first providing a substrate and then forming an interlayer dielectric layer on the substrate. And forming a conductive layer in the interlayer dielectric layer such that at least a portion of the conductive layer is exposed to the outside through a first opening in the interlayer dielectric layer. Thereafter, an insulating cover layer is formed on the interlayer dielectric layer and extends into the first opening. A metal containing buffer layer is formed to cover the insulating cover layer. After removing a portion of the metal-containing buffer layer above the interlayer dielectric layer, removing a portion of the insulating cap layer in the first opening such that the remaining insulating cap layer forms a gap on the first sidewall of the first opening The wall is in contact with the conductive layer to define a second opening in the first opening to expose at least a portion of the conductive layer.
本說明書的另一實施例揭露一種電阻式隨機存取記憶體(Resistance Random Access Memory, ReRAM)元件,此電阻式隨機存取記憶體單元包括:基材、層間介電層、底部電極層、絕緣覆蓋層、過渡金屬氧化物(Transition Metal Oxides,TMO)層以及上方電極層。層間介電層位於基材之上,且具有一個第一開口。底部電極層位於層間介電層中,並對準第一開口。絕緣覆蓋層具有位於第一開口之第一側壁上的間隙壁,其中間隙壁與底部電極層接觸,並在第一開口中定義出一個第二開口。過渡金屬氧化物層,位於第二開口中,並與底部電極層接觸。上方電極層位於第二開口中,並與過渡金屬氧化物層接觸。Another embodiment of the present disclosure discloses a resistive random access memory (ReRAM) device including: a substrate, an interlayer dielectric layer, a bottom electrode layer, and an insulating layer. A cover layer, a Transition Metal Oxides (TMO) layer, and an upper electrode layer. The interlayer dielectric layer is over the substrate and has a first opening. The bottom electrode layer is in the interlayer dielectric layer and is aligned with the first opening. The insulating cover layer has a spacer on the first side wall of the first opening, wherein the spacer wall is in contact with the bottom electrode layer and defines a second opening in the first opening. A transition metal oxide layer is located in the second opening and is in contact with the bottom electrode layer. The upper electrode layer is located in the second opening and is in contact with the transition metal oxide layer.
根據上述實施例,本說明書是在提供一種接觸開口結構及其製作方法以及應用此一接觸開口結構所製作的電阻式隨機存取記憶體單元。其係先在層間介電層中形成導電層使其經由第一開口暴露於外。再形成一個絕緣覆蓋層部分地填充第一開口,並在絕緣覆蓋層上覆蓋一個含金屬緩衝層。在移除覆蓋於層間介電層上的一部份含金屬緩衝層之後,將一部分的含金屬緩衝層餘留在第一開口中,藉以覆蓋位於第一開口之側壁上的一部分絕緣覆蓋層。之後,再移除位於第一開口底部的一部分絕緣覆蓋層,藉以在第一開口中定義出一個第二開口,將至少一部份導電層暴露在外。According to the above embodiment, the present specification provides a contact opening structure, a manufacturing method thereof, and a resistive random access memory cell fabricated by using the contact opening structure. It is first formed in the interlayer dielectric layer to expose it to the outside through the first opening. An insulating cover layer is further formed to partially fill the first opening, and a metal-containing buffer layer is covered on the insulating cover layer. After removing a portion of the metal-containing buffer layer overlying the interlayer dielectric layer, a portion of the metal-containing buffer layer remains in the first opening to cover a portion of the insulating cap layer on the sidewall of the first opening. Thereafter, a portion of the insulating cover layer at the bottom of the first opening is removed, thereby defining a second opening in the first opening to expose at least a portion of the conductive layer.
藉由含金屬緩衝層的保護,可使餘留在第一開口側壁上的一部分絕緣覆蓋層不會受到後續蝕刻製程的毀損,可精確地控制第二開口的寬度尺寸,以在層間介電層中形成一個具有較小寬度尺寸的接觸開口。可進一步微縮後續形成在接觸開口中之元件或內連線的結構尺寸,進而提高整體電路的元件密度。By protecting the metal-containing buffer layer, a portion of the insulating coating remaining on the sidewall of the first opening is not damaged by the subsequent etching process, and the width dimension of the second opening can be accurately controlled to be in the interlayer dielectric layer. A contact opening having a smaller width dimension is formed in the middle. The structural dimensions of the subsequently formed elements or interconnects in the contact openings can be further reduced, thereby increasing the component density of the overall circuit.
本說明書是提供一種接觸開口結構及其製作方法,以及應用此一接觸開口結構所製作的電阻式隨機存取記憶體單元,可微縮形成在接觸開口中的元件或內連線結構,進而提高整體電路的元件密度。為了對本說明書之上述實施例及其他目的、特徵和優點能更明顯易懂,下文特舉一記憶體元件及其製作方法作為較佳實施例,並配合所附圖式作詳細說明。The present specification provides a contact opening structure and a manufacturing method thereof, and a resistive random access memory unit fabricated by using the contact opening structure, which can be formed into a component or an interconnect structure in a contact opening, thereby improving the overall The component density of the circuit. The above described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.
但必須注意的是,這些特定的實施案例與方法,並非用以限定本發明。本發明仍可採用其他特徵、元件、方法及參數來加以實施。較佳實施例的提出,僅係用以例示本發明的技術特徵,並非用以限定本發明的申請專利範圍。該技術領域中具有通常知識者,將可根據以下說明書的描述,在不脫離本發明的精神範圍內,作均等的修飾與變化。在不同實施例與圖式之中,相同的元件,將以相同的元件符號加以表示。However, it must be noted that these specific embodiments and methods are not intended to limit the invention. The invention may be practiced with other features, elements, methods and parameters. The preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the invention. Equivalent modifications and variations will be made without departing from the spirit and scope of the invention. In the different embodiments and the drawings, the same elements will be denoted by the same reference numerals.
請參照第1A圖至第1E圖,第1A圖至第1E圖係根據本說明書的一實施例,繪示製作接觸開口結構100的一系列製程結構剖面圖。製作接觸開口結構100的方法包括下述步驟:首先提供一個基材101,並且在基材101表面101a上形成一個層間介電層(Interlayer Dielectric, ILD)104,使其具有一個導電層102經由層間介電層104的一個第一開口105暴露於外。Referring to FIGS. 1A through 1E, FIGS. 1A through 1E are cross-sectional views showing a series of process structures for fabricating the contact opening structure 100 in accordance with an embodiment of the present specification. The method of fabricating the contact opening structure 100 includes the steps of first providing a substrate 101 and forming an interlayer dielectric (ILD) 104 on the surface 101a of the substrate 101 to have a conductive layer 102 via the interlayer. A first opening 105 of the dielectric layer 104 is exposed to the outside.
例如,基材101可以是一個矽基材。且基材101中還包括一個金屬-氧化物-半導體場效電晶體(Metal-Oxide-Semiconductor Filed Effect Transistor,MOSFET)單元103。層間介電層104,其包含堆疊於基材101表面101a上方的第一部份層間介電層104A,以及堆疊於第一部份層間介電層104A上方的第二部分層間介電層104B。導電層102貫穿第一部份層間介電層104A,與電晶體單元103的源極 /汲極103a接觸,用以作為電晶體單元103與其他元件(未繪示)電性連接的金屬插塞。第二部分層間介電層104B覆蓋於導電層102上,且具有一個第一開口105,用來將至少有一部分導電層102暴露於外(如第1A圖所繪示)。For example, the substrate 101 can be a tantalum substrate. The substrate 101 further includes a Metal-Oxide-Semiconductor Filed Effect Transistor (MOSFET) unit 103. An interlayer dielectric layer 104 includes a first portion of the interlayer dielectric layer 104A stacked over the surface 101a of the substrate 101, and a second portion of the interlayer dielectric layer 104B stacked over the first portion of the interlayer dielectric layer 104A. The conductive layer 102 is in contact with the source/drain 103a of the transistor unit 103, and is used as a metal plug electrically connected to other components (not shown). . The second portion of the interlayer dielectric layer 104B overlies the conductive layer 102 and has a first opening 105 for exposing at least a portion of the conductive layer 102 (as depicted in FIG. 1A).
在本說明書的一些實施例中,構成第一部份層間介電層104A和第二部分層間介電層104B層的材料,可以是由矽氧化物(SiOx)、氮化矽(SiNx)和氮氧化矽(SiON)中至少一種或其他合適的介電材質。其中,構成第一部份層間介電層104A和第二部分層間介電層104B層的材料,可以相同或不同。而構成導電層102的材料,可以包括金屬。In some embodiments of the present specification, the material constituting the first partial interlayer dielectric layer 104A and the second partial interlayer dielectric layer 104B may be made of tantalum oxide (SiOx), tantalum nitride (SiNx), and nitrogen. At least one of cerium oxide (SiON) or other suitable dielectric material. The materials constituting the first partial interlayer dielectric layer 104A and the second partial interlayer dielectric layer 104B may be the same or different. The material constituting the conductive layer 102 may include a metal.
在本實施例中,可以先藉由沉積製程(例如原子層沉積法(Atomic Layer Deposition, ALD)製程),在基材101表面101a上,形成材質為二氧化矽的第一部份層間介電層104A。再採用乾式蝕刻製程(例如反應式離子蝕刻(Reactive Ion Etching,RIE)製程)來移除一部份第一部份層間介電層104A,形成貫穿孔111將一部分的基材101表面101a暴露出來。之後,以導電材料,填充貫穿孔111,再予以平坦化,例如進行化學機械研磨(Chemical-Mechanical Polishing,CMP)製程,以形成導電層102。後續形成第二部分層間介電層104B覆蓋於第一部份層間介電層104A與導電層102上,再以蝕刻製程移除一部分第二部分層間介電層104B,以形成第一開口105,將至少一部份的導電層102暴露於外。其中,第一開口105的寬度範圍實質介於50奈米至150奈米之間。In this embodiment, a first portion of the interlayer dielectric material of the material ceria is formed on the surface 101a of the substrate 101 by a deposition process (for example, an Atomic Layer Deposition (ALD) process). Layer 104A. A dry etching process (such as a reactive ion etching (RIE) process) is used to remove a portion of the first portion of the interlayer dielectric layer 104A, and the through hole 111 is formed to expose a portion of the surface 101a of the substrate 101. . Thereafter, the through hole 111 is filled with a conductive material, and then planarized, for example, by a chemical-mechanical polishing (CMP) process to form the conductive layer 102. Subsequently forming a second portion of the interlayer dielectric layer 104B over the first portion of the interlayer dielectric layer 104A and the conductive layer 102, and then removing a portion of the second portion of the interlayer dielectric layer 104B by an etching process to form the first opening 105. At least a portion of the conductive layer 102 is exposed to the outside. Wherein, the width of the first opening 105 ranges substantially between 50 nm and 150 nm.
然後,於介電層104上形成一個絕緣覆蓋層106,並延伸進入第一開口105中,以覆蓋被暴露於外的一部分導電層102 (如第1B圖所繪示)。在本說明書的一些實施例中,構成絕緣覆蓋層106的材料可以是矽氧化物、氮化矽或二者的組合。在本實施例中,絕緣覆蓋層106可以是一種藉由沉積製程(例如原子層沉積法)形成在層間介電層104和導電層102上,厚度實質介於100埃(angstrom,Å)至1500埃的二氧化矽層。其中,絕緣覆蓋層106包括覆蓋於第二部分層間介電層104B上方的第一部分絕緣覆蓋層106A,以及覆蓋於第一開口105的第一側壁105a和底部105b之上的第二部分絕緣覆蓋層106B。且絕緣覆蓋層106並未完全填滿第一開口105。An insulating cap layer 106 is then formed over the dielectric layer 104 and extends into the first opening 105 to cover a portion of the conductive layer 102 that is exposed (as depicted in FIG. 1B). In some embodiments of the present specification, the material constituting the insulating cover layer 106 may be tantalum oxide, tantalum nitride, or a combination of both. In this embodiment, the insulating cap layer 106 may be formed on the interlayer dielectric layer 104 and the conductive layer 102 by a deposition process (for example, atomic layer deposition), and the thickness is substantially between 100 angstroms (Åstroms) and 1500 degrees. A layer of erbium dioxide. The insulating cover layer 106 includes a first partial insulating cover layer 106A overlying the second partial interlayer dielectric layer 104B, and a second partial insulating cover layer overlying the first sidewall 105a and the bottom portion 105b of the first opening 105. 106B. And the insulating cover layer 106 does not completely fill the first opening 105.
接著,形成一個含金屬緩衝層107,覆蓋於絕緣覆蓋層106之上(如第1C圖所繪示)。在本說明書的一些實施例中,構成含金屬緩衝層107的材料可以是鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、鉭氮化(TaN)或上述之任意組合。在本實施例中,絕緣覆蓋層106可以是一種藉由沉積製程(例如原子層沉積法)形成在上,厚度實質介於10埃至200埃的氮化鈦薄膜。Next, a metal-containing buffer layer 107 is formed overlying the insulating cap layer 106 (as depicted in FIG. 1C). In some embodiments of the present specification, the material constituting the metal-containing buffer layer 107 may be titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or any combination thereof. In the present embodiment, the insulating cap layer 106 may be a titanium nitride film formed by a deposition process (for example, atomic layer deposition) having a thickness substantially between 10 angstroms and 200 angstroms.
後續,移除位於第一部分絕緣覆蓋層106A上方 (與第二部分層間介電層104B重疊)的一部份含金屬緩衝層107。在本說明書的一些實施例中,移除一部份含金屬緩衝層107的步驟,可採用第一部分絕緣覆蓋層106A為蝕刻停止層,以乾式電漿蝕刻,不須使用任何罩幕,直接移除一部份的含金屬緩衝層107。Subsequently, a portion of the metal containing buffer layer 107 overlying the first portion of the insulating cap layer 106A (overlying the second portion of the interlayer dielectric layer 104B) is removed. In some embodiments of the present specification, the step of removing a portion of the metal-containing buffer layer 107 may be performed by using a first portion of the insulating cap layer 106A as an etch stop layer for dry plasma etching without using any mask. Except for a portion of the metal containing buffer layer 107.
根據沉積製程的特性,一般而言沉積層(例如含金屬緩衝層107)形成在開口(例如第一開口105)中的厚度,會實質上小於沉積在平面(例如第一部分絕緣覆蓋層106A頂面)上的厚度。因此,在本實施例中,當移除位於第一部分絕緣覆蓋106A上方的一部份含金屬緩衝層107時,位於第一開口105底部105b上的一部份含金屬緩衝層107會被移除,而將一部分第二部分絕緣覆蓋層106B暴露於外,僅餘留下一部分金屬緩衝層107,覆蓋住位於第一開口105之第一側壁105a的另一部分第二部分絕緣覆蓋層106B。其中,餘留下來的一部分金屬緩衝層107,可以具有L形的一截面形狀 (如第1D圖所繪示)。但在本說明書的另一些實施例中,當移除位於第一部分絕緣覆蓋層106A上方的一部份含金屬緩衝層107時,位於第一開口105之第一側壁105a和底部105b的所有含金屬緩衝層107可能會被一併移除。Depending on the nature of the deposition process, generally the thickness of the deposited layer (e.g., metal-containing buffer layer 107) formed in the opening (e.g., first opening 105) will be substantially less than that deposited on the plane (e.g., the top surface of the first portion of insulating coating 106A). The thickness on the). Therefore, in the present embodiment, when a portion of the metal-containing buffer layer 107 located above the first portion of the insulating cover 106A is removed, a portion of the metal-containing buffer layer 107 on the bottom portion 105b of the first opening 105 is removed. While a portion of the second portion of the insulating cap layer 106B is exposed, only a portion of the metal buffer layer 107 remains, covering another portion of the second portion of the insulating cap layer 106B of the first sidewall 105a of the first opening 105. Wherein, a portion of the remaining metal buffer layer 107 may have an L-shaped cross-sectional shape (as shown in FIG. 1D). However, in other embodiments of the present specification, all of the metal containing the first sidewall 105a and the bottom 105b of the first opening 105 are removed when a portion of the metal containing buffer layer 107 above the first portion of the insulating cap layer 106A is removed. The buffer layer 107 may be removed together.
然後,以導電層102為蝕刻停止層,進行另一次蝕刻製程,移除位於第一開口105底部105b上的一部分第二部分絕緣覆蓋層106B,使剩餘的第二部分絕緣覆蓋層106B於第一開口105之第一側壁105a上形成一個間隙壁108,而與導電層102接觸,並在第一開口105中定義出一個第二開口109,藉以將位於第一開口105底部105b的一部份導電層102暴露於外,形成如第1E圖所繪示的接觸開口結構100。其中,餘留下來的含金屬緩衝層107,係位於間隙壁108上,且與暴露於外的導電層104相隔一段距離H1。Then, using the conductive layer 102 as an etch stop layer, another etching process is performed to remove a portion of the second partial insulating cover layer 106B on the bottom portion 105b of the first opening 105, so that the remaining second portion of the insulating cover layer 106B is first. A spacer 108 is formed on the first sidewall 105a of the opening 105 to be in contact with the conductive layer 102, and a second opening 109 is defined in the first opening 105, thereby electrically conducting a portion of the bottom portion 105b of the first opening 105. The layer 102 is exposed to form a contact opening structure 100 as depicted in FIG. 1E. The remaining metal-containing buffer layer 107 is located on the spacers 108 and is separated from the exposed conductive layer 104 by a distance H1.
在本實施例中,在形成第二開口109時,並未將第一部份絕緣覆蓋層106A全部移除。剩餘之第一部份絕緣覆蓋層106A的厚度為實質介於10埃至300埃之間。但在本說明書的一些實施例中,在形成第二開口109時,會將接觸開口結構100’中的第一部份絕緣覆蓋層106A全部移除。意即,剩餘的第一部份絕緣覆蓋層106A厚度為0,可將第二部分層間介電層104B暴露於外,並在剩餘的第二部分層間介電層104B和第二部分絕緣覆蓋層106B二者之間,形成一個具有高梯差的階梯狀結構110(如第1E’圖所繪示)。在本說明書的另一些實施例中,在形成第二開口109時,不僅將剩餘之第一部份絕緣覆蓋層106A全部移除,並且還移除了一部分的第二部分層間介電層104B,使第二部分層間介電層104B的厚度減少了10埃至300埃之間。In the present embodiment, the first portion of the insulating cover layer 106A is not completely removed when the second opening 109 is formed. The remaining first portion of the insulating cover layer 106A has a thickness of substantially between 10 angstroms and 300 angstroms. However, in some embodiments of the present specification, the first portion of the insulating cover layer 106A in the contact opening structure 100' will be completely removed when the second opening 109 is formed. That is, the remaining first portion of the insulating cap layer 106A has a thickness of 0, the second portion of the interlayer dielectric layer 104B may be exposed, and the remaining second portion of the interlayer dielectric layer 104B and the second portion of the insulating cap layer Between the two, a stepped structure 110 having a high step is formed (as shown in FIG. 1E'). In other embodiments of the present specification, when the second opening 109 is formed, not only the remaining first partial insulating cover layer 106A is removed, but also a portion of the second partial interlayer dielectric layer 104B is removed. The thickness of the second portion of the interlayer dielectric layer 104B is reduced by between 10 angstroms and 300 angstroms.
藉由含金屬緩衝層107的保護,可使餘留在第一開口105之第一側壁105a上,用來構成間隙壁108的一部分絕緣覆蓋層106不會受到蝕刻製程的毀損,可精確地控制第二開口109的寬度尺寸,藉以微縮形成在第二開口109中的元件或內連線結構,進而提高整體電路的元件密度。By the protection of the metal-containing buffer layer 107, the first sidewall 105a of the first opening 105 can be left over, and a part of the insulating cover layer 106 for forming the spacers 108 is not damaged by the etching process, and can be accurately controlled. The width dimension of the second opening 109 is formed by miniaturizing the component or interconnect structure formed in the second opening 109, thereby increasing the component density of the overall circuit.
請參照第2A圖至第2E圖,第2A圖至第2E圖係根據本說明書的再一實施例,繪示製作接觸開口結構200的一系列製程結構剖面圖。製作接觸開口結構200的方法包括下述步驟:首先提供一個基材201,並且在基材201表面上形成一個層間介電層204,使其具有一個導電層202經由層間介電層204的一個第一開口205暴露於外。Referring to FIGS. 2A-2E, FIGS. 2A-2E are cross-sectional views showing a series of process structures for fabricating the contact opening structure 200 according to still another embodiment of the present specification. The method of fabricating the contact opening structure 200 includes the steps of first providing a substrate 201 and forming an interlayer dielectric layer 204 on the surface of the substrate 201 to have a conductive layer 202 via a layer of the interlayer dielectric layer 204. An opening 205 is exposed to the outside.
例如,基材201可以是一個矽基材。且基材201中還包括一個金屬-氧化物-半導體場效電晶體單元203。層間介電層204堆疊於基材201表面201a上方。導電層202貫穿層間介電層204,與電晶體單元203的源極/汲極203a接觸,用以作為電晶體單元203的金屬插塞,並且經由層間介電層204中的第一開口205暴露於外(如第2A圖所繪示)。在本說明書的一些實施例中,構成層間介電層204的材料可以是由矽氧化物、氮化矽和氮氧化矽中至少一種或其他合適的介電材質。導電層202可以包括金屬。For example, substrate 201 can be a tantalum substrate. Also included in the substrate 201 is a metal-oxide-semiconductor field effect transistor unit 203. The interlayer dielectric layer 204 is stacked over the surface 201a of the substrate 201. The conductive layer 202 penetrates the interlayer dielectric layer 204, is in contact with the source/drain 203a of the transistor unit 203, serves as a metal plug of the transistor unit 203, and is exposed through the first opening 205 in the interlayer dielectric layer 204. Outside (as shown in Figure 2A). In some embodiments of the present specification, the material constituting the interlayer dielectric layer 204 may be at least one of tantalum oxide, tantalum nitride, and hafnium oxynitride or other suitable dielectric material. Conductive layer 202 can include a metal.
在本實施例中,可以先藉由沉積製程(例如原子層沉積法製程),在基材201表面201a上,形成材質為二氧化矽的層間介電層204。再採用乾式蝕刻製程(例如反應式離子蝕刻製程)來移除一部份層間介電層204,形成貫穿孔211將一部分的基材201表面201a暴露出來。之後,以導電材料,填充貫穿孔211,再予以平坦化,以形成由基材201的表面201a向下延伸,且與電晶體單元203的源極/汲極203a接觸的導電層202。In this embodiment, the interlayer dielectric layer 204 made of cerium oxide may be formed on the surface 201a of the substrate 201 by a deposition process (for example, an atomic layer deposition process). A dry etching process (for example, a reactive ion etching process) is used to remove a portion of the interlayer dielectric layer 204, and a through hole 211 is formed to expose a portion of the surface 201a of the substrate 201. Thereafter, the through hole 211 is filled with a conductive material, and then planarized to form a conductive layer 202 extending downward from the surface 201a of the substrate 201 and in contact with the source/drain 203a of the transistor unit 203.
之後,再對導電層202進行回蝕,移除一部分的導電層202,使導電層202的頂部202a實質低於基材201的表面201a ,以定義第一開口205 (如第2A圖所繪示)。在本發明的一些實施例中,第一開口205的深度D2 ,由基材201的表面201a 起算至導電層202的頂部202a,實質介於500埃製2000埃之間。在本實施例中,回蝕之後貫穿開口211的深度,實質介於1000埃至1500埃之間。Thereafter, the conductive layer 202 is etched back, and a portion of the conductive layer 202 is removed, so that the top portion 202a of the conductive layer 202 is substantially lower than the surface 201a of the substrate 201 to define the first opening 205 (as shown in FIG. 2A). ). In some embodiments of the present invention, the depth D2 of the first opening 205 is calculated from the surface 201a of the substrate 201 to the top portion 202a of the conductive layer 202, substantially between 500 angstroms and 2000 angstroms. In the present embodiment, the depth of the through opening 211 after etch back is substantially between 1000 Å and 1500 Å.
然後,形成一個絕緣覆蓋層206,覆蓋於層間介電層204上並延伸進入第一開口205之中(如第2B圖所繪示)。在本說明書的一些實施例中,絕緣覆蓋層206可以是一種藉由沉積製程(例如原子層沉積法)形成在層間介電層204上,厚度實質介於50埃至2500埃的二氧化矽層。在本實施例中,絕緣覆蓋層206的厚度實質介於100埃至2000埃。其中,絕緣覆蓋層206包括覆蓋於層間介電層204上(未與第一開口205重疊)的第一部分絕緣覆蓋層206A,以及延伸進入第一開口205,但未完全填滿第一開口205的第二部分絕緣覆蓋層206B。An insulating cap layer 206 is then formed overlying the interlayer dielectric layer 204 and extending into the first opening 205 (as depicted in FIG. 2B). In some embodiments of the present specification, the insulating cap layer 206 may be a ceria layer formed on the interlayer dielectric layer 204 by a deposition process (eg, atomic layer deposition) having a thickness substantially between 50 Å and 2500 Å. . In the present embodiment, the thickness of the insulating cover layer 206 is substantially between 100 angstroms and 2000 angstroms. The insulating cover layer 206 includes a first partial insulating cover layer 206A overlying the interlayer dielectric layer 204 (not overlapping the first opening 205), and extending into the first opening 205 but not completely filling the first opening 205. The second portion of the insulating cover layer 206B.
接著,形成一個含金屬緩衝層207,覆蓋於絕緣覆蓋層206之上(如第2C圖所繪示)。在本說明書的一些實施例中,絕緣覆蓋層206可以是一種藉由沉積製程(例如原子層沉積法)形成在上,厚度實質介於5埃至200埃的氮化鈦薄膜。在本實施例中,絕緣覆蓋層206的厚度實質介於10埃至100埃。Next, a metal containing buffer layer 207 is formed overlying the insulating cap layer 206 (as depicted in FIG. 2C). In some embodiments of the present specification, the insulating cap layer 206 may be a titanium nitride film formed by a deposition process (eg, atomic layer deposition) having a thickness substantially between 5 angstroms and 200 angstroms. In the present embodiment, the thickness of the insulating cover layer 206 is substantially between 10 angstroms and 100 angstroms.
後續,移除位於第一部分絕緣覆蓋層206A (與層間介電層204)上方的一部份含金屬緩衝層207。在本說明書的一些實施例中,移除一部份含金屬緩衝層207的步驟,可採用第一部份絕緣覆蓋層206A為蝕刻停止層,以乾式電漿蝕刻,不須使用任何罩幕,直接移除一部份的含金屬緩衝層207。Subsequently, a portion of the metal-containing buffer layer 207 above the first portion of the insulating cap layer 206A (and the interlayer dielectric layer 204) is removed. In some embodiments of the present specification, the step of removing a portion of the metal-containing buffer layer 207 may employ a first portion of the insulating cap layer 206A as an etch stop layer for dry plasma etching without using any mask. A portion of the metal containing buffer layer 207 is removed directly.
根據沉積製程的特性,一般而言沉積層(例如含金屬緩衝層207)形成在開口(例如第一開口205)中的厚度,會實質上小於沉積在平面(例如第一部分絕緣覆蓋層206A頂部)上的厚度。因此在本實施例中,當移除位於第一部分絕緣覆蓋206A上方的一部份含金屬緩衝層207時,位於第一開口205底部205b上的一部份含金屬緩衝層207會被移除,而將一部分第二部分絕緣覆蓋層206B暴露於外,僅餘留下一部分金屬緩衝層207,覆蓋住位於第一開口205之第一側壁205a的另一部分第二部分絕緣覆蓋層206B。其中,餘留下來的一部分金屬緩衝層107,可以具有L形的一截面形狀(如第2D圖所繪示)。但在本說明書的另一些實施例中,當移除位於第一部分絕緣覆蓋層206A上方的一部份含金屬緩衝層207時,位於第一開口205側壁205a和底部205b上的所有含金屬緩衝207可能會被一併移除。Depending on the nature of the deposition process, generally the thickness of the deposited layer (eg, metal-containing buffer layer 207) formed in the opening (eg, first opening 205) will be substantially less than deposited on the plane (eg, at the top of the first portion of insulating cover 206A) The thickness on the top. Therefore, in this embodiment, when a portion of the metal-containing buffer layer 207 located above the first portion of the insulating cover 206A is removed, a portion of the metal-containing buffer layer 207 located on the bottom portion 205b of the first opening 205 is removed. While a portion of the second portion of the insulating cap layer 206B is exposed, only a portion of the metal buffer layer 207 remains, covering another portion of the second portion of the insulating cap layer 206B that is located on the first sidewall 205a of the first opening 205. Wherein, a portion of the remaining metal buffer layer 107 may have an L-shaped cross-sectional shape (as shown in FIG. 2D). However, in other embodiments of the present specification, all of the metal-containing buffers 207 on the sidewalls 205a and 205b of the first opening 205 are removed when a portion of the metal-containing buffer layer 207 located above the first portion of the insulating cap layer 206A is removed. May be removed together.
然後,以導電層202為蝕刻停止層,進行另一次蝕刻製程,移除位於第一開口205底部205a的一部分第二部分絕緣覆蓋層206B,使剩餘的第二部分絕緣覆蓋層206B於第一開口205的側壁205a上形成一個間隙壁208,而與導電層202接觸,並在第一開口205中定義出一個第二開口209,藉以將一部份導電層202暴露於外,形成如第2E圖所繪示的接觸開口結構200。其中,餘留下來的含金屬緩衝層107,係位於間隙壁208上,且與暴露於外的導電層104相隔一段距離H2。Then, the conductive layer 202 is used as an etch stop layer, and another etching process is performed to remove a portion of the second partial insulating cover layer 206B located at the bottom 205a of the first opening 205, so that the remaining second portion of the insulating cover layer 206B is in the first opening. A spacer 208 is formed on the sidewall 205a of the 205, and is in contact with the conductive layer 202, and a second opening 209 is defined in the first opening 205, thereby exposing a portion of the conductive layer 202 to the outside, forming a pattern as shown in FIG. The contact opening structure 200 is illustrated. The remaining metal-containing buffer layer 107 is located on the spacer 208 and spaced apart from the exposed conductive layer 104 by a distance H2.
在本實施例中,在形成第二開口209時,並未將第一部份絕緣覆蓋層206A全部移除。剩餘的第一部份絕緣覆蓋層206A的厚度為實質介於50埃至1000埃之間。但在本說明書的一些實施例中,在形成第二開口209時,會將接觸開口結構200’的第一部份絕緣覆蓋層206A全部移除。意即,剩餘的第一部份絕緣覆蓋層206A厚度為0,可將層間介電層204暴露於外(如第2E’圖所繪示)。In the present embodiment, when the second opening 209 is formed, the first partial insulating cover layer 206A is not completely removed. The remaining first portion of the insulating cover layer 206A has a thickness substantially between 50 angstroms and 1000 angstroms. However, in some embodiments of the present specification, the first portion of the insulating cover layer 206A of the contact opening structure 200' will be removed when the second opening 209 is formed. That is, the remaining first portion of the insulating cap layer 206A has a thickness of zero, and the interlayer dielectric layer 204 can be exposed to the outside (as shown in FIG. 2E').
藉由含金屬緩衝層207的保護,可使餘留在第一開口205之第一側壁205a上,用來構成間隙壁208的一部分絕緣覆蓋層206不會受到蝕刻製程的毀損,可精確地控制第二開口209的寬度尺寸,藉以微縮形成在第二開口209中的元件或內連線結構,進而提高整體電路的元件密度。By the protection of the metal-containing buffer layer 207, the first sidewall 205a of the first opening 205 can be left on the first sidewall 205a of the first opening 205, and a portion of the insulating coating 206 for forming the spacer 208 is not damaged by the etching process, and can be accurately controlled. The width dimension of the second opening 209 is used to reduce the component or interconnect structure formed in the second opening 209, thereby increasing the component density of the overall circuit.
請參照第3A圖至第3C圖,第3A圖至第3C圖係繪示應用第2E圖之接觸開口結構200來製作電阻式隨機存取記憶體單元300的製程結構剖面圖。電阻式隨機存取記憶體單元300的製作方法包括下述步驟:首先,形成過渡金屬氧化物(transition metal oxides,TMO)層301覆蓋於經由第二開口209暴露於外的一部份導電層202上,使過渡金屬氧化物層301與導電層202接觸。在本說明書的一些實施例中,構成過渡金屬氧化物層301的材質,可以是金屬氧化物,例如(TaOx)鉭氧化物,鎢氧化物(WOx)、鋡氧化物(HfOx)或上述材料的組合。在本實施例中,過渡金屬氧化物層301並未完全填滿第二開口209(如第3A圖所繪示)。Referring to FIGS. 3A to 3C, FIGS. 3A to 3C are cross-sectional views showing a process structure for fabricating the resistive random access memory cell 300 by applying the contact opening structure 200 of FIG. 2E. The manufacturing method of the resistive random access memory cell 300 includes the following steps: First, a transition metal oxides (TMO) layer 301 is formed to cover a portion of the conductive layer 202 exposed through the second opening 209. The transition metal oxide layer 301 is brought into contact with the conductive layer 202. In some embodiments of the present specification, the material constituting the transition metal oxide layer 301 may be a metal oxide such as (TaOx) tantalum oxide, tungsten oxide (WOx), tantalum oxide (HfOx) or the like. combination. In the present embodiment, the transition metal oxide layer 301 does not completely fill the second opening 209 (as shown in FIG. 3A).
之後,再形成一上方電極層302覆蓋於過渡金屬氧化物層301上,並於上方電極層302上形成金屬材料層303(如第3B圖所繪示)。在本說明書的一些實施例中,構成上方電極層302的材料可以包括氮化鉭。金屬材料層303可以包括鎢(W)。Thereafter, an upper electrode layer 302 is formed overlying the transition metal oxide layer 301, and a metal material layer 303 is formed on the upper electrode layer 302 (as shown in FIG. 3B). In some embodiments of the present specification, the material constituting the upper electrode layer 302 may include tantalum nitride. The metal material layer 303 may include tungsten (W).
接著,以第一部份絕緣覆蓋層206A為停止層,對金屬材料層303、上方電極層302和過渡金屬氧化物層301進行平坦化製程,例如化學機械研磨製程,完成電阻式隨機存取記憶體單元300(如第3C圖所繪示)的製作。在本實施例中,接觸開口結構200中的導電層204,可以作為電阻式隨機存取記憶體單元300的下電極層。Then, the first portion of the insulating cover layer 206A is used as a stop layer, and the metal material layer 303, the upper electrode layer 302, and the transition metal oxide layer 301 are planarized, for example, a chemical mechanical polishing process to complete the resistive random access memory. Fabrication of body unit 300 (as depicted in Figure 3C). In the present embodiment, the conductive layer 204 in the contact opening structure 200 can serve as the lower electrode layer of the resistive random access memory cell 300.
如前所述,由於接觸開口結構200可精確控制第二開口209的寬度尺寸範圍。例如在本實施例中,第二開口209可以具有實質介於5奈米(nm)至50奈米的一底部寬度 BW,以及實質介於10奈米至100奈米的開口寬度OW。因此,形成在第二開口209中的電阻式隨機存取記憶體單元300之尺寸,可微縮至第二開口209的尺寸範圍,大幅增加記憶體元件的儲存密度。As previously mentioned, the contact opening structure 200 can precisely control the width dimension range of the second opening 209. For example, in the present embodiment, the second opening 209 may have a bottom width BW substantially between 5 nanometers (nm) and 50 nanometers, and an opening width OW substantially between 10 nanometers and 100 nanometers. Therefore, the size of the resistive random access memory cell 300 formed in the second opening 209 can be reduced to the size range of the second opening 209, which greatly increases the storage density of the memory element.
請參照第4圖,第4圖係繪示分別應用第2E’圖之接觸開口結構200’所製作之電阻式隨機存取記憶體單元400的結構剖面圖。電阻式隨機存取記憶體單元400的結構與製作方式大致與電阻式隨機存取記憶體單元300類似。差別僅在於,電阻式隨機存取記憶體單元400不具有第一部份絕緣覆蓋層206A。在對金屬材料層303、上方電極層302和過渡金屬氧化物層301進行平坦化製程時,是以層間介電層204作為停止層。由於製作電阻式隨機存取記憶體單元400的其他製程步驟以詳述如上,故不再贅述。Referring to Fig. 4, Fig. 4 is a cross-sectional view showing the structure of a resistive random access memory cell 400 fabricated by applying the contact opening structure 200' of Fig. 2E'. The structure and fabrication of the resistive random access memory cell 400 is substantially similar to that of the resistive random access memory cell 300. The only difference is that the resistive random access memory cell 400 does not have the first partial insulating cap layer 206A. When the metal material layer 303, the upper electrode layer 302, and the transition metal oxide layer 301 are planarized, the interlayer dielectric layer 204 is used as a stop layer. Since other process steps for fabricating the resistive random access memory cell 400 are detailed above, they are not described again.
根據上述實施例,本說明書是在提供一種接觸開口結構及其製作方法,以及應用此一接觸開口結構所製作的電阻式隨機存取記憶體單元。其係先在介電層中形成導電層使其經由第一開口暴露於外。再形成一個絕緣覆蓋層部分地填充第一開口,並在絕緣覆蓋層上覆蓋一個含金屬緩衝層。在移除覆蓋於層間介電層上的一部份含金屬緩衝層之後,將一部分的含金屬緩衝層餘留在第一開口中,藉以覆蓋位於第一開口之側壁上的一部分絕緣覆蓋層。之後,再移除位於第一開口底部的一部分絕緣覆蓋層,藉以在第一開口中定義出一個第二開口,將導電層暴露在外。According to the above embodiment, the present specification is to provide a contact opening structure and a manufacturing method thereof, and a resistive random access memory unit fabricated by using the contact opening structure. It is formed by first forming a conductive layer in the dielectric layer to be exposed to the outside through the first opening. An insulating cover layer is further formed to partially fill the first opening, and a metal-containing buffer layer is covered on the insulating cover layer. After removing a portion of the metal-containing buffer layer overlying the interlayer dielectric layer, a portion of the metal-containing buffer layer remains in the first opening to cover a portion of the insulating cap layer on the sidewall of the first opening. Thereafter, a portion of the insulating cover layer at the bottom of the first opening is removed, thereby defining a second opening in the first opening to expose the conductive layer.
藉由含金屬緩衝層的保護,可使餘留在第一開口側壁上的一部分絕緣覆蓋層不會受到後續蝕刻製程的毀損,可精確地控制第二開口的寬度尺寸,以在層間介電層中形成一個具有較小寬度尺寸的接觸開口。可進一步微縮後續形成在接觸開口中之元件或內連線結構的尺寸,進而提高整體電路的元件密度。By protecting the metal-containing buffer layer, a portion of the insulating coating remaining on the sidewall of the first opening is not damaged by the subsequent etching process, and the width dimension of the second opening can be accurately controlled to be in the interlayer dielectric layer. A contact opening having a smaller width dimension is formed in the middle. The size of the component or interconnect structure that is subsequently formed in the contact opening can be further miniaturized, thereby increasing the component density of the overall circuit.
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何該技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and it is to be understood by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
100、100’、200、200’‧‧‧作接觸開口結構100, 100', 200, 200'‧‧‧ contact opening structure
101、201‧‧‧基材101, 201‧‧‧ substrate
101a、201a‧‧‧基材表面101a, 201a‧‧‧ substrate surface
102、202‧‧‧導電層102, 202‧‧‧ conductive layer
103、203‧‧‧電晶體單元103, 203‧‧‧Optocell unit
103a、203a‧‧‧電晶體單元的源極/汲極103a, 203a‧‧‧Source/drain of the crystal unit
104、204‧‧‧層間介電層104, 204‧‧‧ Interlayer dielectric layer
104A‧‧‧第一部份層間介電層104A‧‧‧The first part of the interlayer dielectric layer
104B‧‧‧第二部分層間介電層104B‧‧‧Second part interlayer dielectric layer
105、205‧‧‧第一開口105, 205‧‧‧ first opening
105a、205a‧‧‧第一開口的第一側壁105a, 205a‧‧‧ first side wall of the first opening
105b、205b‧‧‧第一開口的底部105b, 205b‧‧‧ bottom of the first opening
106、206‧‧‧絕緣覆蓋層106, 206‧‧ ‧ insulating cover
106A、206B‧‧‧第一部分絕緣覆蓋層106A, 206B‧‧‧ first part insulation cover
106B、206B‧‧‧第二部分絕緣覆蓋層106B, 206B‧‧‧Second part insulating cover
107、207‧‧‧含金屬緩衝層107, 207‧‧‧ metal buffer layer
108、208‧‧‧間隙壁108, 208‧‧‧ spacers
109、209‧‧‧第二開口109, 209‧‧‧ second opening
110‧‧‧階梯狀結構110‧‧‧step structure
111、211‧‧‧貫穿孔111, 211‧‧‧through holes
202a‧‧‧導電層的頂部202a‧‧‧Top of the conductive layer
300‧‧‧電阻式隨機存取記憶體單元300‧‧‧Resistive random access memory unit
301‧‧‧過渡金屬氧化物層301‧‧‧Transition metal oxide layer
302‧‧‧上方電極層302‧‧‧Upper electrode layer
303‧‧‧金屬材料層303‧‧‧Metal material layer
H1、H2‧‧‧距離H1, H2‧‧‧ distance
OW‧‧‧開口寬度OW‧‧‧ opening width
BW‧‧‧底部寬度BW‧‧‧ bottom width
D2‧‧‧第一開口的深度D2‧‧‧Deep depth of the first opening
為了對本說明書之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下: 第1A圖至第1E圖係根據本說明書的一實施例繪示製作接觸開口結構的一系列製程結構剖面圖; 第1E’圖係根據本說明書的另一實施例所繪示的接觸開口結構的剖面示意圖; 第2A圖至第2E圖係根據本說明書的又一實施例,繪示製作接觸開口結構的一系列製程結構剖面圖; 第2E’圖係根據本說明書的再一實施例所繪示的接觸開口結構結構剖面圖; 第3A圖至第3C圖係繪示應用第2E圖之接觸開口結構來製作電阻式隨機存取記憶體單元300的製程結構剖面圖;以及 第4圖係繪示分別應用第2E’圖之接觸開口結構所製作之電阻式隨機存取記憶體單元的結構剖面圖。In order to better understand the above and other aspects of the present specification, the following specific embodiments are described in detail below with reference to the accompanying drawings: FIGS. 1A through 1E are diagrams showing contact openings according to an embodiment of the present specification. A series of process structure cross-sectional views of the structure; FIG. 1E' is a schematic cross-sectional view of the contact opening structure according to another embodiment of the present specification; FIGS. 2A to 2E are diagrams according to still another embodiment of the present specification, FIG. 2E′ is a cross-sectional view showing a structure of a contact opening according to still another embodiment of the present specification; FIGS. 3A to 3C are diagrams showing an application. FIG. 4 is a cross-sectional view showing a process structure of the resistive random access memory cell 300; and FIG. 4 is a resistive random access memory fabricated by using the contact opening structure of FIG. 2E respectively. A structural section view of the unit.
無。no.

Claims (10)

  1. 一種接觸開口 (contact hole)結構,包括: 一基材; 一層間介電層,位於該基材之上,且具有一第一開口; 一導電層,位於該層間介電層中,並對準該第一開口;以及 一絕緣覆蓋層,具有位於該第一開口的一第一側壁上的一間隙壁,其中該間隙壁與該導電層接觸,並在該第一開口中定義出一第二開口,藉以將一部份該導電層暴露於外。A contact hole structure comprising: a substrate; an interlayer dielectric layer on the substrate and having a first opening; a conductive layer located in the interlayer dielectric layer and aligned The first opening; and an insulating cover layer having a spacer on a first sidewall of the first opening, wherein the spacer contacts the conductive layer and defines a second in the first opening Opening to expose a portion of the conductive layer to the outside.
  2. 如申請專利範圍第1項所述之接觸開口結構,更包括一含金屬緩衝層,位於該第二開口的一第二側壁上,且與該導電層相隔一距離 ,其中該含金屬緩衝層包括氮化鈦(TiN)、氮化鉭(TaN)、鈦金屬和鉭金屬中至少一者。The contact opening structure of claim 1, further comprising a metal-containing buffer layer on a second sidewall of the second opening and spaced apart from the conductive layer, wherein the metal-containing buffer layer comprises At least one of titanium nitride (TiN), tantalum nitride (TaN), titanium metal, and base metal.
  3. 一種接觸開口結構的製作方法,包括: 提供一基材; 於該基材上形成一層間介電層; 於該層間介電層中形成一導電層,並使至少一部份該導電層經由該層間介電層中的一第一開口暴露於外; 以及 於該層間介電層上形成一絕緣覆蓋層,並延伸進入該第一開口之中; 形成一含金屬緩衝層,以覆蓋該絕緣覆蓋層; 移除位於該層間介電層上方的一部份該含金屬緩衝層;以及 移除位於該第一開口中的一部分該絕緣覆蓋層,以使剩餘的該絕緣覆蓋層在該第一開口的一第一側壁上形成一間隙壁,而與該導電層接觸,藉以在該第一開口中定義出一第二開口,將至少一部份該導電層暴露於外。A method for fabricating a contact opening structure, comprising: providing a substrate; forming an interlayer dielectric layer on the substrate; forming a conductive layer in the interlayer dielectric layer; and allowing at least a portion of the conductive layer to pass through the layer a first opening in the interlayer dielectric layer is exposed to the outside; and an insulating coating layer is formed on the interlayer dielectric layer and extends into the first opening; forming a metal-containing buffer layer to cover the insulating cover Removing a portion of the metal-containing buffer layer over the interlayer dielectric layer; and removing a portion of the insulating cover layer in the first opening such that the remaining insulating cover layer is in the first opening A spacer is formed on a first sidewall to contact the conductive layer, thereby defining a second opening in the first opening to expose at least a portion of the conductive layer to the outside.
  4. 如申請專利範圍第3項所述之接觸開口結構的製作方法,其中該層間介電層包括一第一部份層間介電層和一第二部份層間介電層,且形成該第一開口的步驟,包括: 於該基材上形成該第一部份層間介電層; 於該第一部份層間介電層中形成該導電層; 形成該第二部份層間介電層,覆蓋該第一部份層間介電層和該導電層;以及 移除位於該導電層上方的一部份該第二部份層間介電層。The method of fabricating the contact opening structure of claim 3, wherein the interlayer dielectric layer comprises a first partial interlayer dielectric layer and a second partial interlayer dielectric layer, and the first opening is formed The step of forming: forming the first partial interlayer dielectric layer on the substrate; forming the conductive layer in the first partial interlayer dielectric layer; forming the second partial interlayer dielectric layer, covering the a first portion of the interlayer dielectric layer and the conductive layer; and removing a portion of the second portion of the interlayer dielectric layer over the conductive layer.
  5. 如申請專利範圍第3項所述之接觸開口結構的製作方法,形成該第一開口的步驟,包括: 於該基材上形成該層間介電層; 於該層間介電層中形成該導電層;以及 回蝕該導電層。The method for fabricating the contact opening structure according to claim 3, wherein the forming the first opening comprises: forming the interlayer dielectric layer on the substrate; forming the conductive layer in the interlayer dielectric layer And etch back the conductive layer.
  6. 如申請專利範圍第3項所述之接觸開口結構的製作方法,其中移除位於該第一開口中的該部分該絕緣覆蓋層的同時,完全地移除覆蓋於該層間介電層上的另一部份該絕緣覆蓋層。The method of fabricating the contact opening structure of claim 3, wherein the portion of the insulating cover layer located in the first opening is removed while completely removing the cover layer on the interlayer dielectric layer A portion of the insulating cover.
  7. 如申請專利範圍第3項所述之接觸開口結構的製作方法,其中移除位於該第一開口中的該部分該絕緣覆蓋層的同時,僅部份地移除覆蓋於該層間介電層上的另一部份該絕緣覆蓋層。The method of fabricating the contact opening structure of claim 3, wherein the portion of the insulating cover layer located in the first opening is removed, and only partially removed over the interlayer dielectric layer The other part of the insulating cover.
  8. 如申請專利範圍第3項所述之接觸開口結構的製作方法,其中移除位於該層間介電層上方的該部份該含金屬緩衝層的同時,包括餘留一部份該含金屬緩衝層,部分地覆蓋在該第二開口之一第二側壁上。The method for fabricating a contact opening structure according to claim 3, wherein the portion of the metal-containing buffer layer located above the interlayer dielectric layer is removed, including a portion of the metal-containing buffer layer remaining And partially covering the second side wall of one of the second openings.
  9. 一種電阻式隨機存取記憶體(Resistance. Random Access Memory, ReRAM)單元包括: 一基材; 一層間介電層,位於該基材之上,且具有一第一開口; 一底部電極層,位於該層間介電層中,並對準該第一開口; 一絕緣覆蓋層,具有位於該第一開口的一第一側壁上的一間隙壁,其中該間隙壁與該底部電極層接觸,並在該第一開口中定義出一第二開口; 一過渡金屬氧化物(transition metal oxides,TMO)層,位於該第二開口中,並與該底部電極層接觸;以及 一上方電極層,位於該第二開口中,並與該過渡金屬氧化物層接觸。A Resistance. Random Access Memory (ReRAM) unit includes: a substrate; an interlayer dielectric layer on the substrate and having a first opening; a bottom electrode layer located at The interlayer dielectric layer is aligned with the first opening; an insulating cover layer having a spacer on a first sidewall of the first opening, wherein the spacer is in contact with the bottom electrode layer, and a second opening is defined in the first opening; a transition metal oxides (TMO) layer is disposed in the second opening and is in contact with the bottom electrode layer; and an upper electrode layer is located in the first opening In the two openings, and in contact with the transition metal oxide layer.
  10. 如申請專利範圍第9項所述之電阻式隨機存取記憶體單元,更包括: 一含金屬緩衝層,位於該第二開口的一第二側壁上,且與該導電層相隔一距離,其中該含金屬緩衝層包括氮化鈦、氮化鉭、鈦金屬和鉭金屬中至少一者;以及一金屬-氧化物-半導體場效電晶體(Metal-Oxide-Semiconductor Filed Effect Transistor,MOSFET)單元位於該基材之中,具有一源極/汲極結構,與該底部電極層接觸。The resistive random access memory unit of claim 9, further comprising: a metal-containing buffer layer on a second sidewall of the second opening and spaced apart from the conductive layer, wherein The metal-containing buffer layer comprises at least one of titanium nitride, tantalum nitride, titanium metal and tantalum metal; and a Metal-Oxide-Semiconductor Filed Effect Transistor (MOSFET) unit is located The substrate has a source/drain structure in contact with the bottom electrode layer.
TW106139069A 2017-11-10 2017-11-10 Contact hole structure mrthod for fabricting the same and applications thereof TWI641096B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW106139069A TWI641096B (en) 2017-11-10 2017-11-10 Contact hole structure mrthod for fabricting the same and applications thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW106139069A TWI641096B (en) 2017-11-10 2017-11-10 Contact hole structure mrthod for fabricting the same and applications thereof

Publications (2)

Publication Number Publication Date
TWI641096B TWI641096B (en) 2018-11-11
TW201919173A true TW201919173A (en) 2019-05-16

Family

ID=65034283

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106139069A TWI641096B (en) 2017-11-10 2017-11-10 Contact hole structure mrthod for fabricting the same and applications thereof

Country Status (1)

Country Link
TW (1) TWI641096B (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8107274B2 (en) * 2009-07-30 2012-01-31 Chrong-Jung Lin Variable and reversible resistive element, non-volatile memory device and methods for operating and manufacturing the non-volatile memory device
CN105990394A (en) * 2015-02-26 2016-10-05 旺宏电子股份有限公司 Storage component and manufacture method thereof
US10068844B2 (en) * 2015-09-30 2018-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US9947610B2 (en) * 2016-01-28 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method for manufacturing the same

Also Published As

Publication number Publication date
TWI641096B (en) 2018-11-11

Similar Documents

Publication Publication Date Title
TWI594405B (en) Integrated circuit and method for forming the same
US10109793B2 (en) Bottom electrode for RRAM structure
CN106252505B (en) RRAM device and method
US20190074440A1 (en) Memory device having via landing protection
KR102146761B1 (en) Recap layer scheme to enhance rram performance
TWI635578B (en) Methods of fabricating an f-ram
TWI739174B (en) Memory cell and method for manufacturing the same
TW201227879A (en) Semiconductor device with MIM capacitor and method for manufacturing the same
TWI695498B (en) Integrated chip and method of forming thereof
JP6510678B2 (en) Method of fabricating ferroelectric random access memory on pre-patterned bottom electrode and oxidation barrier
TW201820424A (en) An embedded memory device with a composite top electrode
KR102106957B1 (en) Resistive random-access memory(rram) cell with recessed bottom electrode sidewalls
US20210351349A1 (en) Top electrode last scheme for memory cell to prevent metal redeposit
US9960349B2 (en) Resistive random-access memory structure and method for fabricating the same
TWI641096B (en) Contact hole structure mrthod for fabricting the same and applications thereof
JP2007227500A (en) Semiconductor memory device, and fabrication process of semiconductor memory device
CN109801938B (en) Contact opening structure, manufacturing method and application thereof
US10490744B2 (en) Contact hole structure method for fabricating the same and applications thereof
TWI607592B (en) semiconductor device INCLUDING A MEMORY CELL STRUCTURE
KR20210038824A (en) Middle-of-line interconnect structure and manufacturing method
TW202131533A (en) Integrated chip, memory device and method of forming the same
TWI607591B (en) ResistANce Switching Memory Device And Method Of Manufacturing The Same
KR20040080573A (en) Method for manufacturing semiconductor device
CN113745238A (en) Three-dimensional memory device and method
TW201633575A (en) Memory device and method for fabricating the same