CN105990394A - Storage component and manufacture method thereof - Google Patents

Storage component and manufacture method thereof Download PDF

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Publication number
CN105990394A
CN105990394A CN201510087796.3A CN201510087796A CN105990394A CN 105990394 A CN105990394 A CN 105990394A CN 201510087796 A CN201510087796 A CN 201510087796A CN 105990394 A CN105990394 A CN 105990394A
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China
Prior art keywords
layer
alcove
memory
contact area
sidewall
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Pending
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CN201510087796.3A
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Chinese (zh)
Inventor
林昱佑
李峰旻
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Macronix International Co Ltd
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Macronix International Co Ltd
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Priority to CN201510087796.3A priority Critical patent/CN105990394A/en
Publication of CN105990394A publication Critical patent/CN105990394A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a storage component which comprises a substrate, a first electrode layer, a gap wall, a storage layer and a second storage layer. The substrate includes a recessed cavity. The first electrode is placed in the recessed cavity, and includes an upper surface exposed out of an opening of the recessed cavity. The gap wall covers part of the upper surface to define a contact area in the upper surface. The storage layer is formed on the contact area. The second electrode layer is formed on the storage layer, and makes electrical contact with the storage layer.

Description

Memory element and preparation method thereof
Technical field
The present invention relates to semiconductor element and preparation method thereof, particularly a kind of variable resistance type storage (Resistive random-access memory, ReRAM) element and preparation method thereof.
Background technology
Non-volatile memories (Non-Volatile Memory, NVM) element, has when removing power supply The most do not lose the characteristic of the information being stored in memory element.Being belonging to of being relatively widely used at present is adopted Store with the electric charge storage type quick flashing (Charge Trap Flash, CTF) of electric charge storage type (charge trap) Element.But, along with the integration density of memory element increases, element critical size (critical size) With interval (pitch) reduces, electric charge storage type flash element faces its physics limit, and cannot action.
Variable resistance type memory element, is to utilize the size of memory element resistance to be used as information to store shape The interpretation foundation of state.No matter it is in component density (device density), power consumption, sequencing/smear Except in speed or three dimensions stack properties, better than flash memory.Therefore, extremely industry has the most been become One of memory element paid close attention to.
Typical changing resistor type memory element include the lower metal electrode layer/accumulation layer of a vertical stacking/ Upper metal electrode layer stacked structure.Crossings on different level bar array structure (crossbar array can be realized Configuration) high density storage.In order to increase the combination between metal electrode layer and base material, existing Some changing resistor type memory elements, typically first can form an alcove on base material, then bottom alcove with Sidewall forms a barrier layer, such as titanium nitride (TiN) barrier layer.Again with metal material, such as tungsten (W), Fill this alcove, form lower metal electrode layer, electric at lower metal with oxidation or depositing operation afterwards The top surface of pole layer forms metal oxide layer, as accumulation layer, then on metal oxide layer overlying lid Metal electrode layer.
But, the accumulation layer formed by oxidation or depositing operation, it is difficult to intactly cover lower metal The top surface of electrode layer, may be by the top surface of lower metal electrode layer near the angle of alcove sidewall Fall outside (comprising a part of barrier layer) be exposed to.Cause, the follow-up upper metal electricity being covered in accumulation layer Pole layer meeting and lower metal electrode layer and/or barrier layer form electrical connection, and produce electrical leakage problems and even make Become component failure.
Therefore, it is necessary to provide a kind of more advanced memory element and preparation method thereof, existing to improve Technology problem encountered.
Summary of the invention
It is an aspect of the invention to provide a kind of memory element, this memory element includes: base material, the One electrode layer, clearance wall, accumulation layer and the second electrode lay.Wherein, base material has an alcove. First electrode layer is positioned among alcove, has one and is exposed to outer upper surface by pocket open.Gap Wall covers a part of upper surface, to define a contact area on this upper surface.Accumulation layer is formed at and connects Touch in district.The second electrode lay, is formed in accumulation layer, and in electrical contact with accumulation layer.
Another aspect of the present invention is to provide the manufacture method of a kind of memory element, the system of this memory element Comprise the steps: first to provide a base material with at least one alcove, and shape in alcove as method Become the first electrode layer, make the first electrode layer have one and be exposed to outer upper surface by the opening of alcove. Then, form clearance wall, cover a part of upper surface, to define a contact area on an upper. Then, contact area forms an accumulation layer.Follow-up, accumulation layer is formed the second electrode lay, makes The second electrode lay is in electrical contact with accumulation layer.
According to above-mentioned aspect, it is desirable to provide a kind of memory element and preparation method thereof.The method It is first in the alcove of base material, to form the first electrode layer, then form a clearance wall, is covered in the first electricity The upper surface of pole layer, to define a contact area.In contact area, form accumulation layer again, form second Electrode layer covers accumulation layer.The first electrode layer is covered by the clearance wall being formed on alcove sidewall Upper surface, near the corner of alcove sidewall, can reach to prevent because accumulation layer covers not exclusively, causes the Two electrode layers and the first electrode layer or and barrier layer (if having) produce unexpected in electrical contact.Solve existing Have memory element therefore and leak electricity cause inefficacy problem.
Accompanying drawing explanation
In order to the above embodiment of the present invention and other objects, features and advantages can be become apparent, Especially exemplified by several preferred embodiments, and coordinate accompanying drawing, be described in detail below:
Figure 1A to Fig. 1 F is the making variable resistance type storage drawn according to one embodiment of the invention The series of process structural profile schematic diagram of element;And
Fig. 2 A to Fig. 2 E is that the making variable resistance type drawn according to another embodiment of the present invention is deposited The series of process structural profile schematic diagram of storage element.
[description of reference numerals]
100: variable resistance type memory element 101: base material
101a: base semiconductor layer 101b: insulating barrier
101c: substrate surface 102: alcove
102a: pocket open 102b: alcove sidewall
103: barrier layer 104: the first electrode layer
The upper surface of the 104a: the first electrode layer
Interface between 105: the first electrode layers and barrier layer
106: clearance wall 107: accumulation layer
108: the second electrode lay
200: variable resistance type memory element
201: dielectric layer 202: through hole
203: barrier layer 204: the first electrode layer
The upper surface of the 204a: the first electrode layer
Interface between 205: the first electrode layers and barrier layer
206: clearance wall 207: accumulation layer
208: the second electrode lay A1: contact area
A2: contact area
Distance between D1: contact area and alcove sidewall
Distance between D2: contact area and alcove sidewall
Detailed description of the invention
The present invention provides a kind of memory element and preparation method thereof, it is possible to resolve existing memory element is because of storage Layer covers not exclusively, results in unexpected electrical leakage problems.In order to aforementioned aspect of the present invention and Other objects, features and advantages can become apparent, several solid storing elements cited below particularly and making thereof Method as the presently preferred embodiments, and coordinates accompanying drawing to elaborate.
But must be noted that these specific embodiment and methods, be not limited to the present invention. The present invention still can use other features, element, method and parameter to be carried out.Preferred embodiment Propose, be only the technical characteristic illustrating the present invention, be not limited to the patent protection of the present invention Scope.Those of ordinary skill in the art, can be according to description below, without departing from this In bright scope, make modification and the change being equal to.In different embodiments and accompanying drawing, identical Element will be represented with identical reference.
Refer to Figure 1A to Fig. 1 F, Figure 1A to Fig. 1 F is to be drawn according to one embodiment of the invention Make variable resistance type memory element 100 series of process structural profile schematic diagram.Make variable The method of resistive memory element 100 comprises the steps: first to provide and has at least one alcove 102 Base material 101.Among some embodiments of the present invention, base material 101 can be to include that basis is partly led Body layer 101a and the insulating barrier 101b being positioned in base semiconductor layer 101a.Alcove 102 is by position In the opening 102a of insulating barrier 101b (base material 101) surface 101c, extend vertically downward into into insulating barrier Among 101b (as shown in Figure 1A).
Among some embodiments of the present invention, basis semiconductive layer 101a include by polysilicon structure or Any applicable semiconductor material, the germanium of such as crystalline state;Compound semiconductor, such as carborundum, GaAs, gallium phosphide, Echothiopate Iodide, arsenic iodine and/or antimony iodine, or the crystalline substance that combinations of the above is constituted Circle.Among the present embodiment, base material 101 is the wafer being made up of polysilicon.Insulating barrier 101b Including silicon dioxide (SiO2)。
Then, alcove 102 forms the first electrode layer 104, make the first electrode layer 104 have one Individual it is exposed to outer upper surface 104a (as shown in Figure 1B) by the opening 102a of alcove 102.At this Among some bright embodiments, the first electrode layer 104 can pass through depositing operation, such as low pressure chemical gas Deposition (LoW Pressure Chemical Vapor Deposition, LPCVD) technique mutually, or other conjunctions Suitable technique is made.The material constituting the first electrode layer 104 can include, copper (Cu), aluminum (A1), Tungsten (W), titanium (Ti) or other possible metal or non-metallic conducting material.Among the present embodiment, structure The material becoming the first electrode layer 104 is preferably tungsten.
In the other embodiment of the present invention, before forming the first electrode layer 104, it is preferably The bottom of alcove 102 and sidewall 102b are formed a barrier layer 103.(as shown in Figure 1B).Resistance Barrier 103 also can be passed through depositing operation, such as low-pressure chemical vapor deposition process and be made.Constitute The material on barrier layer 103 can include titanium nitride (TiN).
Then, barrier layer 103 first electrode layer 104 is carried out an etch-back technics, will be close to alcove 102 Outside a part of alcove 102 sidewall 102b of opening 102a is exposed to, and make the first electrode layer 104 Upper surface 104a less than the opening 102a (as shown in Figure 1 C) of alcove 102.In the present embodiment, The upper surface on barrier layer 103 is also below the opening 102a of alcove 102, the first electrode layer 104 and stop Interface 105 between layer 103, outside being also exposed to via alcove 102 opening 102a.
Afterwards, form clearance wall 106 and cover the upper surface 104a of a part of first electrode layer 104, with Upper surface 104a defines a contact area A1 (as shown in Fig. 1 D schemes).Wherein, clearance wall 106 Be formed at alcove 102 to be exposed on outer sidewall 102b, and with the first electrode layer 104 and stopping Layer 103 contact.Among some embodiments of the present invention, clearance wall 106 can pass through depositing operation, Such as low-pressure chemical vapor deposition process is made.The material constituting clearance wall 106 can be nitridation Silicon (SiN), silicon oxide (SiO), silicon oxynitride (SiON) or other possible dielectric materials.
Among the present embodiment, clearance wall 106 is to be made up of silicon nitride.Wherein, clearance wall 106 Interface 105 between covering barrier layer 103 and the first electrode layer 104 and barrier layer 103;And with Ring style covers a part of upper surface 104a of the first electrode layer 104, to be exposed by contact area A1 In outward.Wherein, the size being smaller in size than alcove 102 of contact area A1.In other words, contact area Between A1 and barrier layer 103, and between the sidewall 102b of contact area A1 and alcove 102, phase Away from there being a segment distance.
Then, contact area A1 forms an accumulation layer 107.Some embodiments of the present invention it In, accumulation layer 107 can comprise metal-oxide, such as tungsten oxide (WOx) or oxide (HfOx).In some embodiments of the invention, formed accumulation layer 107 step, can include into Row one depositing operation, to form gold on the upper surface 104a of the first electrode layer 104 in contact area A1 Belong to oxide layer.But in other embodiments of the present invention, oxidation technology, the hottest oxygen can be passed through Metallization processes, the first electrode layer 104 that direct oxidation is positioned in contact area A1, on upper surface 104a Form metal oxide layer.
In the present embodiment, the formation of accumulation layer 107 includes carrying out one around oxidation technology, in contact area A1 forms tungsten oxide (WO on the upper surface 104a of the first electrode layer 104x) layer.According further to Above-mentioned, owing to accumulation layer 107 is formed on contact area A1, therefore accumulation layer 107 and barrier layer 103 Between, and between the sidewall 102b of accumulation layer 107 and alcove 102, the most apart have a segment distance (as Shown in Fig. 1 E).In the preferred embodiment of the present invention, contact area A1 and alcove 102 sidewall 102b Between distance D1 be substantially greater than 5 nanometers (nm).
Follow-up, accumulation layer 107 is formed the second electrode lay 108, makes the second electrode lay 108 and deposit Reservoir 107 (as shown in fig. 1f) in electrical contact, completes the preparation of variable resistance type memory element 100. Wherein, the manufacture method of the second electrode lay 108 and material and the manufacture method of the first electrode layer 104 and Material can be identical or different.And among the present embodiment, the second electrode lay 108 is also by deposition Technique, such as low-pressure chemical vapor deposition process are made.Constitute the material of the second electrode lay 108 Also tungsten is included.
Referring again to Fig. 1 F, preceding method the variable resistance type memory element 100 prepared may include that Base material 101, barrier layer the 103, first electrode layer 104, clearance wall 106, accumulation layer 107 and Two electrode layers 108.Wherein, base material 101 has an alcove 102.First electrode layer 104 is positioned at Among alcove 102, there is one and be exposed to outer upper surface 104a by alcove 102 opening 102a. Barrier layer 103 is positioned on the sidewall 102a of alcove 102, and makes the first electrode layer 104 and base material 101 Isolation.Gap 106 wall covering barrier layer 103 and a part of upper surface 104a of the first electrode layer 104, To define a contact area A1 on this upper surface 104a.Accumulation layer 107 is formed at contact area A1 On.The second electrode lay 108, is formed in accumulation layer 107, and in electrical contact with accumulation layer 108.
Refer to Fig. 2 A to Fig. 2 E, Fig. 2 A to Fig. 2 E is institute according to another embodiment of the present invention The series of process structural profile schematic diagram making variable resistance type memory element 200 drawn.Make The method of variable resistance type memory element 200 comprises the steps: first to provide and has at least one alcove The base material 101 of 102.Owing to preparing base material 101 material of variable resistance type memory element 100 and 200 Matter is identical with structure, so not repeating at this.The method making variable resistance type memory element 200 connects Continuous Figure 1A and by Fig. 2 A.
In alcove 102, form the first electrode layer 204, make the first electrode layer 204 have one by recessed The opening 102a of room 102 is exposed to outer upper surface 204a.In other embodiment, formed Before first electrode layer 204, the most also can form one on the bottom of alcove 102 and sidewall 102b Barrier layer 203 (as shown in Figure 2 A).Owing to making the first electrode layer 204 and the method on barrier layer 203 Describe in detail as above with material, therefore do not repeat at this.
Then, the surface 101c of insulating barrier 101b (base material 101) forms a dielectric layer 201, and And pattern dielectric layer 201, with formed at least one through hole 202 around alcove 102 opening 102a, It is exposed to the surface 101c and whole opening 102a by the insulating barrier 101b (base material 101) of a part Outward (as shown in Figure 2 B).Among some embodiments of the present invention, dielectric layer 201 can be by deposition work Skill, such as low-pressure chemical vapor deposition process are made.The material constituting dielectric layer 201 can be Silicon nitride, silicon oxide, silicon oxynitride, carborundum or other possible dielectric materials.At the present embodiment Among, dielectric layer 201 is made up of silicon nitride.
Afterwards, form clearance wall 206 and cover the upper surface 204a of a part of first electrode layer 204, with Upper surface 204a defines a contact area A2 (as shown in Figure 2 C).Wherein, clearance wall 106 It is formed on the sidewall 202a of through hole 202, and extends in alcove 102, and electric with first Pole layer 204 contacts with barrier layer 203.Among the present embodiment, clearance wall 206 covering barrier layer 203 And the interface 205 that first between electrode layer 204 and barrier layer 203;And cover the with ring style A part of upper surface 204a of one electrode layer 204, outside being exposed to contact area A2.Wherein, connect Touch the size being smaller in size than alcove 102 of district A2.In other words, contact area A2 and barrier layer 203 Between, and between the sidewall 102b of contact area A2 and alcove 102, apart have a segment distance.
Then, contact area A2 forms an accumulation layer 207.Owing to accumulation layer 207 is to be formed at On contact area A2, therefore between accumulation layer 207 and barrier layer 203, and accumulation layer 207 is with recessed Between the sidewall 102b of room 102, the most apart there is a segment distance (as shown in Figure 2 D).In the present invention A preferred embodiment in, the distance D2 essence between contact area A2 and alcove 102 sidewall 102b More than 5 nanometers (nm).
Follow-up, accumulation layer 207 is formed the second electrode lay 208, makes the second electrode lay 208 and deposit Reservoir 207 (as shown in Figure 2 E) in electrical contact, completes the preparation of variable resistance type memory element 200.
Referring again to Fig. 2 E, preceding method the variable resistance type memory element 200 prepared can wrap Include: base material 101, dielectric layer 201, barrier layer the 203, first electrode layer 204, clearance wall 206, Accumulation layer 207 and the second electrode lay 208.Wherein, base material 101 has an alcove 102.The One electrode layer 204 is positioned among alcove 102, has one and is exposed to by alcove 102 opening 102a Outer upper surface 204a.Barrier layer 203 is positioned on the sidewall 102a of alcove 102, and makes the first electricity Pole layer 204 is isolated with base material 101.Dielectric layer 201 is positioned on base material 101, has around alcove One through hole 202 of 102.Clearance wall 206 is formed on the sidewall of through hole 202, and extends into recessed In room 102, and covering barrier layer 203 and a part of upper surface 204a of the first electrode layer 204, with This upper surface 204a defines a contact area A2.Accumulation layer 207 is formed on contact area A2. The second electrode lay 208, is formed in accumulation layer 207, and in electrical contact with accumulation layer 208.
According to above-described embodiment, the invention provides a kind of memory element and preparation method thereof.It first exists The alcove of base material is formed the first electrode layer, then forms a clearance wall, be covered in the first electrode layer Upper surface, to define a contact area.In contact area, form accumulation layer again, form the second electrode lay Cover accumulation layer.The upper surface of the first electrode layer is covered by the clearance wall being formed on alcove sidewall Near the corner of alcove sidewall, can reach to prevent from, because accumulation layer covers not exclusively, causing the second electrode Layer and the first electrode layer or and barrier layer (if having) produce unexpected in electrical contact.Solve existing storage The element therefore problem that electric leakage causes inefficacy.
Particular embodiments described above, is carried out the purpose of the present invention, technical scheme and beneficial effect Further describe it should be understood that the foregoing is only the specific embodiment of the present invention, Be not limited to the present invention, all within the spirit and principles in the present invention, any amendment of being made, Equivalent, improvement etc., should be included within the scope of the present invention.

Claims (17)

1. a memory element, including:
One base material, has an alcove;
One first electrode layer, is positioned in this alcove, and has a upper surface, by an opening of this alcove Outside being exposed to;
One clearance wall, covers this upper surface of a part, to define a contact area on this upper surface;
One accumulation layer, is formed on this contact area;And
One the second electrode lay, is formed in this accumulation layer, and in electrical contact with this accumulation layer.
2. memory element as claimed in claim 1, it is characterised in that also include: a barrier layer, It is positioned on the sidewall of this alcove, and makes this first electrode layer isolate with this base material, and this clearance wall covers This barrier layer.
3. memory element as claimed in claim 2, it is characterised in that this upper surface is opened less than this Mouthful, and this clearance wall is formed on the sidewall of this alcove, and with this barrier layer and this upper surface.
4. memory element as claimed in claim 2, it is characterised in that also include a dielectric layer, It is positioned on this base material, there is the through hole around this alcove;Wherein this clearance wall is formed at this through hole Sidewall on, and extend into this alcove, and with this barrier layer and this upper surface.
5. memory element as claimed in claim 1, it is characterised in that this contact area has and is less than The size of this alcove.
6. memory element as claimed in claim 1, it is characterised in that this contact area and this alcove Sidewall between, there is the distance more than 5 nanometers (nm).
7. memory element as claimed in claim 1, it is characterised in that this base material includes titanium dioxide Silicon (SiO2);This first electrode layer and this second electrode lay include tungsten (W);This accumulation layer includes that tungsten aoxidizes Thing (WOx) or oxide (HfOx);And this clearance wall includes silicon nitride (SiN).
8. a manufacture method for memory element, including:
One base material is provided, makes this base material have an alcove;
In this alcove, form one first electrode layer, make this first electrode layer, there is a upper surface, by Outside one opening of this alcove is exposed to;
Form a clearance wall, cover this upper surface of a part, to define a contact on this upper surface District;
This contact area is formed an accumulation layer;And
This accumulation layer is formed a second electrode lay, makes this second electrode lay be electrically connected with this accumulation layer Touch.
9. the manufacture method of memory element as claimed in claim 8, it is characterised in that recessed at this Before room is formed this first electrode layer, it is additionally included on the sidewall of this alcove and forms a barrier layer.
10. the manufacture method of memory element as claimed in claim 7, it is characterised in that formed Also include before this clearance wall this first electrode layer and this barrier layer being carried out an etch-back technics, by one Outside this sidewall dividing this alcove is exposed to, and make this upper surface less than this opening.
The manufacture method of 11. memory elements as claimed in claim 10, it is characterised in that between Gai Gap wall is formed on the sidewall of this alcove, and with this barrier layer and this upper surface.
The manufacture method of 12. memory elements as claimed in claim 8, it is characterised in that formed Also include before this clearance wall:
A dielectric layer is formed on this base material;And
Pattern this dielectric layer, form the through hole around this alcove.
The manufacture method of 13. memory elements as claimed in claim 12, it is characterised in that between Gai Gap wall is formed on the sidewall of this through hole, and extends into this alcove, and with this barrier layer and table on this Face contacts.
The manufacture method of 14. memory elements as claimed in claim 8, it is characterised in that being formed should The step of accumulation layer, carries out a thermal oxidation technology including to this contact area, with being somebody's turn to do in this contact area Upper surface forms a metal oxide layer.
The manufacture method of 15. memory elements as claimed in claim 8, it is characterised in that being formed should The step of accumulation layer, including carrying out a depositing operation, to be formed on this upper surface in this contact area One metal oxide layer.
The manufacture method of 16. memory elements as claimed in claim 8, it is characterised in that being formed should The step of clearance wall, has the size less than this alcove including making this contact area.
The manufacture method of 17. memory elements as claimed in claim 16, it is characterised in that this connects Touch between district and the sidewall of this alcove, there is the distance more than 5 nanometers.
CN201510087796.3A 2015-02-26 2015-02-26 Storage component and manufacture method thereof Pending CN105990394A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108134008A (en) * 2016-12-01 2018-06-08 旺宏电子股份有限公司 Electric resistance transition memory element and its manufacturing method
TWI641096B (en) * 2017-11-10 2018-11-11 旺宏電子股份有限公司 Contact hole structure mrthod for fabricting the same and applications thereof
CN109801938A (en) * 2017-11-15 2019-05-24 旺宏电子股份有限公司 Contact openings structure and production method and its application
US10490744B2 (en) 2017-11-07 2019-11-26 Macronix International Co., Ltd. Contact hole structure method for fabricating the same and applications thereof

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US20080090400A1 (en) * 2006-10-17 2008-04-17 Cheek Roger W Self-aligned in-contact phase change memory device
CN101226771A (en) * 2007-01-19 2008-07-23 旺宏电子股份有限公司 Multilevel-cell memory structures employing multi-memory layers with tungsten oxides and manufacturing method
CN103594619A (en) * 2012-08-13 2014-02-19 中芯国际集成电路制造(上海)有限公司 Phase change memory and formation method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080090400A1 (en) * 2006-10-17 2008-04-17 Cheek Roger W Self-aligned in-contact phase change memory device
CN101226771A (en) * 2007-01-19 2008-07-23 旺宏电子股份有限公司 Multilevel-cell memory structures employing multi-memory layers with tungsten oxides and manufacturing method
CN103594619A (en) * 2012-08-13 2014-02-19 中芯国际集成电路制造(上海)有限公司 Phase change memory and formation method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108134008A (en) * 2016-12-01 2018-06-08 旺宏电子股份有限公司 Electric resistance transition memory element and its manufacturing method
CN108134008B (en) * 2016-12-01 2021-06-29 旺宏电子股份有限公司 Resistance conversion memory element and manufacturing method thereof
US10490744B2 (en) 2017-11-07 2019-11-26 Macronix International Co., Ltd. Contact hole structure method for fabricating the same and applications thereof
TWI641096B (en) * 2017-11-10 2018-11-11 旺宏電子股份有限公司 Contact hole structure mrthod for fabricting the same and applications thereof
CN109801938A (en) * 2017-11-15 2019-05-24 旺宏电子股份有限公司 Contact openings structure and production method and its application

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Application publication date: 20161005