TWI607591B - ResistANce Switching Memory Device And Method Of Manufacturing The Same - Google Patents

Description

Resistance conversion memory element and method of manufacturing same

The present invention relates to a memory element and a method of fabricating the same, and more particularly to a resistance switching memory device and a method of fabricating the same.

A Resistive random-access memory (RRAM or ReRAM) component is a non-volatile memory component. Resistive memory components are highly regarded by the industry due to their simple metal-insulator-metal (MIM, Metal-Insulator-Metal) structure and scale scalability. At present, there are many different forms of ReRAM from perovskites to transition metal oxides to chalcogenides depending on the dielectric materials used and the memory layer materials. The component is presented.

The resistance-switching memory element is one example of a transition metal oxide memory element, which is a group of bistable bistable memory devices that can store data by different resistance states. For example, a code The type of ReRAM device includes a tungsten bottom electrode, a tungsten germanium oxide (WSixOy) memory layer, and a titanium nitride (TiN) top electrode. In the conventional process, titanium oxynitride (TiONx) may be formed beside the resistance conversion layer (i.e. memory layer) and have a non-negligible effect on the conversion characteristics of the memory element. Therefore, the related industry has no desire to develop and realize a resistance-switching memory element having excellent structural stability and electronic characteristics such as good stability of data storage.

The present invention relates to a resistance-switching memory element and a method of fabricating the same, which provide a raised bottom electrode and a bottom electrode without titanium oxynitride (TiON) forming and smoothing the upper surface, which can effectively enhance the resistance-switching memory element. Stability and electrical performance. .

According to an embodiment, a resistance conversion memory element is provided, comprising: an insulating layer having an upper surface; a bottom electrode buried in the insulating layer, one of the bottom electrodes protruding above the upper surface of the insulating layer, and the upper portion The edge has a rounded corner; a resistance conversion layer is disposed on the bottom electrode; and a top electrode is formed on the resistance conversion layer and covers the resistance conversion layer.

According to an embodiment, there is further provided a resistance-switching memory device, comprising: an insulating layer having an upper surface; a raised bottom electrode buried in the insulating layer and protruding over the upper surface of the insulating layer; spacers a side wall surrounding an upper portion of the bottom electrode of the protrusion; a resistance conversion layer disposed on the bottom electrode of the protrusion; and a top electrode formed on the resistance conversion layer, and the top electrode covering the resistance conversion layer and the spacer.

According to an embodiment, there is provided a resistance-switching memory device, comprising: providing an insulating layer having a hole; forming a hole in which a bottom electrode fills the insulating layer, wherein an upper portion of the bottom electrode protrudes above the insulating layer, and The upper edge has a rounded corner; a resistive conversion layer is disposed on the bottom electrode; and a top electrode is formed on the resistance conversion layer and covers the resistance conversion layer.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.

11‧‧‧Insulation

112‧‧‧ hole

11a‧‧‧Top surface of insulation

12‧‧‧Electrical barrier

121‧‧‧First barrier layer

122‧‧‧Second barrier layer

T1‧‧‧First barrier thickness

T2‧‧‧second barrier thickness

13‧‧‧ bottom electrode

130‧‧‧conductive plug

130U‧‧‧layer of conductive material

130U’‧‧‧ patterned conductive material layer

131‧‧‧Under the bottom electrode

132‧‧‧Top part of the bottom electrode

132a‧‧‧ Upper surface of the upper part of the bottom electrode

132b‧‧‧ sidewall of the bottom electrode

T _BY ‧‧‧ thickness of the upper part

15‧‧‧ clearance

150, 162‧‧‧ dielectric layer

152‧‧‧Oxide film

Ts‧‧‧ thickness of the spacer

16‧‧‧resistive conversion layer

16c‧‧‧ bottom surface of the resistance conversion layer

161‧‧‧metal oxide layer

18‧‧‧ top electrode

19‧‧‧Oxygen storage layer

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a resistive switching memory device of an embodiment.

2A to 2H-1 (/2H-2) A method of manufacturing a resistance-switching memory element according to an embodiment of the present disclosure.

FIG. 3A is a schematic view showing a resistance conversion memory element of another embodiment.

FIG. 3B is a schematic view showing a resistance-switching memory device according to still another embodiment.

FIG. 4 is a schematic view showing a resistance conversion memory element according to still another embodiment of the present invention.

According to an embodiment of the present disclosure, a resistance switching memory device and a method of fabricating the same are provided. The resistance-switching memory device of the embodiment has a raised bottom electrode and no TiON is formed, and the bottom electrode has a smooth top surface and an electrical field enhanced corner, thereby enhancing The resulting resistance converts the stability and electrical performance of the memory component. Furthermore, the manufacturing method proposed in the embodiment not only improves the properties of the related components (for example, the prepared bottom electrode has a smooth upper surface), but also applies an embodiment to form a resistance conversion layer having a self-aligned structure. .

Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings to describe the related configurations and manufacturing methods. Relevant structural details such as related layers and spatial configurations are as described in the following examples. However, the disclosure is not limited to the description, and the disclosure does not show all possible embodiments. The same or similar reference numerals in the embodiments are used to designate the same or similar parts. Furthermore, other implementations not presented in this disclosure may also be applicable. Variations and modifications of the structure of the embodiments can be made in the relevant embodiments without departing from the spirit and scope of the disclosure. The drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to scale in terms of actual products. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

Furthermore, the ordinal used in the specification and the request item, for example, The words "a", "second", "third", etc., are used to modify the elements of the claim, and are not intended to represent any prior ordinal of the claim element. The order of the requesting elements, or the order of the manufacturing methods, is used only to enable a requesting element having a certain name to be clearly distinguished from another requesting element having the same name.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a resistive switching memory device of an embodiment. In one embodiment, the resistance-switching memory device includes an insulating layer 11 (eg, an inter-layered dielectric (ILD)) having a hole 112, a bottom electrode 13 formed on the bottom electrode 13. A resistance switching layer 16, and a top electrode 18 formed on the resistance conversion layer 16 and covering the resistance conversion layer 16. According to an embodiment, the bottom electrode 13 is buried in the insulating layer 11 and protrudes above the insulating layer 11 (i.e. the bottom electrode 13 has a concave profile). As shown in Fig. 1, the bottom electrode 13 can be regarded as a combination of a lower portion 131 buried in the insulating layer 11 and an upper portion 132 protruding from the upper surface 11a of the insulating layer 11 (ie The dotted line drawn in Fig. 1 indicates the upper portion 132) which protrudes from the upper surface 11a of the insulating layer 11. The upper surface 132a of the upper portion 132 of the bottom electrode 13 has a substantially smooth surface and is higher than the upper surface 11a of the insulating layer 11. The edges of the upper portion 132a of the bottom electrode 13 have round corners at edges. Moreover, according to the element structure of the embodiment, the resistance conversion layer 16 is located at a higher horizontal level than the insulating layer 11, and thus the bottom surface 16c of the resistance conversion layer 16 is higher than the insulating layer 11. Surface 11a. Furthermore, Figure 1 only draws a single layer structure. The resistance conversion layer 16 is a simplified representation of one of the embodiments of the present disclosure, but the disclosure is not limited to such an aspect. According to an embodiment, the resistance conversion layer 16 may be a single layer structure or a bilayer structure, depending on the requirements of the application, and may be formed by a slightly changed method in practical applications. Single or double layer structure. In one embodiment, the resistance conversion layer 16 can be a self-aligned bilayer structure (as described in the embodiment of FIG. 2A - FIG. 2H-1 below).

Furthermore, the resistance-switching memory element further includes spacers 15 formed on the insulating layer 11 adjacent to the bottom electrode 13; for example, the spacer 15 is formed (eg, surrounding) at the sidewall 132a of the upper portion 132 of the bottom electrode 13 Wherein the top electrode 18 covers the resistance conversion layer 16 and the spacer 15 . According to the embodiment, the side wall 132b of the bottom electrode 13 is completely covered by the thick spacer 15, so that the gap between the top electrode 18 and the side wall 132b of the bottom electrode 13 can be electrically insulated by the presence of the spacer 15. Since the spacer 15 covers the sidewall 132b of the bottom electrode 13, the resistance conversion of the embodiment elements can be completed in the intermediate portion of the resistance conversion layer 16. In one embodiment, the thickness ts of the spacer 15 is, for example, but not limited to, between 20 Å and 50 Å. In one embodiment, the thickness of the resistance conversion layer 16 is, for example, but not limited to, between 15 Å and 70 Å.

Furthermore, the resistance-switching memory device of the embodiment further includes a conductive barrier 12 to partition the insulating layer 11 and the lower portion 131 of the bottom electrode 13. It is known that directly depositing the bottom electrode 13 (ex: tungsten) in the hole 112 without any barrier layer may cause cracks or peeling of the bottom electrode 13 in the subsequent process. The situation arises. According to the embodiment, the spacer 15 shields the conductive barrier 12, and the raised bottom electrode 13 separates the resistance conversion layer 16 from the conductive barrier 12 by a distance, thereby effectively preventing the conductive barrier 12 from forming the resistance conversion layer 16 Produces oxidation. In one embodiment, the conductive barrier 12 includes a first barrier layer 121 having a first barrier thickness t1 (eg, 25Å-75Å), and a second barrier layer 122 formed on the first barrier layer 121 and having a second barrier. A thickness t2 (eg, 100 Å to 200 Å), wherein the second barrier thickness t2 is different (eg, less than) the first barrier thickness t1. As shown in FIG. 1, the second barrier layer 122 is disposed between the upper portion 132 of the bottom electrode 13 and the insulating layer 11, and the second barrier layer 122 is located below the upper surface 11a of the insulating layer 11.

2A to 2H-1 (/2H-2) A method of manufacturing a resistance-switching memory element according to an embodiment of the present disclosure. In this embodiment, tungsten (Tungsten, W) is used as the material of the bottom electrode 13 as an example to clearly illustrate the disclosure. However, the bottom electrode of the present disclosure is not limited to the material tungsten.

First, an insulating layer 11 having a hole is provided, and the hole is filled with an etched conductive plug 130 (e.g., a tungsten plug, W-plug) as shown in Fig. 2A. Furthermore, a first barrier layer 121 (eg, a titanium nitride (TiN) layer) is formed between the etched conductive plug 130 and the insulating layer 11. In an embodiment, the thickness (t1) of the first barrier layer 121 is, for example, in the range of 100 Å to 200 Å.

Thereafter, a second barrier layer 122 (eg, a titanium nitride (TiN) layer) is deposited, and a conductive material layer 130U, such as a W material layer, is formed on the insulating layer 11, as shown in FIG. 2B. In an embodiment, the thickness (t2) of the second barrier layer 1221 is, for example, in the range of 10 Å to 100 Å or between 25 Å and 75 Å. The thickness (t2) thereof is smaller than the thickness (t1) of the first barrier layer 121. Next, a planarization step such as chemical mechanical polishing (CMP) is performed on the conductive material layer 130U until the portion of the second barrier layer 122 located above the insulating layer 11 is completely removed (ex: the polishing stops on the upper surface of the insulating layer 11 ), as shown in Figure 2C. In an embodiment, a two-degree deposition barrier layer and a patterned conductive material layer 130U' (such as patterning, for example, polishing the conductive material layer 130U) are formed over the conductive material layer 130U (eg, a tungsten material layer) to obtain a Seamless seam tungsten plug (seam-free W-plug) (Fig. 2C).

Next, a convex bottom electrode 13 is formed, and as shown in FIG. 2D, the insulating layer and the conductive barrier are partially removed to expose the upper portion 132 of the bottom electrode 13. In one embodiment, the insulating layer 11 and the second barrier layer 122 of the conductive barrier 12 are partially removed, for example, by an oxide buffing (and polishing process), and the bottom electrode 13 is formed into a A smooth top surface 132a. After the oxidizing polishing process (for example, CMP or etch back step), the insulating layer 11 (for example, ILD) is chemically polished by the cerium oxide polishing slurry to physically polish the bottom electrode 13 (for example, ILD). Chemical polishing, so that the bottom electrode 13 can be made to produce this smooth upper surface 132a. Furthermore, after the oxidative polishing process (for example, CMP or etch back step), the edges of the bottom electrode 13 can also be formed into rounded corners at edges. In the latter stage of operation of the resistance-switching memory element, the rounded corner of the bottom electrode can improve the uniformity (consistency) of the formation of the electric field and achieve a better electrical performance of the resistance-switching memory element. The material of the bottom electrode 13 includes, for example, but not limited to, tungsten (W), (Cu), (Fe), (Ti), (Ni), (Hf), (TiN), (TaN). And other applicable materials.

Furthermore, the degree of protrusion of the bottom electrode 13 (e.g., the thickness of the upper portion 132 T _BY ) may vary depending on the second barrier thickness t2 of the second barrier layer 122. In some experimental examples, if a tungsten material layer and a titanium nitride (TiN) layer are formed as the bottom electrode and the second barrier layer, respectively, the experimental results show that when the oxidation polishing process conditions are fixed (for example, the oxidation polishing time is the same) The degree of protrusion of the tungsten material layer is related to the thickness of the titanium nitride layer. In one embodiment, the thickness T _BY of the upper portion 132 of the bottom electrode 13 is in the range of 50 Å to 1000 Å or in the range of 200 Å to 1000 Å. For example, when the second barrier thickness t2 of the second barrier layer 122 is 75 Å, 45 Å, and 25 Å, the thickness T _BY is 200 Å, 400 Å, and 600 Å, respectively. The thicker the second barrier thickness t2, the less the second barrier thickness t2 protrudes (under the same oxidative polishing process conditions). Of course, the values listed above are only a few examples and are not intended to limit the disclosure. It will be appreciated by those skilled in the relevant art that the thickness of the second barrier rib, the thickness of the upper portion 132 of the bottom electrode 13 (T _BY ), the thickness of the resistance conversion layer 16 and the thickness of the spacer 15 can be varied according to the needs of the application. And make appropriate changes and adjustments.

Thereafter, fabrication of the spacer 15 and the resistance conversion layer 16 is performed. According to the method of the embodiment, the spacer 15 and the resistance conversion layer 16 may be formed in different steps or formed in the same step. 2E to 2G are diagrams showing a manner in which the spacer 15 and the resistance conversion layer 16 can be simultaneously formed.

As shown in FIG. 2E, a dielectric layer 150 such as an oxide layer is deposited on the insulating layer 11 and the bottom electrode 13. The oxide layer described herein is only the dielectric layer 150 As an example of one material, the dielectric layer 150 (ex: 20 Å - 50 Å) applicable materials include, for example, oxides, nitrides, and other suitable dielectric materials, and are not limited to oxides.

Thereafter, an oxygen plasma etching process is performed anisotropically as shown in FIG. 2F. During the oxygen plasma etching process, the oxide layer (ie dielectric layer 150) is thinned and a spacer 15 is formed around the sidewall 132b of the bottom electrode 13 (the protrusion, such as the upper portion 132). For example, during an oxy-plasma etching process, a chemical vapor deposited oxide (ie, as dielectric layer 150 of FIG. 2E, a material such as cerium oxide) is re-sputtered such that dielectric layer 150 is rendered. The thickness of the central portion (for example, SiO ₂ ) is reduced. After the oxygen plasma etching is completed, the spacer 15 and the resistance conversion layer 16 can be simultaneously formed as shown in FIG. 2G. Next, a top electrode 18 is formed on the resistance conversion layer 16 and covers the resistance conversion layer 16, as shown in the second H-1. After deposition and definition of the top electrode, a subsequent complementary metal oxide semiconductor (CMOS) back end process can be performed. Further, the oxide film 152 can be selectively left on the upper surface 11a of the insulating layer 11. However, the present disclosure is not limited thereto, and in some embodiments, no oxide film remains on the upper surface 11a of the insulating layer 11 after the oxygen plasma etching step.

Furthermore, the resistance conversion layer 16 as shown in FIG. 2G may be a single layer structure or a two-layer structure depending on the process conditions of the oxygen plasma etching step. For example, if the energy/power of the plasma condition of the oxygen plasma etching step is high enough to allow oxygen to penetrate to the upper portion 132 of the bottom electrode 13, causing the material of the bottom electrode 13 to be oxidized, a metal oxide layer 161 may be formed (eg, tungsten is formed). Oxidation to form a layer of tungsten monoxide). Meanwhile, in the oxygen plasma etching step, the spacer 15 may be formed around the sidewall 132b of the bottom electrode 13 by the thinning of the oxide layer (ie dielectric layer 150), and the dielectric layer 162 may be formed (ex: having and spacers) 15 the same material, such as ruthenium dioxide, is applied to the metal oxide layer 161 as shown in the 2H-1 diagram. Accordingly, a self-aligned bilayer structure including a dielectric layer 162 (e.g., hafnium oxide) and a metal oxide layer 161 (e.g., tungsten oxide) can be formed. In one embodiment, a self-aligned two-layer structure comprising a layer of tungsten monoxide (WO ₃ ; metal oxide layer 161 ) having a thickness of 5 Å to 30 Å and a layer of SiO ₂ (ie, a dielectric layer) can be formed. 162) has a thickness of 10 Å to 40 Å. In this example, the metal oxide layer 161 and the dielectric layer 162 together serve as a resistance conversion layer 16 of the resistance conversion memory element of the embodiment.

In another application, the energy/power of the plasma conditions of the oxygen plasma etching step may also be low enough to allow oxygen to penetrate the bottom electrode 13 and cause the bottom electrode 13 material to be oxidized, thus, etching in the oxygen plasma After the step, only a single layer such as an oxide layer (ex: having the same material as the spacer 15 such as hafnium oxide) is formed on the bottom electrode 13 as a resistance conversion layer 16, as shown in Fig. 2H-2.

Further, the oxygen plasma etching conditions are, for example, but not limited to, 60B-100B bias (in a direction perpendicular to the upper surface 11a of the insulating layer 11), 30 mt-60 mt pressure, 300 W-600 W power, and 30 s-100 s. Etching time. Furthermore, the material of the resistance conversion layer 16 or the spacer 15 includes, but is not limited to, cerium oxide (SiO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiOx), titanium oxynitride (TiON), tungsten oxide. (WOx), yttrium oxide (Ta ₂ O ₅ ), alumina (Al ₂ O ₃ ) and other applicable materials. The material of the self-aligned multilayer RRAM film (ie dielectric layer 162 / metal oxide layer 161; resistance conversion layer 16) includes, but is not limited to, cerium oxide / tungsten oxide (SiO ₂ / WOx), cerium oxide / oxidation铪 (SiO ₂ /HfO ₂ ), yttrium oxide / tungsten oxide (HfO ₂ /WOx), titanium oxide / tungsten oxide (TiOx / WOx), titanium oxynitride / tungsten oxide (TiON / WOx), alumina / tungsten oxide ( Al ₂ O ₃ /WOx) and other applicable materials. The above materials are for illustrative purposes only and are not intended to limit the disclosure.

Although FIGS. 2E to 2G are diagrams showing one manner in which the spacer 15 and the resistance conversion layer 16 can be simultaneously formed, the spacer 15 and the resistance conversion layer 16 can also be formed in different steps. 3A and 3B illustrate two possible configurations of the resistance-switching memory element of the application embodiment.

FIG. 3A is a schematic view showing a resistance conversion memory element of another embodiment. FIG. 3B is a schematic view showing a resistance-switching memory device according to still another embodiment. Please also refer to Figure 1. In addition, the same and/or similar elements in the 3A/3B and FIG. 1 are denoted by the same and/or similar reference numerals, and the configuration, the manufacturing method and the function of each layer of the same elements/layers are not described herein again.

In FIGS. 3A and 3B, the material of the spacer 15 may be a nitride or other material (for example, depositing a nitride layer as the dielectric layer 150 as shown in FIG. 2E, and then etching to form nitrogen. The spacers 15). Thereafter, the resistance conversion layer 16 is formed over the bottom electrode 13, as shown in FIG. 3A. If an oxidation conversion process is used to form the resistance conversion layer, a portion of the bottom electrode 13 is oxidized to form the resistance conversion layer 16, as shown in FIG. 3B.

FIG. 4 is a schematic view showing a resistance conversion memory element according to still another embodiment of the present invention. Please also refer to Figure 1. The structure of Fig. 4 and Fig. 1 is the same except that an oxygen ion reservoir layer is added. The same and/or similar elements in the fourth and the first drawings are denoted by the same and/or similar reference numerals, and the configuration, the manufacturing method and the functions of the layers of the same elements/layers are not described herein again. As shown in FIG. 4, an oxygen storage layer 19 can be selectively formed between the top electrode 18 and the resistance conversion layer 16 (eg, over a self-aligned SiO ₂ /WO ₃ resistance conversion layer). Providing oxygen enhances the resistance conversion function of the component. Further, the oxygen ion storage layer 19 covers the spacer 15 and the resistance conversion layer 16. In one embodiment, the thickness of the oxygen ion storage layer 19 is in the range of 10 Å to 100 Å. The material of the oxygen ion storage layer 19 is, for example, but not limited to, titanium oxide (TiOx), titanium oxynitride (TiON), hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), and tantalum oxide (Ta ₂ O). ₅ ) and other applicable materials.

In the above-described resistance conversion memory element of the embodiment, when the resistance conversion layer 16 is formed, the spacer 15 shields the conductive barrier 12, so the conductive barrier 12 (ex:TiN) does not form during the formation of the resistance conversion layer 16. Produces oxidation. Therefore, according to the structure and method proposed in the embodiment, a resistance-switching memory element which does not form titanium oxide (TiON-free) can be obtained. Further, according to the structure and method proposed in the embodiment, a bottom electrode having a smooth upper surface and a rounded corner can be formed. Furthermore, the method proposed in the embodiment can be applied to form a resistance conversion layer having a self-aligned structure. Therefore, the structure and method proposed by the application embodiments can effectively improve the structural reliability and electrical performance of the resistance-switching memory device.

Other embodiments, such as known components of components, may have different arrangements and arrangements, and may be applied, depending on the actual needs and conditions of the application, and may be appropriately adjusted or changed. Therefore, the structures shown in the specification and drawings are for illustrative purposes only and are not intended to limit the scope of the disclosure. In addition, the relevant artisan It is to be understood that the shapes and positions of the components in the embodiments are not limited to those illustrated in the drawings, and may be made according to the needs and/or manufacturing steps of the actual application without departing from the spirit of the disclosure. Adjust accordingly.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

11‧‧‧Insulation

11a‧‧‧Top surface of insulation

12‧‧‧Electrical barrier

121‧‧‧First barrier layer

122‧‧‧Second barrier layer

T1‧‧‧First barrier thickness

T2‧‧‧second barrier thickness

13‧‧‧ bottom electrode

131‧‧‧Under the bottom electrode

132‧‧‧Top part of the bottom electrode

132a‧‧‧ Upper surface of the upper part of the bottom electrode

132b‧‧‧ sidewall of the bottom electrode

15‧‧‧ clearance

152‧‧‧Oxide film

Ts‧‧‧ thickness of the spacer

16‧‧‧resistive conversion layer

16c‧‧‧ bottom surface of the resistance conversion layer

18‧‧‧ top electrode

Claims (9)

A resistance-switching memory device, comprising: an insulating layer having an upper surface; a bottom electrode embedded in the insulating layer, an upper portion of the bottom electrode protruding from the upper surface of the insulating layer and having an edge at the upper portion a smooth corner, a lower portion of the bottom electrode filling a hole of the insulating layer; a barrier layer located in the hole to separate the insulating layer and the bottom electrode, the barrier layer comprising: having a thickness of a first barrier a first barrier layer, and a second barrier layer formed on the first barrier layer and having a second barrier thickness, wherein the second barrier thickness is less than the first barrier thickness; a resistance conversion layer is disposed on the And a top electrode formed on the resistance conversion layer and covering the resistance conversion layer. The resistance-switching memory device of claim 1, wherein the barrier layer is disposed between the upper portion of the bottom electrode and the insulating layer, and the barrier layer is located below the upper surface of the insulating layer. The resistance-switching memory device of claim 1, further comprising a spacer formed on the insulating layer and located at a sidewall of the upper portion of the bottom electrode. The resistance conversion memory element according to claim 1, wherein the resistance conversion layer is a two-layer structure. The resistance conversion memory component according to claim 1, wherein The barrier layer is a conductive barrier located in the hole to separate the upper portion and the lower portion of the insulating layer and the bottom electrode. The resistance-switching memory device of claim 1, further comprising an oxygen ion storage layer between the top electrode and the resistance conversion layer. A method of manufacturing a resistance-switching memory device, comprising: providing an insulating layer having a hole; forming a hole in which a bottom electrode fills the insulating layer, wherein an upper portion of the bottom electrode protrudes above the insulating layer, and The upper edge has a rounded corner; a resistance conversion layer is disposed on the bottom electrode; and a top electrode is formed on the resistance conversion layer and covers the resistance conversion layer. The manufacturing method of claim 7, wherein the insulating layer is removed in an oxidative polishing process to form the bottom electrode having a smooth upper surface. The manufacturing method of claim 7, further comprising: forming an oxide layer on the insulating layer and the bottom electrode; and performing an oxygen plasma etching process on the oxide layer in an isotropic manner, wherein After the oxygen plasma etching process, a spacer is formed at a sidewall surrounding the upper portion of the bottom electrode, and at the same time, the resistance conversion layer having a self-aligned structure is produced.