TWI607591B - ResistANce Switching Memory Device And Method Of Manufacturing The Same - Google Patents

ResistANce Switching Memory Device And Method Of Manufacturing The Same Download PDF

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TWI607591B
TWI607591B TW105139112A TW105139112A TWI607591B TW I607591 B TWI607591 B TW I607591B TW 105139112 A TW105139112 A TW 105139112A TW 105139112 A TW105139112 A TW 105139112A TW I607591 B TWI607591 B TW I607591B
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layer
electrode
resistance
barrier
insulating layer
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TW105139112A
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TW201820668A (en
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曾柏皓
李峰旻
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旺宏電子股份有限公司
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電阻轉換記憶體元件及其製造方法 Resistance conversion memory element and method of manufacturing same
本發明是有關於一種記憶體元件及其製造方法,且特別是有關於一種電阻轉換記憶體元件(resistance switching memory device)及其製造方法。 The present invention relates to a memory element and a method of fabricating the same, and more particularly to a resistance switching memory device and a method of fabricating the same.
電阻式隨機存取記憶體(Resistive random-access memory)(RRAM或ReRAM)元件是一種非揮發式記憶體元件。電阻式記憶體元件由於它簡單的金屬層-絕緣層-金屬層(MIM,Metal-Insulator-Metal)結構和規模可擴展性而深受相關業者的注目。目前根據使用的介電材料不同和記憶體層材料的不同,從鈣鈦礦(perovskites)到過渡金屬氧化物(transition metal oxides)到硫族(元素)化物(chalcogenides),已有許多不同形態的ReRAM元件被提出。 A Resistive random-access memory (RRAM or ReRAM) component is a non-volatile memory component. Resistive memory components are highly regarded by the industry due to their simple metal-insulator-metal (MIM, Metal-Insulator-Metal) structure and scale scalability. At present, there are many different forms of ReRAM from perovskites to transition metal oxides to chalcogenides depending on the dielectric materials used and the memory layer materials. The component is presented.
電阻轉換記憶體元件是過渡金屬氧化物記憶體元件的示例之一,其為一群雙穩態兩端記憶體元件(two-terminal bistable memory devices)藉由不同電阻態可儲存資料。例如一典 型的ReRAM元件包括了鎢底電極、一氧化矽鎢(WSixOy)記憶層和一氮化鈦(TiN)頂電極。在傳統的製程中,氮氧化鈦(TiONx)可能會形成於電阻轉換層旁(i.e.記憶層)而對記憶體元件的轉換特性造成不可忽視的影響。因此,相關業者無不希望可以發展和實現一個具有優異結構穩定性和電子特性(例如資料儲存具有良好穩定度)的電阻轉換記憶體元件。 The resistance-switching memory element is one example of a transition metal oxide memory element, which is a group of bistable bistable memory devices that can store data by different resistance states. For example, a code The type of ReRAM device includes a tungsten bottom electrode, a tungsten germanium oxide (WSixOy) memory layer, and a titanium nitride (TiN) top electrode. In the conventional process, titanium oxynitride (TiONx) may be formed beside the resistance conversion layer (i.e. memory layer) and have a non-negligible effect on the conversion characteristics of the memory element. Therefore, the related industry has no desire to develop and realize a resistance-switching memory element having excellent structural stability and electronic characteristics such as good stability of data storage.
本發明係有關於一種電阻轉換記憶體元件及其製造方法,其提出一種突起的底電極以及沒有氮氧化鈦(TiON)形成與平滑上表面的底電極,可有效地增進電阻轉換記憶體元件的穩定度和的電性表現。。 The present invention relates to a resistance-switching memory element and a method of fabricating the same, which provide a raised bottom electrode and a bottom electrode without titanium oxynitride (TiON) forming and smoothing the upper surface, which can effectively enhance the resistance-switching memory element. Stability and electrical performance. .
根據一實施例,係提出一種電阻轉換記憶體元件,包括一絕緣層具有一上表面;一底電極,埋置於絕緣層中,底電極之一上部突出於絕緣層之上表面,且上部之邊緣具有圓滑轉角;一電阻轉換層,設置於底電極上;和一頂電極,形成於電阻轉換層上並覆蓋電阻轉換層。 According to an embodiment, a resistance conversion memory element is provided, comprising: an insulating layer having an upper surface; a bottom electrode buried in the insulating layer, one of the bottom electrodes protruding above the upper surface of the insulating layer, and the upper portion The edge has a rounded corner; a resistance conversion layer is disposed on the bottom electrode; and a top electrode is formed on the resistance conversion layer and covers the resistance conversion layer.
根據一實施例,再提出一種電阻轉換記憶體元件,包括一絕緣層具有一上表面;一突起之底電極,埋置於絕緣層中且突出於絕緣層之上表面上;間隙壁(spacers),圍繞突起之底電極之一上部的側壁;一電阻轉換層設置於突起之底電極上;和一頂電極,形成於電阻轉換層上,且頂電極覆蓋電阻轉換層和間隙壁。 According to an embodiment, there is further provided a resistance-switching memory device, comprising: an insulating layer having an upper surface; a raised bottom electrode buried in the insulating layer and protruding over the upper surface of the insulating layer; spacers a side wall surrounding an upper portion of the bottom electrode of the protrusion; a resistance conversion layer disposed on the bottom electrode of the protrusion; and a top electrode formed on the resistance conversion layer, and the top electrode covering the resistance conversion layer and the spacer.
根據一實施例,係提出一種電阻轉換記憶體元件,包括:提供具有一孔洞之一絕緣層;形成一底電極填滿絕緣層之孔洞,其中底電極之一上部突出於絕緣層之上,且上部之邊緣具有圓滑轉角;設置一電阻轉換層於底電極上;和形成一頂電極於電阻轉換層上並覆蓋電阻轉換層。 According to an embodiment, there is provided a resistance-switching memory device, comprising: providing an insulating layer having a hole; forming a hole in which a bottom electrode fills the insulating layer, wherein an upper portion of the bottom electrode protrudes above the insulating layer, and The upper edge has a rounded corner; a resistive conversion layer is disposed on the bottom electrode; and a top electrode is formed on the resistance conversion layer and covers the resistance conversion layer.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式,作詳細說明如下。然而,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.
11‧‧‧絕緣層 11‧‧‧Insulation
112‧‧‧孔洞 112‧‧‧ hole
11a‧‧‧絕緣層之上表面 11a‧‧‧Top surface of insulation
12‧‧‧導電障壁 12‧‧‧Electrical barrier
121‧‧‧第一障壁層 121‧‧‧First barrier layer
122‧‧‧第二障壁層 122‧‧‧Second barrier layer
t1‧‧‧第一障壁厚度 T1‧‧‧First barrier thickness
t2‧‧‧第二障壁厚度 T2‧‧‧second barrier thickness
13‧‧‧底電極 13‧‧‧ bottom electrode
130‧‧‧導電插塞 130‧‧‧conductive plug
130U‧‧‧導電材料層 130U‧‧‧layer of conductive material
130U’‧‧‧圖案化導電材料層 130U’‧‧‧ patterned conductive material layer
131‧‧‧底電極之下部 131‧‧‧Under the bottom electrode
132‧‧‧底電極之上部 132‧‧‧Top part of the bottom electrode
132a‧‧‧底電極上部之上表面 132a‧‧‧ Upper surface of the upper part of the bottom electrode
132b‧‧‧底電極之側壁 132b‧‧‧ sidewall of the bottom electrode
TBY‧‧‧上部之厚度 T BY ‧‧‧ thickness of the upper part
15‧‧‧間隙壁 15‧‧‧ clearance
150、162‧‧‧介電層 150, 162‧‧‧ dielectric layer
152‧‧‧氧化物薄膜 152‧‧‧Oxide film
ts‧‧‧間隙壁的厚度 Ts‧‧‧ thickness of the spacer
16‧‧‧電阻轉換層 16‧‧‧resistive conversion layer
16c‧‧‧電阻轉換層之底表面 16c‧‧‧ bottom surface of the resistance conversion layer
161‧‧‧金屬氧化層 161‧‧‧metal oxide layer
18‧‧‧頂電極 18‧‧‧ top electrode
19‧‧‧氧離子貯藏層 19‧‧‧Oxygen storage layer
第1圖係簡繪本揭露一實施例之一電阻轉換記憶體元件之示意圖。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a resistive switching memory device of an embodiment.
第2A圖-第2H-1圖(/第2H-2圖)根據本揭露一實施例之電阻轉換記憶體元件的製造方法。 2A to 2H-1 (/2H-2) A method of manufacturing a resistance-switching memory element according to an embodiment of the present disclosure.
第3A圖係簡繪本揭露另一實施例之一電阻轉換記憶體元件之示意圖。 FIG. 3A is a schematic view showing a resistance conversion memory element of another embodiment.
第3B圖係簡繪本揭露再一實施例之一電阻轉換記憶體元件之示意圖。 FIG. 3B is a schematic view showing a resistance-switching memory device according to still another embodiment.
第4圖係簡繪本揭露又一實施例之一電阻轉換記憶體元件之示意圖。 FIG. 4 is a schematic view showing a resistance conversion memory element according to still another embodiment of the present invention.
根據本揭露之實施例,係提出一種電阻轉換記憶體元件(resistance switching memory device)及其製造方法。實施例之電阻轉換記憶體元件係具有一突起的底電極且沒有TiON形成,且底電極具有一平滑上表面(a smooth top surface)和可以增進電場的邊角(electrical field enhanced corner),因而增進所製得之電阻轉換記憶體元件的穩定度和的電性表現。再者,實施例所提出之製造方法不但考有效改善相關元件的性質(例如使製得的底電極具有平滑上表面),更可應用實施例以形成具有一自對準結構之一電阻轉換層。 According to an embodiment of the present disclosure, a resistance switching memory device and a method of fabricating the same are provided. The resistance-switching memory device of the embodiment has a raised bottom electrode and no TiON is formed, and the bottom electrode has a smooth top surface and an electrical field enhanced corner, thereby enhancing The resulting resistance converts the stability and electrical performance of the memory component. Furthermore, the manufacturing method proposed in the embodiment not only improves the properties of the related components (for example, the prepared bottom electrode has a smooth upper surface), but also applies an embodiment to form a resistance conversion layer having a self-aligned structure. .
以下係參照所附圖式敘述本揭露提出之其中多個實施態樣,以描述相關構型與製造方法。相關的結構細節例如相關層別和空間配置等內容如下面實施例內容所述。然而,但本揭露並非僅限於所述態樣,本揭露並非顯示出所有可能的實施例。實施例中相同或類似的標號係用以標示相同或類似之部分。再者,未於本揭露提出的其他實施態樣也可能可以應用。相關領域者可在不脫離本揭露之精神和範圍內對實施例之結構加以變化與修飾,以符合實際應用所需。而圖式係已簡化以利清楚說明實施例之內容,圖式上的尺寸比例並非按照實際產品等比例繪製。因此,說明書和圖示內容僅作敘述實施例之用,而非作為限縮本揭露保護範圍之用。 Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings to describe the related configurations and manufacturing methods. Relevant structural details such as related layers and spatial configurations are as described in the following examples. However, the disclosure is not limited to the description, and the disclosure does not show all possible embodiments. The same or similar reference numerals in the embodiments are used to designate the same or similar parts. Furthermore, other implementations not presented in this disclosure may also be applicable. Variations and modifications of the structure of the embodiments can be made in the relevant embodiments without departing from the spirit and scope of the disclosure. The drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to scale in terms of actual products. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.
再者,說明書與請求項中所使用的序數例如”第 一”、”第二”、”第三”等之用詞,以修飾請求項之元件,其本身並不意含及代表該請求元件有任何之前的序數,也不代表某一請求元件與另一請求元件的順序、或是製造方法上的順序,該些序數的使用僅用來使具有某命名的一請求元件得以和另一具有相同命名的請求元件能作出清楚區分。 Furthermore, the ordinal used in the specification and the request item, for example, The words "a", "second", "third", etc., are used to modify the elements of the claim, and are not intended to represent any prior ordinal of the claim element. The order of the requesting elements, or the order of the manufacturing methods, is used only to enable a requesting element having a certain name to be clearly distinguished from another requesting element having the same name.
第1圖係簡繪本揭露一實施例之一電阻轉換記憶體元件之示意圖。實施例之一電阻轉換記憶體元件包括一絕緣層11(例如一層間介電層(inter-layered dielectric,ILD))具有一孔洞112、一底電極(bottom electrode)13、形成於底電極13上之一電阻轉換層(resistance switching layer)16、和形成於電阻轉換層16上並覆蓋電阻轉換層16之一頂電極(top electrode)18。根據實施例,底電極13埋置於絕緣層11內且突出於絕緣層11之上(i.e.底電極13具有一上凸廓型(concave profile))。如第1圖所示,底電極13可被視為埋置於絕緣層11內的下部(lower portion)131與突出於絕緣層11之上表面11a的上部(upper portion)132之組合(i.e.第1圖中所繪示之虛線表示出突出於絕緣層11之上表面11a的上部132)。底電極13之上部132的上表面132a係具有一實質上平滑之表面且高於絕緣層11之上表面11a。底電極13之上部132a之邊緣具有圓滑轉角(round corners at edges)。再者,根據實施例之元件結構,相較於絕緣層11,電阻轉換層16是位於更高的水平位置(horizontal level),因此電阻轉換層16之底表面16c係高於絕緣層11之上表面11a。再者,第1圖僅繪製單層結構的 電阻轉換層16以簡示本揭露之其中之一個可實施態樣,但本揭露並不限制於此種態樣。根據實施例,電阻轉換層16可以是一單層結構或是一雙層結構(bilayer structure),視應用時之需求而定,而且於實際應用時可以通過稍加變化的製法而達到所欲形成的單層或雙層結構。於一實施例中,電阻轉換層16可以是一自對準雙層結構(self-aligned bilayer structure)(如以下文中第2A圖-第2H-1圖之實施例所述)。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a resistive switching memory device of an embodiment. In one embodiment, the resistance-switching memory device includes an insulating layer 11 (eg, an inter-layered dielectric (ILD)) having a hole 112, a bottom electrode 13 formed on the bottom electrode 13. A resistance switching layer 16, and a top electrode 18 formed on the resistance conversion layer 16 and covering the resistance conversion layer 16. According to an embodiment, the bottom electrode 13 is buried in the insulating layer 11 and protrudes above the insulating layer 11 (i.e. the bottom electrode 13 has a concave profile). As shown in Fig. 1, the bottom electrode 13 can be regarded as a combination of a lower portion 131 buried in the insulating layer 11 and an upper portion 132 protruding from the upper surface 11a of the insulating layer 11 (ie The dotted line drawn in Fig. 1 indicates the upper portion 132) which protrudes from the upper surface 11a of the insulating layer 11. The upper surface 132a of the upper portion 132 of the bottom electrode 13 has a substantially smooth surface and is higher than the upper surface 11a of the insulating layer 11. The edges of the upper portion 132a of the bottom electrode 13 have round corners at edges. Moreover, according to the element structure of the embodiment, the resistance conversion layer 16 is located at a higher horizontal level than the insulating layer 11, and thus the bottom surface 16c of the resistance conversion layer 16 is higher than the insulating layer 11. Surface 11a. Furthermore, Figure 1 only draws a single layer structure. The resistance conversion layer 16 is a simplified representation of one of the embodiments of the present disclosure, but the disclosure is not limited to such an aspect. According to an embodiment, the resistance conversion layer 16 may be a single layer structure or a bilayer structure, depending on the requirements of the application, and may be formed by a slightly changed method in practical applications. Single or double layer structure. In one embodiment, the resistance conversion layer 16 can be a self-aligned bilayer structure (as described in the embodiment of FIG. 2A - FIG. 2H-1 below).
再者,電阻轉換記憶體元件更包括間隙壁(spacers)15形成於絕緣層11上且鄰近底電極13;例如,間隙壁15是形成(例如圍繞)於底電極13之上部132的側壁132a處,其中頂電極18覆蓋電阻轉換層16和所述間隙壁15。根據實施例,底電極13之側壁132b係完全被厚的間隙壁15所覆蓋,致使頂電極18與底電極13的側壁132b之間可藉由間隙壁15的存在而達到電性絕緣。由於間隙壁15覆蓋底電極13之側壁132b,因此實施例元件的電阻轉換可在電阻轉換層16的中間部分完成。一實施例中,間隙壁15的厚度ts例如是,但不限制是,在20Å-50Å範圍之間。一實施例中,電阻轉換層16的厚度例如是,但不限制是,在15Å-70Å範圍之間。 Furthermore, the resistance-switching memory element further includes spacers 15 formed on the insulating layer 11 adjacent to the bottom electrode 13; for example, the spacer 15 is formed (eg, surrounding) at the sidewall 132a of the upper portion 132 of the bottom electrode 13 Wherein the top electrode 18 covers the resistance conversion layer 16 and the spacer 15 . According to the embodiment, the side wall 132b of the bottom electrode 13 is completely covered by the thick spacer 15, so that the gap between the top electrode 18 and the side wall 132b of the bottom electrode 13 can be electrically insulated by the presence of the spacer 15. Since the spacer 15 covers the sidewall 132b of the bottom electrode 13, the resistance conversion of the embodiment elements can be completed in the intermediate portion of the resistance conversion layer 16. In one embodiment, the thickness ts of the spacer 15 is, for example, but not limited to, between 20 Å and 50 Å. In one embodiment, the thickness of the resistance conversion layer 16 is, for example, but not limited to, between 15 Å and 70 Å.
再者,實施例之電阻轉換記憶體元件更包括一導電障壁(conductive barrier)12以隔開絕緣層11和底電極13之下部131。已知若沒有任何障壁層的存在而直接沈積底電極13(ex:鎢)於孔洞112內可能會造成後續製程中的底電極13有裂痕或是剝落 的情況產生。根據實施例,間隙壁15遮蔽導電障壁12,且突起的底電極13會使電阻轉換層16與導電障壁12相隔開來一距離,因而可有效避免導電障壁12在形成電阻轉換層16的過程中產生氧化。一實施例中,導電障壁12包括一第一障壁層121具有一第一障壁厚度t1(例如25Å-75Å),和一第二障壁層122形成於第一障壁層121上且具有一第二障壁厚度t2(例如100Å-200Å),其中第二障壁厚度t2不同於(例如小於)第一障壁厚度t1。如第1圖所示,第二障壁層122設置於底電極13之上部132與絕緣層11之間,且第二障壁層122位於絕緣層11之上表面11a的下方。 Furthermore, the resistance-switching memory device of the embodiment further includes a conductive barrier 12 to partition the insulating layer 11 and the lower portion 131 of the bottom electrode 13. It is known that directly depositing the bottom electrode 13 (ex: tungsten) in the hole 112 without any barrier layer may cause cracks or peeling of the bottom electrode 13 in the subsequent process. The situation arises. According to the embodiment, the spacer 15 shields the conductive barrier 12, and the raised bottom electrode 13 separates the resistance conversion layer 16 from the conductive barrier 12 by a distance, thereby effectively preventing the conductive barrier 12 from forming the resistance conversion layer 16 Produces oxidation. In one embodiment, the conductive barrier 12 includes a first barrier layer 121 having a first barrier thickness t1 (eg, 25Å-75Å), and a second barrier layer 122 formed on the first barrier layer 121 and having a second barrier. A thickness t2 (eg, 100 Å to 200 Å), wherein the second barrier thickness t2 is different (eg, less than) the first barrier thickness t1. As shown in FIG. 1, the second barrier layer 122 is disposed between the upper portion 132 of the bottom electrode 13 and the insulating layer 11, and the second barrier layer 122 is located below the upper surface 11a of the insulating layer 11.
第2A圖-第2H-1圖(/第2H-2圖)根據本揭露一實施例之電阻轉換記憶體元件的製造方法。在此實施例中係以鎢(Tungsten,W)為底電極13之材料為例以利清楚說明本揭露。但本揭露之底電極並不僅限於材料鎢。 2A to 2H-1 (/2H-2) A method of manufacturing a resistance-switching memory element according to an embodiment of the present disclosure. In this embodiment, tungsten (Tungsten, W) is used as the material of the bottom electrode 13 as an example to clearly illustrate the disclosure. However, the bottom electrode of the present disclosure is not limited to the material tungsten.
首先,提供具有一孔洞之絕緣層11,且孔洞中填充有一回蝕之導電插塞130(例如鎢插塞,W-plug),如第2A圖所示。再者,第一障壁層121(例如氮化鈦(TiN)層)係形成於回蝕之導電插塞130和絕緣層11之間。於一實施例中,第一障壁層121厚度(t1)例如是在100Å-200Å範圍之間。 First, an insulating layer 11 having a hole is provided, and the hole is filled with an etched conductive plug 130 (e.g., a tungsten plug, W-plug) as shown in Fig. 2A. Furthermore, a first barrier layer 121 (eg, a titanium nitride (TiN) layer) is formed between the etched conductive plug 130 and the insulating layer 11. In an embodiment, the thickness (t1) of the first barrier layer 121 is, for example, in the range of 100 Å to 200 Å.
之後,沈積第二障壁層122(例如氮化鈦(TiN)層),並且形成一導電材料層130U例如鎢材料層(W material layer)於絕緣層11上,如第2B圖所示。於一實施例中,第二障壁層1221厚度(t2)例如是在10Å-100Å範圍之間,或是25Å-75Å範圍之間, 其厚度(t2)小於第一障壁層121的厚度(t1)。接著,對導電材料層130U進行平坦化步驟例如化學機械研磨(CMP),直到位於絕緣層11上方的第二障壁層122的部分被完全移除為止(ex:研磨停在絕緣層11上表面為止),如第2C圖所示。實施例中,兩度沈積障壁層以及在導電材料層130U(例如鎢材料層)上方形成一圖案化導電材料層130U’(對導電材料層130U進行圖案化例如研磨後而得),可得到一無縫隙的鎢插塞(seam-free W-plug)(第2C圖)。 Thereafter, a second barrier layer 122 (eg, a titanium nitride (TiN) layer) is deposited, and a conductive material layer 130U, such as a W material layer, is formed on the insulating layer 11, as shown in FIG. 2B. In an embodiment, the thickness (t2) of the second barrier layer 1221 is, for example, in the range of 10 Å to 100 Å or between 25 Å and 75 Å. The thickness (t2) thereof is smaller than the thickness (t1) of the first barrier layer 121. Next, a planarization step such as chemical mechanical polishing (CMP) is performed on the conductive material layer 130U until the portion of the second barrier layer 122 located above the insulating layer 11 is completely removed (ex: the polishing stops on the upper surface of the insulating layer 11 ), as shown in Figure 2C. In an embodiment, a two-degree deposition barrier layer and a patterned conductive material layer 130U' (such as patterning, for example, polishing the conductive material layer 130U) are formed over the conductive material layer 130U (eg, a tungsten material layer) to obtain a Seamless seam tungsten plug (seam-free W-plug) (Fig. 2C).
接著,形成突起的底電極(convex bottom electrode)13,如第2D圖所示,部分地移除絕緣層和導電障壁以暴露出底電極13之上部(upper portion)132。一實施例中,例如是以氧化抛光(和研磨)製程(oxide buffing(and polishing)process)將絕緣層11和導電障壁12的第二障壁層122部分地移除,而使底電極13形成一平滑的上表面(smooth top surface)132a。在進行氧化抛光製程(例如CMP或回蝕步驟)後,由於二氧化矽研磨漿料會對底電極13進行物理性研磨(physical polishing)而對絕緣層11(例如ILD)是進行化學性研磨(chemical polishing),因此可使底電極13產生此平滑上表面132a。再者,進行氧化抛光製程(例如CMP或回蝕步驟)後,亦可使底電極13之邊緣形成圓滑的轉角(rounded corners at edges)。在電阻轉換記憶體元件之一後階段操作中,底電極的圓滑轉角可以改善形成電場的均勻性(一致性)而使電阻轉換記憶體元件達到較佳的電性表現。底電極13的材料例如是包括(但不限制於)鎢(W)、(Cu)、(Fe)、(Ti)、(Ni)、(Hf)、(TiN)、(TaN) 和其他可應用之材料。 Next, a convex bottom electrode 13 is formed, and as shown in FIG. 2D, the insulating layer and the conductive barrier are partially removed to expose the upper portion 132 of the bottom electrode 13. In one embodiment, the insulating layer 11 and the second barrier layer 122 of the conductive barrier 12 are partially removed, for example, by an oxide buffing (and polishing process), and the bottom electrode 13 is formed into a A smooth top surface 132a. After the oxidizing polishing process (for example, CMP or etch back step), the insulating layer 11 (for example, ILD) is chemically polished by the cerium oxide polishing slurry to physically polish the bottom electrode 13 (for example, ILD). Chemical polishing, so that the bottom electrode 13 can be made to produce this smooth upper surface 132a. Furthermore, after the oxidative polishing process (for example, CMP or etch back step), the edges of the bottom electrode 13 can also be formed into rounded corners at edges. In the latter stage of operation of the resistance-switching memory element, the rounded corner of the bottom electrode can improve the uniformity (consistency) of the formation of the electric field and achieve a better electrical performance of the resistance-switching memory element. The material of the bottom electrode 13 includes, for example, but not limited to, tungsten (W), (Cu), (Fe), (Ti), (Ni), (Hf), (TiN), (TaN). And other applicable materials.
再者,底電極13的突出程度(例如上部132之厚度TBY的大小)可隨第二障壁層122的第二障壁厚度t2之變化而有所改變。於一些實驗例中,若形成一鎢材料層和一氮化鈦(TiN)層分別做為底電極和第二障壁層,其實驗結果顯示當氧化抛光製程條件都固定時(例如氧化抛光時間相同),鎢材料層的突出程度和氮化鈦層的厚度有關。於一實施例中,底電極13之上部132的厚度TBY係在50Å-1000Å的範圍內、或是在200Å-1000Å的範圍內。例如,當第二障壁層122的第二障壁厚度t2為75Å、45Å和25Å時,厚度TBY分別為200Å、400Å和600Å。第二障壁厚度t2越厚,第二障壁厚度t2的突出程度越少(在相同氧化抛光製程條件之下)。當然,上述列出之數值僅是其中幾組示例,並非限制本揭露之用。相關領域之技藝者可知,實施例中所提出之第二障壁厚度、底電極13之上部132厚度(TBY)、電阻轉換層16厚度和間隙壁15厚度等數值,皆可根據實際應用之需求而做適當變化和調整。 Furthermore, the degree of protrusion of the bottom electrode 13 (e.g., the thickness of the upper portion 132 T BY ) may vary depending on the second barrier thickness t2 of the second barrier layer 122. In some experimental examples, if a tungsten material layer and a titanium nitride (TiN) layer are formed as the bottom electrode and the second barrier layer, respectively, the experimental results show that when the oxidation polishing process conditions are fixed (for example, the oxidation polishing time is the same) The degree of protrusion of the tungsten material layer is related to the thickness of the titanium nitride layer. In one embodiment, the thickness T BY of the upper portion 132 of the bottom electrode 13 is in the range of 50 Å to 1000 Å or in the range of 200 Å to 1000 Å. For example, when the second barrier thickness t2 of the second barrier layer 122 is 75 Å, 45 Å, and 25 Å, the thickness T BY is 200 Å, 400 Å, and 600 Å, respectively. The thicker the second barrier thickness t2, the less the second barrier thickness t2 protrudes (under the same oxidative polishing process conditions). Of course, the values listed above are only a few examples and are not intended to limit the disclosure. It will be appreciated by those skilled in the relevant art that the thickness of the second barrier rib, the thickness of the upper portion 132 of the bottom electrode 13 (T BY ), the thickness of the resistance conversion layer 16 and the thickness of the spacer 15 can be varied according to the needs of the application. And make appropriate changes and adjustments.
之後,進行間隙壁15和電阻轉換層16之製作。根據實施例之方法,間隙壁15和電阻轉換層16可以在不同步驟中形成或是於同一步驟中形成。第2E圖-第2G圖係繪示可以同時形成間隙壁15和電阻轉換層16之一種方式。 Thereafter, fabrication of the spacer 15 and the resistance conversion layer 16 is performed. According to the method of the embodiment, the spacer 15 and the resistance conversion layer 16 may be formed in different steps or formed in the same step. 2E to 2G are diagrams showing a manner in which the spacer 15 and the resistance conversion layer 16 can be simultaneously formed.
如第2E圖所示,一介電層150例如一氧化層係沈積於絕緣層11和底電極13上。此敘述之氧化層僅是介電層150 其中一種材料示例,介電層150(ex:20Å-50Å)可應用之材料例如包括氧化物、氮化物和其他適合的介電材料,並不限制於氧化物。 As shown in FIG. 2E, a dielectric layer 150 such as an oxide layer is deposited on the insulating layer 11 and the bottom electrode 13. The oxide layer described herein is only the dielectric layer 150 As an example of one material, the dielectric layer 150 (ex: 20 Å - 50 Å) applicable materials include, for example, oxides, nitrides, and other suitable dielectric materials, and are not limited to oxides.
之後,非等向性地(anisotropically)進行一氧電漿蝕刻製程(oxygen plasma etching process),如第2F圖所示。在進行氧電漿蝕刻製程期間,氧化層(i.e.介電層150)會被薄化且形成間隙壁15圍繞底電極13(之突出部例如上部132)的側壁132b處。例如,在進行氧電漿蝕刻製程期間,一化學氣相沈積之氧化物(i.e.做為第2E圖之介電層150,材料例如是二氧化矽)會被重新濺鍍因而使介電層150(例如SiO2)的中央部分厚度減薄。在氧電漿蝕刻完成後,可以同時形成間隙壁15和電阻轉換層16,如第2G圖所示。接著,形成頂電極18於電阻轉換層16上並覆蓋電阻轉換層16,如第2H-1圖所示。在沈積與定義頂電極之後,可進行後續之一互補性氧化金屬半導體(CMOS)後端製程。再者,一氧化物薄膜152可選擇性地留在絕緣層11的上表面11a。但本揭露並不限制於此,於一些實施例中,在氧電漿蝕刻步驟後,沒有氧化物薄膜留在絕緣層11的上表面11a。 Thereafter, an oxygen plasma etching process is performed anisotropically as shown in FIG. 2F. During the oxygen plasma etching process, the oxide layer (ie dielectric layer 150) is thinned and a spacer 15 is formed around the sidewall 132b of the bottom electrode 13 (the protrusion, such as the upper portion 132). For example, during an oxy-plasma etching process, a chemical vapor deposited oxide (ie, as dielectric layer 150 of FIG. 2E, a material such as cerium oxide) is re-sputtered such that dielectric layer 150 is rendered. The thickness of the central portion (for example, SiO 2 ) is reduced. After the oxygen plasma etching is completed, the spacer 15 and the resistance conversion layer 16 can be simultaneously formed as shown in FIG. 2G. Next, a top electrode 18 is formed on the resistance conversion layer 16 and covers the resistance conversion layer 16, as shown in the second H-1. After deposition and definition of the top electrode, a subsequent complementary metal oxide semiconductor (CMOS) back end process can be performed. Further, the oxide film 152 can be selectively left on the upper surface 11a of the insulating layer 11. However, the present disclosure is not limited thereto, and in some embodiments, no oxide film remains on the upper surface 11a of the insulating layer 11 after the oxygen plasma etching step.
再者,如第2G圖所示之電阻轉換層16可能是一單層結構或是一雙層結構,視氧電漿蝕刻步驟的製程條件而定。例如,若氧電漿蝕刻步驟的電漿條件之能量/功率夠高而足以使氧穿透至底電極13之上部132致使底電極13材料被氧化而可形成一金屬氧化層161(例如使鎢氧化而形成一氧化鎢層)。同時,於氧電漿蝕刻步驟中亦可因氧化層(i.e.介電層150)的薄化而形成間隙壁 15圍繞底電極13之側壁132b,以及形成介電層162(ex:具有和間隙壁15相同的材料,例如二氧化矽)於金屬氧化層161上,如第2H-1圖所示。據此,可形成包括介電層162(例如二氧化矽)和金屬氧化層161(例如氧化鎢)的一自對準雙層結構(self-aligned bilayer structure)。於一實施例中,可形成一自對準雙層結構包括一氧化鎢(WO3;即金屬氧化層161)層具有厚度5Å-30Å,以及一二氧化矽層(SiO2;即介電層162)具有厚度10Å-40Å。於此示例,金屬氧化層161和介電層162一起做為實施例之電阻轉換記憶體元件的一電阻轉換層16。 Furthermore, the resistance conversion layer 16 as shown in FIG. 2G may be a single layer structure or a two-layer structure depending on the process conditions of the oxygen plasma etching step. For example, if the energy/power of the plasma condition of the oxygen plasma etching step is high enough to allow oxygen to penetrate to the upper portion 132 of the bottom electrode 13, causing the material of the bottom electrode 13 to be oxidized, a metal oxide layer 161 may be formed (eg, tungsten is formed). Oxidation to form a layer of tungsten monoxide). Meanwhile, in the oxygen plasma etching step, the spacer 15 may be formed around the sidewall 132b of the bottom electrode 13 by the thinning of the oxide layer (ie dielectric layer 150), and the dielectric layer 162 may be formed (ex: having and spacers) 15 the same material, such as ruthenium dioxide, is applied to the metal oxide layer 161 as shown in the 2H-1 diagram. Accordingly, a self-aligned bilayer structure including a dielectric layer 162 (e.g., hafnium oxide) and a metal oxide layer 161 (e.g., tungsten oxide) can be formed. In one embodiment, a self-aligned two-layer structure comprising a layer of tungsten monoxide (WO 3 ; metal oxide layer 161 ) having a thickness of 5 Å to 30 Å and a layer of SiO 2 (ie, a dielectric layer) can be formed. 162) has a thickness of 10 Å to 40 Å. In this example, the metal oxide layer 161 and the dielectric layer 162 together serve as a resistance conversion layer 16 of the resistance conversion memory element of the embodiment.
於另外應用例中,氧電漿蝕刻步驟的電漿條件之能量/功率也可能較低而不足以使氧穿透至底電極13而致使底電極13材料被氧化,因此,在氧電漿蝕刻步驟後只形成單一層例如一氧化層(ex:具有和間隙壁15相同的材料,例如二氧化矽)於底電極13上做為一電阻轉換層16,如第2H-2圖所示。 In another application, the energy/power of the plasma conditions of the oxygen plasma etching step may also be low enough to allow oxygen to penetrate the bottom electrode 13 and cause the bottom electrode 13 material to be oxidized, thus, etching in the oxygen plasma After the step, only a single layer such as an oxide layer (ex: having the same material as the spacer 15 such as hafnium oxide) is formed on the bottom electrode 13 as a resistance conversion layer 16, as shown in Fig. 2H-2.
再者,氧電漿蝕刻條件例如是(但不限制是):60B-100B偏壓(沿垂直於絕緣層11之上表面11a的方向)、30mt-60mt壓力、300W-600W功率和30s-100s蝕刻時間。再者,電阻轉換層16或間隙壁15的材料包括,但不限制於,二氧化矽(SiO2)、氧化鉿(HfO2)、氧化鈦(TiOx)、氮氧化鈦(TiON)、氧化鎢(WOx)、氧化鉭(Ta2O5)、氧化鋁(Al2O3)和其他可應用之材料。自對準多層RRAM膜(i.e.介電層162/金屬氧化層161;電阻轉換層16)的材料包括,但不限制於,二氧化矽/氧化鎢(SiO2/WOx)、二 氧化矽/氧化鉿(SiO2/HfO2)、氧化鉿/氧化鎢(HfO2/WOx)、氧化鈦/氧化鎢(TiOx/WOx)、氮氧化鈦/氧化鎢(TiON/WOx)、氧化鋁/氧化鎢(Al2O3/WOx)和其他可應用之材料。而上述該些材料僅為舉例之用,而非用以限制本揭露。 Further, the oxygen plasma etching conditions are, for example, but not limited to, 60B-100B bias (in a direction perpendicular to the upper surface 11a of the insulating layer 11), 30 mt-60 mt pressure, 300 W-600 W power, and 30 s-100 s. Etching time. Furthermore, the material of the resistance conversion layer 16 or the spacer 15 includes, but is not limited to, cerium oxide (SiO 2 ), hafnium oxide (HfO 2 ), titanium oxide (TiOx), titanium oxynitride (TiON), tungsten oxide. (WOx), yttrium oxide (Ta 2 O 5 ), alumina (Al 2 O 3 ) and other applicable materials. The material of the self-aligned multilayer RRAM film (ie dielectric layer 162 / metal oxide layer 161; resistance conversion layer 16) includes, but is not limited to, cerium oxide / tungsten oxide (SiO 2 / WOx), cerium oxide / oxidation铪 (SiO 2 /HfO 2 ), yttrium oxide / tungsten oxide (HfO 2 /WOx), titanium oxide / tungsten oxide (TiOx / WOx), titanium oxynitride / tungsten oxide (TiON / WOx), alumina / tungsten oxide ( Al 2 O 3 /WOx) and other applicable materials. The above materials are for illustrative purposes only and are not intended to limit the disclosure.
雖然第2E圖-第2G圖是繪示可以同時形成間隙壁15和電阻轉換層16的一種方式,但是間隙壁15和電阻轉換層16亦可以在不同步驟中形成。第3A圖和第3B圖繪示應用實施例之電阻轉換記憶體元件的其中兩種可能的結構。 Although FIGS. 2E to 2G are diagrams showing one manner in which the spacer 15 and the resistance conversion layer 16 can be simultaneously formed, the spacer 15 and the resistance conversion layer 16 can also be formed in different steps. 3A and 3B illustrate two possible configurations of the resistance-switching memory element of the application embodiment.
第3A圖係簡繪本揭露另一實施例之一電阻轉換記憶體元件之示意圖。第3B圖係簡繪本揭露再一實施例之一電阻轉換記憶體元件之示意圖。請同時參照第1圖。再者,第3A圖/第3B圖和第1圖中相同和/或相似元件係沿用相同和/或相似標號,且相同元件/層的構型、製法與各層功能在此不再贅述。 FIG. 3A is a schematic view showing a resistance conversion memory element of another embodiment. FIG. 3B is a schematic view showing a resistance-switching memory device according to still another embodiment. Please also refer to Figure 1. In addition, the same and/or similar elements in the 3A/3B and FIG. 1 are denoted by the same and/or similar reference numerals, and the configuration, the manufacturing method and the function of each layer of the same elements/layers are not described herein again.
在第3A圖和第3B圖中,間隙壁15的材料可以是氮化物或其他材料(例如,沈積一氮化層做為如第2E圖所示之介電層150,之後再蝕刻以形成氮化物間隙壁15)。之後,再形成電阻轉換層16於底電極13上方,如第3A圖所示。若是採用氧化製程來形成電阻轉換層,則部分的底電極13被氧化而形成電阻轉換層16,如第3B圖所示。 In FIGS. 3A and 3B, the material of the spacer 15 may be a nitride or other material (for example, depositing a nitride layer as the dielectric layer 150 as shown in FIG. 2E, and then etching to form nitrogen. The spacers 15). Thereafter, the resistance conversion layer 16 is formed over the bottom electrode 13, as shown in FIG. 3A. If an oxidation conversion process is used to form the resistance conversion layer, a portion of the bottom electrode 13 is oxidized to form the resistance conversion layer 16, as shown in FIG. 3B.
第4圖係簡繪本揭露又一實施例之一電阻轉換記憶體元件之示意圖。請同時參照第1圖。第4圖和第1圖的結構相同,除了增加了一氧離子貯藏層(oxygen ion reservoir layer)。第4 圖和第1圖中相同和/或相似元件係沿用相同和/或相似標號,且相同元件/層的構型、製法與各層功能在此不再贅述。如第4圖所示,一氧離子貯藏層19可選擇性地形成於頂電極18和電阻轉換層16之間(例如:位於一自對準之SiO2/WO3電阻轉換層之上方)以提供氧而可增進元件的電阻轉換功能。再者,氧離子貯藏層19覆蓋間隙壁15和電阻轉換層16。於一實施例中,氧離子貯藏層19的厚度係在10Å-100Å之範圍。氧離子貯藏層19的材料例如是,但不限制是,氧化鈦(TiOx)、氮氧化鈦(TiON)、氧化鉿(HfO2)、氧化鋁(Al2O3)、氧化鉭(Ta2O5)和其他可應用之材料。 FIG. 4 is a schematic view showing a resistance conversion memory element according to still another embodiment of the present invention. Please also refer to Figure 1. The structure of Fig. 4 and Fig. 1 is the same except that an oxygen ion reservoir layer is added. The same and/or similar elements in the fourth and the first drawings are denoted by the same and/or similar reference numerals, and the configuration, the manufacturing method and the functions of the layers of the same elements/layers are not described herein again. As shown in FIG. 4, an oxygen storage layer 19 can be selectively formed between the top electrode 18 and the resistance conversion layer 16 (eg, over a self-aligned SiO 2 /WO 3 resistance conversion layer). Providing oxygen enhances the resistance conversion function of the component. Further, the oxygen ion storage layer 19 covers the spacer 15 and the resistance conversion layer 16. In one embodiment, the thickness of the oxygen ion storage layer 19 is in the range of 10 Å to 100 Å. The material of the oxygen ion storage layer 19 is, for example, but not limited to, titanium oxide (TiOx), titanium oxynitride (TiON), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), and tantalum oxide (Ta 2 O). 5 ) and other applicable materials.
綜合上述,實施例之電阻轉換記憶體元件中,在形成電阻轉換層16時,間隙壁15係遮蔽導電障壁12,所以導電障壁12(ex:TiN)在形成電阻轉換層16的過程中不會產生氧化。因此,根據實施例之提出之結構和方法,可製得一個不會形成氮氧化鈦(TiON-free)的電阻轉換記憶體元件。再者,根據實施例之提出之結構和方法,可形成一個具有平滑上表面以及圓滑轉角的底電極。再者,實施例提出之方法可應用於形成一個具自對準結構的電阻轉換層。因此,應用實施例所提出之結構和方法的確可以有效改善電阻轉換記憶體元件的結構可靠度與電性表現。 In the above-described resistance conversion memory element of the embodiment, when the resistance conversion layer 16 is formed, the spacer 15 shields the conductive barrier 12, so the conductive barrier 12 (ex:TiN) does not form during the formation of the resistance conversion layer 16. Produces oxidation. Therefore, according to the structure and method proposed in the embodiment, a resistance-switching memory element which does not form titanium oxide (TiON-free) can be obtained. Further, according to the structure and method proposed in the embodiment, a bottom electrode having a smooth upper surface and a rounded corner can be formed. Furthermore, the method proposed in the embodiment can be applied to form a resistance conversion layer having a self-aligned structure. Therefore, the structure and method proposed by the application embodiments can effectively improve the structural reliability and electrical performance of the resistance-switching memory device.
其他實施例,例如元件的已知構件有不同的設置與排列等,亦可能可以應用,係視應用時之實際需求與條件而可作適當的調整或變化。因此,說明書與圖式中所示之結構僅作說明之用,並非用以限制本揭露欲保護之範圍。另外,相關技藝者當 知,實施例中構成部件的形狀和位置亦並不限於圖示所繪之態樣,亦是根據實際應用時之需求和/或製造步驟在不悖離本揭露之精神的情況下而可作相應調整。 Other embodiments, such as known components of components, may have different arrangements and arrangements, and may be applied, depending on the actual needs and conditions of the application, and may be appropriately adjusted or changed. Therefore, the structures shown in the specification and drawings are for illustrative purposes only and are not intended to limit the scope of the disclosure. In addition, the relevant artisan It is to be understood that the shapes and positions of the components in the embodiments are not limited to those illustrated in the drawings, and may be made according to the needs and/or manufacturing steps of the actual application without departing from the spirit of the disclosure. Adjust accordingly.
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
11‧‧‧絕緣層 11‧‧‧Insulation
11a‧‧‧絕緣層之上表面 11a‧‧‧Top surface of insulation
12‧‧‧導電障壁 12‧‧‧Electrical barrier
121‧‧‧第一障壁層 121‧‧‧First barrier layer
122‧‧‧第二障壁層 122‧‧‧Second barrier layer
t1‧‧‧第一障壁厚度 T1‧‧‧First barrier thickness
t2‧‧‧第二障壁厚度 T2‧‧‧second barrier thickness
13‧‧‧底電極 13‧‧‧ bottom electrode
131‧‧‧底電極之下部 131‧‧‧Under the bottom electrode
132‧‧‧底電極之上部 132‧‧‧Top part of the bottom electrode
132a‧‧‧底電極上部之上表面 132a‧‧‧ Upper surface of the upper part of the bottom electrode
132b‧‧‧底電極之側壁 132b‧‧‧ sidewall of the bottom electrode
15‧‧‧間隙壁 15‧‧‧ clearance
152‧‧‧氧化物薄膜 152‧‧‧Oxide film
ts‧‧‧間隙壁的厚度 Ts‧‧‧ thickness of the spacer
16‧‧‧電阻轉換層 16‧‧‧resistive conversion layer
16c‧‧‧電阻轉換層之底表面 16c‧‧‧ bottom surface of the resistance conversion layer
18‧‧‧頂電極 18‧‧‧ top electrode

Claims (9)

  1. 一種電阻轉換記憶體元件,包括:一絕緣層具有一上表面;一底電極,埋置於該絕緣層中,該底電極之一上部突出於該絕緣層之該上表面且該上部之邊緣具有圓滑轉角,該底電極之一下部填滿該絕緣層之一孔洞;一障壁層,位於該孔洞內以隔開該絕緣層和該底電極,該障壁層包括:具有一第一障壁厚度之一第一障壁層,和形成於該第一障壁層上且具有一第二障壁厚度之一第二障壁層,其中該第二障壁厚度係小於該第一障壁厚度;一電阻轉換層,設置於該底電極上;和一頂電極,形成於該電阻轉換層上並覆蓋該電阻轉換層。 A resistance-switching memory device, comprising: an insulating layer having an upper surface; a bottom electrode embedded in the insulating layer, an upper portion of the bottom electrode protruding from the upper surface of the insulating layer and having an edge at the upper portion a smooth corner, a lower portion of the bottom electrode filling a hole of the insulating layer; a barrier layer located in the hole to separate the insulating layer and the bottom electrode, the barrier layer comprising: having a thickness of a first barrier a first barrier layer, and a second barrier layer formed on the first barrier layer and having a second barrier thickness, wherein the second barrier thickness is less than the first barrier thickness; a resistance conversion layer is disposed on the And a top electrode formed on the resistance conversion layer and covering the resistance conversion layer.
  2. 如申請專利範圍第1項所述之電阻轉換記憶體元件,其中該障壁層設置於該底電極之該上部與該絕緣層之間,且該障壁層位於該絕緣層之該上表面的下方。 The resistance-switching memory device of claim 1, wherein the barrier layer is disposed between the upper portion of the bottom electrode and the insulating layer, and the barrier layer is located below the upper surface of the insulating layer.
  3. 如申請專利範圍第1項所述之電阻轉換記憶體元件,更包括間隙壁形成於該絕緣層上且位於該底電極之該上部的側壁處。 The resistance-switching memory device of claim 1, further comprising a spacer formed on the insulating layer and located at a sidewall of the upper portion of the bottom electrode.
  4. 如申請專利範圍第1項所述之電阻轉換記憶體元件,其中該電阻轉換層係為一雙層結構。 The resistance conversion memory element according to claim 1, wherein the resistance conversion layer is a two-layer structure.
  5. 如申請專利範圍第1項所述之電阻轉換記憶體元件,其中 該障壁層係為一導電障壁位於該孔洞內以隔開該絕緣層和該底電極之該上部與該下部。 The resistance conversion memory component according to claim 1, wherein The barrier layer is a conductive barrier located in the hole to separate the upper portion and the lower portion of the insulating layer and the bottom electrode.
  6. 如申請專利範圍第1項所述之電阻轉換記憶體元件,更包括一氧離子貯藏層位於該頂電極和該電阻轉換層之間。 The resistance-switching memory device of claim 1, further comprising an oxygen ion storage layer between the top electrode and the resistance conversion layer.
  7. 一種電阻轉換記憶體元件之製造方法,包括:提供具有一孔洞之一絕緣層;形成一底電極填滿該絕緣層之該孔洞,其中該底電極之一上部突出於該絕緣層之上,且該上部之邊緣具有圓滑轉角;設置一電阻轉換層於該底電極上;和形成一頂電極於該電阻轉換層上並覆蓋該電阻轉換層。 A method of manufacturing a resistance-switching memory device, comprising: providing an insulating layer having a hole; forming a hole in which a bottom electrode fills the insulating layer, wherein an upper portion of the bottom electrode protrudes above the insulating layer, and The upper edge has a rounded corner; a resistance conversion layer is disposed on the bottom electrode; and a top electrode is formed on the resistance conversion layer and covers the resistance conversion layer.
  8. 如申請專利範圍第7項所述之製造方法,其中係以一氧化抛光製程將該絕緣層分地移除,以形成具有一平滑上表面的該底電極。 The manufacturing method of claim 7, wherein the insulating layer is removed in an oxidative polishing process to form the bottom electrode having a smooth upper surface.
  9. 如申請專利範圍第7項所述之製造方法,更包括:形成一氧化層於該絕緣層和該底電極上;和對該氧化層非等向性地進行一氧電漿蝕刻製程,其中在該氧電漿蝕刻製程後,係形成間隙壁於圍繞該底電極之該上部的側壁處,且同時產生具有一自對準結構的該電阻轉換層。 The manufacturing method of claim 7, further comprising: forming an oxide layer on the insulating layer and the bottom electrode; and performing an oxygen plasma etching process on the oxide layer in an isotropic manner, wherein After the oxygen plasma etching process, a spacer is formed at a sidewall surrounding the upper portion of the bottom electrode, and at the same time, the resistance conversion layer having a self-aligned structure is produced.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200828516A (en) * 2006-12-06 2008-07-01 Macronix Int Co Ltd Method for making a self-converged void and bottom electrode for memory cell
TW200845363A (en) * 2007-05-02 2008-11-16 Ind Tech Res Inst Methods for reducing a contact area between heating electrode and phase-change material layer, phase-change memory devices and methods for fabricating the same
TW201006020A (en) * 2008-07-24 2010-02-01 Hynix Semiconductor Inc Resistive memory device and method of fabricating the same
TW201314982A (en) * 2011-09-14 2013-04-01 Renesas Electronics Corp Resistance change nonvolatile memory device, semiconductor device, and method of operating resistance change nonvolatile memory device
US8598011B2 (en) * 2009-12-18 2013-12-03 Hynix Semiconductor Inc. Resistive memory device and method for fabricating the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200828516A (en) * 2006-12-06 2008-07-01 Macronix Int Co Ltd Method for making a self-converged void and bottom electrode for memory cell
TW200845363A (en) * 2007-05-02 2008-11-16 Ind Tech Res Inst Methods for reducing a contact area between heating electrode and phase-change material layer, phase-change memory devices and methods for fabricating the same
TW201006020A (en) * 2008-07-24 2010-02-01 Hynix Semiconductor Inc Resistive memory device and method of fabricating the same
US8598011B2 (en) * 2009-12-18 2013-12-03 Hynix Semiconductor Inc. Resistive memory device and method for fabricating the same
TW201314982A (en) * 2011-09-14 2013-04-01 Renesas Electronics Corp Resistance change nonvolatile memory device, semiconductor device, and method of operating resistance change nonvolatile memory device

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