TW201913834A - 半導體結構及其製作方法 - Google Patents

半導體結構及其製作方法 Download PDF

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Publication number
TW201913834A
TW201913834A TW106139725A TW106139725A TW201913834A TW 201913834 A TW201913834 A TW 201913834A TW 106139725 A TW106139725 A TW 106139725A TW 106139725 A TW106139725 A TW 106139725A TW 201913834 A TW201913834 A TW 201913834A
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Taiwan
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substrate
die
dielectric layer
conductive member
conductive
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TW106139725A
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English (en)
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陳明發
邱文智
葉松峯
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台灣積體電路製造股份有限公司
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Publication of TW201913834A publication Critical patent/TW201913834A/zh

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Abstract

根據本發明之一些實施例，一種半導體結構包括：基板；第一晶粒，其安置於該基板上方；第二晶粒，其安置於該基板上方；模製物，其安置於該基板上方且環繞該第一晶粒及該第二晶粒；互連結構，其包括介電層及導電部件，其中該介電層安置於該第一晶粒、該第二晶粒及該模製物上方，且該等導電部件由該介電層環繞；及通路，其延伸於該第二晶粒內且延伸於該介電層與該基板之間。

Description

半導體結構及其製作方法
本揭示係關於半導體結構及其製作方法。
使用半導體裝置之電子設備對於許多現代應用而言係必需的。隨著電子技術之進步，半導體裝置之尺寸正變得愈來愈小，同時具有更大功能性及更大量之積體電路。由於半導體裝置之小型化尺度，晶圓上晶片(CoW)廣泛用於將若干晶片整合至單個半導體裝置中。在CoW操作期間，數個晶片被組裝於單個半導體裝置上。此外，眾多製作操作被實施於此類小半導體裝置內。 然而，半導體裝置之製作操作係關於對此類小且薄之半導體裝置進行的許多步驟及操作。以小型化尺度製作半導體裝置變得更複雜。製作半導體裝置之複雜度增加可造成例如不良電氣互連、組件分層或其他問題之缺陷，從而導致半導體裝置之高收得率損失且增加製作成本。因而，存在用於修改半導體裝置之結構且改良製作操作的許多挑戰。
根據本發明之一實施例，一種半導體結構包含：基板；第一晶粒，其安置於該基板上方；第二晶粒，其安置於該基板上方；模製物，其安置於該基板上方且環繞該第一晶粒及該第二晶粒；互連結構，其包括介電層及導電部件，其中該介電層安置於該第一晶粒、該第二晶粒及該模製物上方，且該等導電部件由該介電層環繞；及通路，其延伸於該第二晶粒內且延伸於該介電層與該基板之間。 根據本發明之一實施例，一種半導體結構包含：基板；第一晶粒，其安置於該基板上方且包括第一晶粒基板、安置於該第一晶粒基板與該基板之間的第一介電層，及由該第一介電層環繞之第一導電部件；第二晶粒，其安置於該基板上方且包括第二晶粒基板、安置於該第二晶粒基板與該基板之間的第二介電層、由該第二介電層環繞之第二導電部件、安置於該第二晶粒基板上方的第三介電層，及由該第三介電層環繞之第三導電部件；模製物，其安置於該基板上方且環繞該第一晶粒及該第二晶粒；及複數個通路，其延伸於該第二介電層與該第三介電層之間穿過該第二晶粒基板。 根據本發明之一實施例，一種製作半導體結構之方法包含：提供基板；將第一晶粒安置於該基板上方；提供第二晶粒，該第二晶粒包括延伸於該第二晶粒內之通路；將該第二晶粒安置於該基板上方；圍繞該第一晶粒及該第二晶粒形成模製物；及形成包括介電層及導電部件之互連結構，其中該介電層安置於該模製物、該第一晶粒及該第二晶粒上方，且該等導電部件由該介電層環繞，其中藉由移除該第二晶粒之一部分以形成延伸於該第二晶粒內之凹槽且將導電材料安置至該凹槽中而形成該等通路。
以下揭示內容提供用於實施所提供之主題之不同特徵件的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭示。當然，此等特定實例僅為實例，且不意欲具限制性。舉例而言，在以下描述中在第二特徵件上方或上形成第一特徵件可包括其中第一及第二特徵件經形成直接接觸之實施例，且亦可包括其中額外特徵件可經形成於第一特徵件與第二特徵件之間使得第一與第二特徵件可能並不直接接觸之實施例。另外，在各種實例中，本揭示可重複元件符號及/或字母。此重複係出於簡化及清楚之目的且其本身並不指示所論述之各種實施例及/或組態之間的關係。 此外，為了便於描述，本文中可使用空間相對術語，例如「在…下方」、「在…下面」、「下部」、「在…上面」、「上部」等等來描述如圖中所說明之一個元件或特徵件與另一(另外)元件或特徵件的關係。空間相對術語意欲涵蓋裝置在使用或操作中除圖中所描繪之定向之外的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中使用之空間相對描述符可同樣地因此而解譯。 在此文檔中，術語「耦接」亦可稱為「電耦接」，且術語「連接」亦可稱為「電連接」。亦可使用「耦接」及「連接」來指示兩個或多於兩個元件彼此合作或相互作用。 亦可包括其他特徵或過程。舉例而言，可包括測試結構以協助3D封裝或3DIC裝置之驗證測試。測試結構可包括例如形成於重新分佈層中或基板上之測試墊，該基板允許測試3D封裝或3DIC、使用探針及/或探針板等等。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭示之結構及方法可連同結合已知良好晶粒之中間驗證來增加收得率且降低成本的測試方法學一起使用。 半導體結構係藉由數種操作來製作。在半導體結構之製作期間，具有不同功能性及尺寸之半導體晶片被整合至單個模組中。半導體晶片安置於基板或晶圓上，且模製物經形成以囊封半導體晶片，且接著，若干連接器安置於模製物及半導體晶片上以電連接基板及半導體晶片與外部電路。半導體晶片及基板可藉由形成於模製物內之若干通路(例如模製物通孔(TMV)、積體電路通孔(TIV)等等)而與外部電路電通信。然而，呈此類組態之半導體結構具有大形狀因子，通路之間具有大間距(例如大於200 um)，且具有小I/O計數，此係不合意的且可能不滿足需求。 在本揭示中，揭示一種半導體結構。半導體結構包括：基板；第一晶粒，其安置於基板上；第二晶粒，其安置於基板上；若干通路，其延伸於第二晶粒內；模製物，其安置於基板上且環繞第一晶粒及第二晶粒；互連結構，其安置於模製物、第一晶粒及第二晶粒上方；及導電凸塊，其安置於互連結構上方。基板及第一晶粒藉由通路而與RDL及導電凸塊電連接。第二晶粒中之通路可以小間距(例如小於10 um)而組態。因而，可增加I/O端子之數目，可減小或最小化半導體結構之整體尺寸，且可增強半導體結構之電氣效能。 圖1係根據本發明之各種實施例之半導體結構100的示意橫截面圖。在一些實施例中，半導體結構100包括基板101、第一晶粒102、第二晶粒103、模製物104、互連結構105及第一導電凸塊107。 在一些實施例中，半導體結構100係半導體封裝。在一些實施例中，半導體結構100係整合扇出型(InFO)封裝，其中第一晶粒102或第二晶粒103之I/O端子被扇出且被重新分佈於第一晶粒102或第二晶粒103之表面上方的更大區域中。在一些實施例中，半導體結構100係三維積體電路(3D IC)。在一些實施例中，半導體結構100係晶圓上晶片(CoW)結構。在一些實施例中，半導體結構100係系統級封裝(SiP)結構。 在一些實施例中，基板101係半導電基板。在一些實施例中，基板101係載體、晶圓、中介層等等。在一些實施例中，基板101係矽晶圓或矽中介層。在一些實施例中，基板101包括半導電材料，例如矽、鍺、鎵、砷或其組合。在一些實施例中，基板101包括例如陶瓷、玻璃、聚合物等等之材料。在一些實施例中，基板101包括有機材料。在一些實施例中，基板101被製造為在其上具有預定功能電路。在一些實施例中，基板101包括安置於基板101內之若干導電跡線及若干電氣組件，例如電晶體、二極體等等。在一些實施例中，基板101包括應用處理器(AP)。在一些實施例中，基板101具有四邊形、矩形、正方形、多邊形或任何其他合適形狀。 在一些實施例中，基板101包括第一表面101a-1及與第一表面101a-1相對之第二表面101a-2。在一些實施例中，第一表面101a-1係基板101之前側，且第二表面101a-2係基板101之背側。在一些實施例中，第一表面101a-1係被安置有若干電氣組件之作用側。在一些實施例中，第二表面101a-2係未被安置有電氣組件之非作用側。 在一些實施例中，基板介電層101b安置於基板101上方或上。在一些實施例中，基板介電層101b安置於基板101之第一表面101a-1上方。在一些實施例中，基板介電層101b包括堆疊在彼此上方的若干介電材料層。在一些實施例中，基板介電層101b包括介電材料，例如氧化矽、氮化矽、無摻雜矽玻璃等等。在一些實施例中，基板介電層101b包括聚合材料。在一些實施例中，基板介電層101b包括聚醯亞胺(PI)、聚苯并噁唑(PBO)等等。 在一些實施例中，基板導電部件101c安置於基板101上方且由基板介電層101b環繞。在一些實施例中，基板導電部件101c安置於基板介電層101b內或上方。在一些實施例中，基板導電部件101c延伸於基板介電層101b內。在一些實施例中，基板導電部件101c延伸穿過基板介電層101b之一或多個層。在一些實施例中，基板導電部件101c包括導電材料，例如金、銀、銅、鎳、鎢、鋁、錫及/或其合金。 在一些實施例中，基板導電部件101c包括基板連接盤(land)部分101c-1，及自基板連接盤部分101c-1延伸且與基板連接盤部分101c-1耦接之基板通路部分101c-2。在一些實施例中，基板連接盤部分101c-1橫向地延伸於基板介電層101b內或上方。在一些實施例中，基板通路部分101c-2垂直地延伸於基板介電層101b內且穿過基板介電層101b之至少一個層。在一些實施例中，基板連接盤部分101c-1及基板通路部分101c-2堆疊在彼此上方。在一些實施例中，基板連接盤部分101c-1及基板通路部分101c-2交替地堆疊。 在一些實施例中，基板連接盤部分101c-1安置於基板介電層101b上方。在一些實施例中，基板連接盤部分101c-1至少部分地自基板介電層101b曝露。在一些實施例中，基板連接盤部分101c-1係接合墊，其用於收納、接合或電連接導電結構或電路。 在一些實施例中，第一晶粒102安置於基板101上方或上。在一些實施例中，第一晶粒102安置於基板101之第一表面101a-1上方或上。在一些實施例中，第一晶粒102安置於基板介電層101b上方或上。在一些實施例中，第一晶粒102被製造為在第一晶粒102內具有預定功能電路。在一些實施例中，第一晶粒102藉由機械或雷射刀片而自半導電晶圓單粒化。在一些實施例中，第一晶粒102包含適合於特定應用之多種電氣電路。在一些實施例中，電氣電路包括各種裝置，例如電晶體、電容器、電阻器、二極體等等。 在一些實施例中，第一晶粒102係邏輯裝置晶粒、圖形處理單元(GPU)晶粒、應用處理(AP)晶粒、記憶體晶粒、動態隨機存取記憶體(DRAM)晶粒、高頻寬記憶體(HBM)晶粒等等。在一些實施例中，第一晶粒102係晶片或封裝。在一些實施例中，第一晶粒102具有呈四邊形、矩形或正方形形狀之頂部橫截面(自如圖1所展示之半導體結構100之俯視圖來看的橫截面)。 在一些實施例中，第一晶粒102包括第一晶粒基板102a、安置於第一晶粒基板102a與基板101之間的第一介電層102b，及由第一介電層102b環繞之第一導電部件102c。在一些實施例中，第一晶粒基板102a包括半導電材料，例如矽或其他合適材料。在一些實施例中，第一晶粒基板102a係矽基板。在一些實施例中，第一晶粒基板102a包括安置於第一晶粒基板102上方或中的若干電路及一或多個主動元件，例如電晶體等等。在一些實施例中，第一晶粒基板102a包括第三表面102a-1、與第三表面102a-1相對之第四表面102a-2，及基本上正交於第三表面102a-1及第四表面102a-2之側壁102a-3。在一些實施例中，第三表面102a-1係被安置有若干電氣組件之作用側。在一些實施例中，第四表面102a-2係未被安置有電氣組件之非作用側。 在一些實施例中，第一介電層102b安置於第一晶粒基板102a與基板101之間。在一些實施例中，第一介電層102b安置於第一晶粒基板102a下面。在一些實施例中，第一介電層102b安置於基板介電層101b上。在一些實施例中，第一介電層102b接觸基板介電層101b。在一些實施例中，第一介電層102b包括堆疊在彼此上方的若干介電材料層。 在一些實施例中，第一界面102d安置於基板介電層101b與第一介電層102b之間。在一些實施例中，第一界面102d水平地延伸。在一些實施例中，第一界面102d基本上平行於第三表面102a-1及第四表面102a-2，且基本上正交於第一晶粒102之側壁102a-3。在一些實施例中，第一介電層102b包括介電材料，例如氧化矽、氮化矽、無摻雜矽玻璃等等。在一些實施例中，第一介電層102b包括聚合材料。在一些實施例中，第一介電層102b包括聚醯亞胺(PI)、聚苯并噁唑(PBO)等等。 在一些實施例中，第一導電部件102c由第一介電層102b環繞。在一些實施例中，第一導電部件102c安置於第一介電層102b內或上方。在一些實施例中，第一導電部件102c延伸於第一介電層102b內。在一些實施例中，第一導電部件102c延伸穿過第一介電層102b之一或多個層。在一些實施例中，第一導電部件102c經組態以自第一晶粒基板102a路由電路路徑且重新分佈第一晶粒基板102a之I/O端子。在一些實施例中，第一導電部件102c經組態以電連接第一晶粒102與在第一晶粒102外部之電路或導電結構。在一些實施例中，第一導電部件102c與基板導電部件101c電連接。在一些實施例中，第一導電部件102c安置於基板導電部件101c上且與基板導電部件101c接合，使得第一晶粒102電連接至基板101。 在一些實施例中，第二界面102e安置於基板導電部件101c與第一導電部件102c之間。在一些實施例中，第二界面102e水平地延伸。在一些實施例中，第二界面102e基本上平行於第三表面102a-1及第四表面102a-2，且基本上正交於第一晶粒102之側壁102a-3。在一些實施例中，第一導電部件102c包括導電材料，例如金、銀、銅、鎳、鎢、鋁、錫及/或其合金。 在一些實施例中，第一導電部件102c包括第一連接盤部分102c-1，及自第一連接盤部分102c-1延伸且與第一連接盤部分102c-1耦接之第一通路部分102c-2。在一些實施例中，第一連接盤部分102c-1橫向地延伸於第一介電層102b內或上方。在一些實施例中，第一通路部分102c-2垂直地延伸於第一介電層102b內且穿過第一介電層102b之至少一個層。在一些實施例中，第一連接盤部分102c-1及第一通路部分102c-2堆疊在彼此上方。在一些實施例中，第一連接盤部分102c-1及第一通路部分102c-2交替地堆疊。 在一些實施例中，第一連接盤部分102c-1安置於第一介電層102b上方。在一些實施例中，第一連接盤部分102c-1至少部分地自第一介電層102b曝露。在一些實施例中，第一連接盤部分102c-1係接合墊，其用於收納、接合或電連接導電結構或電路。在一些實施例中，第一連接盤部分102c-1安置於基板連接盤部分101c-1上且與基板連接盤部分101c-1接合。 在一些實施例中，第二晶粒103安置於基板101上方或上。在一些實施例中，第二晶粒103安置於基板101之第一表面101a-1上方或上。在一些實施例中，第二晶粒103安置於基板介電層101b上方或上。在一些實施例中，第二晶粒103被製造為在第二晶粒103內具有預定功能電路。在一些實施例中，第二晶粒103藉由機械或雷射刀片而自半導電晶圓單粒化。在一些實施例中，第二晶粒103包含適合於特定應用之多種電氣電路。在一些實施例中，電氣電路包括各種裝置，例如電晶體、電容器、電阻器、二極體等等。在一些實施例中，第二晶粒103係功能晶粒。 在一些實施例中，第一晶粒102係邏輯裝置晶粒、圖形處理單元(GPU)晶粒、應用處理(AP)晶粒、記憶體晶粒、動態隨機存取記憶體(DRAM)晶粒、高頻寬記憶體(HBM)晶粒等等。在一些實施例中，第二晶粒103係晶片或封裝。在一些實施例中，第二晶粒103係虛設晶粒。在一些實施例中，第二晶粒103具有呈四邊形、矩形或正方形形狀之頂部橫截面(自如圖1所展示之半導體結構100之俯視圖來看的橫截面)。在一些實施例中，第一晶粒102之厚度與第二晶粒103之厚度基本上不同或相同。 在一些實施例中，第二晶粒103包括第二晶粒基板103a、安置於第二晶粒基板103a與基板101之間的第二介電層103b，及由第二介電層103b環繞之第二導電部件103c。在一些實施例中，第二晶粒基板103a包括半導電材料，例如矽或其他合適材料。在一些實施例中，第二晶粒基板103a係矽基板。在一些實施例中，第二晶粒基板103a包括安置於第二晶粒基板103a上方或中之若干電路及一或多個主動元件，例如電晶體等等。在一些實施例中，第二晶粒基板103a包括第五表面103a-1、與第五表面103a-1相對之第六表面103a-2，及基本上正交於第五表面103a-1及第六表面103a-2之側壁103a-3。在一些實施例中，第五表面103a-1係被安置有若干電氣組件之作用側。在一些實施例中，第六表面103a-2係未被安置有電氣組件之非作用側。 在一些實施例中，第二介電層103b安置於第二晶粒基板103a與基板101之間。在一些實施例中，第二介電層103b安置於第二晶粒基板103a下面。在一些實施例中，第二介電層103b安置於基板介電層101b上。在一些實施例中，第二介電層103b接觸基板介電層101b。在一些實施例中，第二介電層103b包括堆疊在彼此上方的若干介電材料層。 在一些實施例中，第三界面103d安置於基板介電層101b與第二介電層103b之間。在一些實施例中，第三界面103d水平地延伸。在一些實施例中，第三界面103d基本上平行於第五表面103a-1及第六表面103a-2，且基本上正交於第二晶粒103之側壁103a-3。在一些實施例中，第二介電層103b包括介電材料，例如氧化矽、氮化矽、無摻雜矽玻璃等等。在一些實施例中，第二介電層103b包括聚合材料。在一些實施例中，第二介電層103b包括聚醯亞胺(PI)、聚苯并噁唑(PBO)等等。 在一些實施例中，第二導電部件103c由第二介電層103b環繞。在一些實施例中，第二導電部件103c安置於第二介電層103b內或上方。在一些實施例中，第二導電部件103c延伸於第二介電層103b內。在一些實施例中，第二導電部件103c延伸穿過第二介電層103b之一或多個層。在一些實施例中，第二導電部件103c經組態以自第二晶粒基板103a路由電路路徑且重新分佈第二晶粒基板103a之I/O端子。在一些實施例中，第二導電部件103c經組態以電連接第二晶粒103與在第二晶粒103外部之電路或導電結構。在一些實施例中，第二導電部件103c與基板導電部件101c電連接。在一些實施例中，第二導電部件103c安置於基板導電部件101c上且與基板導電部件101c接合，使得第二晶粒103電連接至基板101。 在一些實施例中，第四界面103e安置於基板導電部件101c與第二導電部件103c之間。在一些實施例中，第四界面103e水平地延伸。在一些實施例中，第四界面103e基本上平行於第五表面103a-1及第六表面103a-2，且基本上正交於第二晶粒103之側壁103a-3。在一些實施例中，第二導電部件103c包括導電材料，例如金、銀、銅、鎳、鎢、鋁、錫及/或其合金。 在一些實施例中，第二導電部件103c包括第二連接盤部分103c-1，及自第二連接盤部分103c-1延伸且與第二連接盤部分103c-1耦接之第二通路部分103c-2。在一些實施例中，第二連接盤部分103c-1橫向地延伸於第二介電層103b內或上方。在一些實施例中，第二通路部分103c-2垂直地延伸於第二介電層103b內且穿過第二介電層103b之至少一個層。在一些實施例中，第二連接盤部分103c-1及第二通路部分103c-2堆疊在彼此上方。在一些實施例中，第二連接盤部分103c-1及第二通路部分103c-2交替地堆疊。 在一些實施例中，第二連接盤部分103c-1安置於第二介電層103b上方。在一些實施例中，第二連接盤部分103c-1至少部分地自第二介電層103b曝露。在一些實施例中，第二連接盤部分103c-1係接合墊，其用於收納、接合或電連接導電結構或電路。在一些實施例中，第二連接盤部分103c-1安置於基板連接盤部分101c-1上且與基板連接盤部分101c-1接合。 在一些實施例中，第二晶粒103包括安置於第二晶粒基板103a上之第三介電層103f，及由第三介電層103f環繞之第三導電部件103g。在一些實施例中，第三介電層103f安置於第二晶粒103之第六表面103a-2上方或上。在一些實施例中，第三介電層103f包括堆疊在彼此上方的若干介電材料層。在一些實施例中，第三介電層103f包括介電材料，例如氧化矽、氮化矽、無摻雜矽玻璃等等。在一些實施例中，第三介電層103f包括聚合材料。在一些實施例中，第二介電層103b包括聚醯亞胺(PI)、聚苯并噁唑(PBO)等等。 在一些實施例中，第三導電部件103g安置於第三介電層103f內或上方。在一些實施例中，第三導電部件103g延伸於第三介電層103f內。在一些實施例中，第三導電部件103g延伸穿過第三介電層103f之一或多個層。在一些實施例中，第三導電部件103g經組態以電連接第二晶粒103與在第二晶粒103外部之電路或導電結構。在一些實施例中，第三導電部件103g包括導電材料，例如金、銀、銅、鎳、鎢、鋁、錫及/或其合金。 在一些實施例中，若干通路103h延伸於第二晶粒103內。在一些實施例中，通路103h延伸穿過第二晶粒基板103a。在一些實施例中，通路103h延伸於第二介電層103b與第三介電層103f之間。在一些實施例中，通路103h與第二導電部件103c及第三導電部件103g電連接且延伸於第二導電部件103c與第三導電部件103g之間。在一些實施例中，基板導電部件101c藉由通路103h及第二導電部件103c而與第三導電部件103g電連接。在一些實施例中，通路103h由第二晶粒基板103、第二介電層103b及第三介電層103f環繞。在一些實施例中，通路103h垂直地延伸於第二晶粒103內。在一些實施例中，通路103h包括導電材料，例如銅、銀、金、鋁等等。在一些實施例中，通路103h係基板通孔或矽通孔(TSV)。在一些實施例中，兩個鄰近通路103h之間的距離D基本上小於或等於10 um。在一些實施例中，距離D基本上小於20 um。 在一些實施例中，模製物104安置於基板101上方或上。在一些實施例中，模製物104環繞第一晶粒102及第二晶粒103。在一些實施例中，模製物104接觸第一晶粒102之第四表面102a-2及側壁102a-3。在一些實施例中，模製物104接觸第二晶粒103之側壁103a-3。在一些實施例中，模製物104安置於第一晶粒102與第二晶粒103之間。在一些實施例中，模製物104安置於基板介電層101b上。在一些實施例中，第三介電層至少部分地自模製物104曝露。在一些實施例中，模製物104可為單層膜或複合堆疊。在一些實施例中，模製物104具有高導熱性、低吸濕率及高撓曲強度。在一些實施例中，模製物104包括各種材料，例如模塑膠、模製底膠、環氧樹脂、樹脂等等。在一些實施例中，模製物104包括氧化物，例如氧化矽等等。 在一些實施例中，互連結構105安置於模製物104、第一晶粒102及第二晶粒103上方或上。在一些實施例中，互連結構105係重新分佈層(RDL)或後鈍化互連件(PPI)。在一些實施例中，互連結構105包括第四介電層105a及第四導電部件105b。 在一些實施例中，第四介電層105a安置於模製物104、第一晶粒102及第二晶粒103上方或上。在一些實施例中，第四介電層105a接觸模製物104及第三介電層103f。在一些實施例中，模製物104安置於第一晶粒102與第四介電層105a之間。在一些實施例中，通路103h安置於第四介電層105a與基板101之間。在一些實施例中，通路103h安置於第四介電層105a與基板介電層101b之間。在一些實施例中，第四介電層105a包括堆疊在彼此上方的若干介電材料層。在一些實施例中，第四介電層105a包括介電材料，例如氧化矽、氮化矽、無摻雜矽玻璃等等。在一些實施例中，第四介電層105a包括聚合材料。在一些實施例中，第四介電層105a包括聚醯亞胺(PI)、聚苯并噁唑(PBO)等等。 在一些實施例中，第四導電部件105b由第四介電層105a環繞。在一些實施例中，第四導電部件105b安置於第四介電層105a內或上方。在一些實施例中，第四導電部件105b延伸於第四介電層105a內。在一些實施例中，第四導電部件105b延伸穿過第四介電層105a之一或多個層。在一些實施例中，第四導電部件105b經組態以自第一晶粒102或第二晶粒103路由電路路徑且重新分佈第一晶粒102或第二晶粒103之I/O端子。在一些實施例中，第四導電部件105b經組態以電連接基板101、第一晶粒102或第二晶粒103與在基板101、第一晶粒102或第二晶粒103外部之電路或導電結構。在一些實施例中，第四導電部件105b與第三導電部件103g、通路103h、第二導電部件103c、第一導電部件102c或基板導電部件101c電連接。在一些實施例中，第四導電部件105b與第三導電部件103g或通路103h電連接及接合。在一些實施例中，基板101藉由通路103h而與第四導電部件105b電連接。在一些實施例中，第一晶粒102藉由基板101及通路103h而與第四導電部件105b電連接。在一些實施例中，第四導電部件105b包括導電材料，例如金、銀、銅、鎳、鎢、鋁、錫及/或其合金。 在一些實施例中，第四導電部件105b包括第四連接盤部分105b-1，及自第四連接盤部分105b-1延伸且與第四連接盤部分105b-1耦接之第四通路部分105b-2。在一些實施例中，第四連接盤部分105b-1橫向地延伸於第四介電層105a內或上方。在一些實施例中，第四通路部分105b-2垂直地延伸於第四介電層105a內且穿過第四介電層105a之至少一個層。在一些實施例中，第四連接盤部分105b-1及第四通路部分105b-2堆疊在彼此上方。在一些實施例中，第四連接盤部分105b-1及第四通路部分105b-2交替地堆疊。 在一些實施例中，凸塊墊106安置於互連結構105上方或上。在一些實施例中，凸塊墊106安置於第四導電部件105b上方且與第四導電部件105b電連接。在一些實施例中，凸塊墊106安置於第四介電層105a上方或由第四介電層105a環繞。在一些實施例中，凸塊墊106至少部分地自第四介電層105a曝露。在一些實施例中，凸塊墊106經組態以收納導電部件等等。在一些實施例中，凸塊墊106係凸塊下金屬化物(UBM)墊。在一些實施例中，凸塊墊106與第四導電部件105b、第三導電部件103g、通路103h、第二導電部件103c、第一導電部件102c或基板導電部件101c電連接。 在一些實施例中，第一導電凸塊107安置於互連結構105上方或上。在一些實施例中，第一導電凸塊107安置於第四導介電層105a上方或上且與第四導電部件105b電連接。在一些實施例中，第一導電凸塊107安置於凸塊墊106上且與凸塊墊106接合。在一些實施例中，第一導電凸塊107包括導電材料，例如包括焊料、銅、鎳、金等等。在一些實施例中，第一導電凸塊107係焊球、球柵陣列(BGA)球、可控塌陷晶片連接(C4)凸塊、支柱等等。在一些實施例中，第一導電凸塊107呈球形、半球形或圓柱形形狀。 圖2係根據本發明之各種實施例之半導體結構200的示意橫截面圖。在一些實施例中，半導體結構200包括基板101、第一晶粒102、第二晶粒103、模製物104、互連結構105及第一導電凸塊107，它們具有與上文所描述或圖1所說明之組態類似的組態。 在一些實施例中，第二導電凸塊108安置於第一晶粒102與基板101之間或安置於第二晶粒103與基板101之間。在一些實施例中，第二導電凸塊108安置於第一導電部件102c與基板導電部件101c之間。在一些實施例中，第二導電凸塊108安置於第二導電部件103c與基板導電部件101c之間。在一些實施例中，第一導電部件102c與基板導電部件101c藉由第二導電凸塊108而電連接。在一些實施例中，第二導電部件103c與基板導電部件101c藉由第二導電凸塊108而電連接。在一些實施例中，第一晶粒102藉由第二導電凸塊108而與基板101電連接。在一些實施例中，第二晶粒103藉由第二導電凸塊108而與基板101電連接。在一些實施例中，第二導電凸塊108包括導電材料，例如包括焊料、銅、鎳、金等等。在一些實施例中，第二導電凸塊108係微凸塊、支柱等等。在一些實施例中，第二導電凸塊108呈球形、半球形或圓柱形形狀。 在一些實施例中，第二導電凸塊108由底膠材料109環繞。在一些實施例中，底膠材料109環繞第一晶粒102之一部分或第二晶粒103之一部分。在一些實施例中，底膠材料109環繞第一介電層102b或第二介電層103b。在一些實施例中，底膠材料109安置於基板介電層101b上方或上。在一些實施例中，底膠材料109填充兩個鄰近第二導電凸塊108之間的間隔。在一些實施例中，底膠材料109係電絕緣黏著劑，其用於保護第二導電凸塊108或固定第一晶粒102與基板101之間或第二晶粒103與基板101之間的接合。在一些實施例中，底膠材料109包括環氧樹脂、樹脂、環氧樹脂模塑膠等等。 圖3係根據本發明之各種實施例之半導體結構300的示意橫截面圖。在一些實施例中，半導體結構300包括基板101、模製物104、互連結構105及第一導電凸塊107，它們具有與上文所描述或圖1或2所說明之組態類似的組態。 在一些實施例中，半導體結構300包括在模製物104內且堆疊在彼此上方的若干第二晶粒103。在一些實施例中，第二晶粒103堆疊在基板101上方。在一些實施例中，第二晶粒103具有與上文所描述或圖1或2所說明之組態類似的組態。在一些實施例中，第二晶粒103藉由安置於第二晶粒103內之若干通路103h而彼此電連接。在一些實施例中，第二晶粒103與互連結構105電連接。在一些實施例中，第二晶粒103藉由通路103h而與第四導電部件105b電連接。 在一些實施例中，介電質通孔110安置於模製物104內且延伸於模製物104內。在一些實施例中，介電質通孔110係模製物通孔(TMV)。在一些實施例中，介電質通孔110延伸穿過模製物104。在一些實施例中，介電質通孔110延伸於第三介電層103f之間或延伸於第三介電層103f與基板介電層101b之間。在一些實施例中，介電質通孔110與互連結構105或基板101電連接。在一些實施例中，介電質通孔110與第四導電部件105b或基板導電部件101c電連接。在一些實施例中，介電質通孔110垂直地延伸穿過模製物104。在一些實施例中，介電質通孔110包括導電材料，例如銅、銀、金、鋁等等。 在本揭示中，亦揭示一種製作半導體結構(100、200、300)之方法。在一些實施例中，半導體結構(100、200、300)係藉由方法400而形成。方法400包括數個操作，且不應將描述及說明認為係對操作順序之限制。圖4係製作半導體結構(100、200、300)之方法400的實施例。方法400包括數個操作(401、402、403、404、405、406及407)。 在操作401中，如圖5A所展示而提供或收納基板101。在一些實施例中，基板101係載體、晶圓、中介層等等。在一些實施例中，基板101係矽晶圓或矽中介層。在一些實施例中，基板101包括第一表面101a-1及與第一表面101a-1相對之第二表面101a-2。 在一些實施例中，基板介電層101b安置於基板101上方或上。在一些實施例中，基板介電層101b安置於基板101之第一表面101a-1上方或上。在一些實施例中，基板介電層101b包括介電材料，例如氧化矽、氮化矽、無摻雜矽玻璃等等。在一些實施例中，基板介電層101b包括聚合材料，例如聚醯亞胺(PI)、聚苯并噁唑(PBO)等等。在一些實施例中，基板介電層101b係藉由旋塗、化學氣相沈積(CVD)、電漿增強CVD (PECVD)、高密度電漿CVD (HDPCVD)或任何其他合適操作而安置。 在一些實施例中，基板導電部件101c形成於基板101上方或上且由基板介電層101b環繞。在一些實施例中，基板導電部件101c至少部分地自基板介電層101b曝露。在一些實施例中，基板導電部件101c包括導電材料，例如金、銀、銅、鎳、鎢、鋁、錫及/或其合金。在一些實施例中，藉由移除基板介電層101b之一部分以形成開口且接著將導電材料安置至開口中而形成基板導電部件101c。在一些實施例中，基板介電層101b之部分的移除包括微影、蝕刻或任何其他合適操作。在一些實施例中，導電材料之安置包括濺鍍、電鍍或任何其他合適操作。在一些實施例中，基板101、基板介電層101b及基板導電部件101c具有與上文所描述或圖1至圖3中之任何者所說明之組態類似的組態。 在操作402中，提供或收納第一晶粒102，且將第一晶粒102安置於基板101上方或上，如圖5B及圖5C所展示。在一些實施例中，第一晶粒102被置放且與基板101接合。在一些實施例中，第一晶粒102係自半導電晶圓單粒化。在一些實施例中，第一晶粒102包含適合於特定應用之多種電氣電路。在一些實施例中，電氣電路包括各種裝置，例如電晶體、電容器、電阻器、二極體等等。 在一些實施例中，第一晶粒102包括第一晶粒基板102a、安置於第一晶粒基板102a與基板101之間的第一介電層102b，及由第一介電層102b環繞之第一導電部件102c。在一些實施例中，第一晶粒基板102a包括半導電材料，例如矽或其他合適材料。在一些實施例中，第一晶粒基板102a係矽基板。在一些實施例中，第一晶粒基板102a包括第三表面102a-1、與第三表面102a-1相對之第四表面102a-2，及基本上正交於第三表面102a-1及第四表面102a-2之側壁102a-3。 在一些實施例中，第一介電層102b安置於第一晶粒基板102a與基板101之間。在一些實施例中，第一介電層102b包括介電材料，例如氧化矽、氮化矽、無摻雜矽玻璃等等。在一些實施例中，第一介電層102b包括聚合材料，例如聚醯亞胺(PI)、聚苯并噁唑(PBO)等等。在一些實施例中，第一介電層102b係藉由旋塗、化學氣相沈積(CVD)、電漿增強CVD (PECVD)、高密度電漿CVD (HDPCVD)或任何其他合適操作而安置。 在一些實施例中，第一介電層102b與基板介電層101b接合以在基板介電層101b與第一介電層102b之間形成第一界面102d。在一些實施例中，第一介電層102b及基板介電層101b係藉由混合式接合或任何其他合適操作而接合。 在一些實施例中，第一導電部件102c形成於第一介電層102b上方或由第一介電層102b環繞。在一些實施例中，第一導電部件102c至少部分地自第一介電層102b曝露。在一些實施例中，第一導電部件102c包括導電材料，例如金、銀、銅、鎳、鎢、鋁、錫及/或其合金。在一些實施例中，藉由移除第一介電層102b之一部分以形成開口且接著將導電材料安置至開口中而形成第一導電部件102c。在一些實施例中，第一介電層102b之部分的移除包括微影、蝕刻或任何其他合適操作。在一些實施例中，導電材料之安置包括濺鍍、電鍍或任何其他合適操作。 在一些實施例中，第一導電部件102c與基板導電部件101c電連接及接合。在一些實施例中，第一導電部件102c與基板導電部件101c接合以在基板導電部件101c與第一導電部件102c之間形成第二界面102e。在一些實施例中，基板導電部件101c及第一導電部件102c係藉由混合式接合或任何其他合適操作而接合。 在一些實施例中，第一晶粒102、第一晶粒基板102a、第一介電層102b及第一導電部件102c具有與上文所描述或圖1至圖3中之任何者所說明之組態類似的組態。 在一些實施例中，如圖5C所展示，第一導電部件102c與基板導電部件101c係藉由第二導電凸塊108而接合。在一些實施例中，第二導電凸塊108藉由落球、焊膏黏合、模板印刷或任何其他合適操作而安置於第一導電部件102c與基板導電部件101c之間。在一些實施例中，第二導電凸塊108包括導電材料，例如包括焊料、銅、鎳、金等等。在一些實施例中，第二導電凸塊108係微凸塊、支柱等等。在一些實施例中，底膠材料109經安置為環繞第二導電凸塊108。在一些實施例中，底膠材料109係藉由流動、注射或任何其他合適操作而安置。 在操作403中，如圖5D所展示而提供或收納第二晶粒103。在一些實施例中，第二晶粒103係自半導電晶圓單粒化。在一些實施例中，第二晶粒103包含適合於特定應用之多種電氣電路。在一些實施例中，電氣電路包括各種裝置，例如電晶體、電容器、電阻器、二極體等等。 在一些實施例中，第二晶粒103包括第二晶粒基板103a、安置於第二晶粒基板103a之下的第二介電層103b，及由第二介電層103b環繞之第二導電部件103c。在一些實施例中，第二晶粒基板103a包括半導電材料，例如矽或其他合適材料。在一些實施例中，第二晶粒基板103a係矽基板。在一些實施例中，第二晶粒基板103a包括第五表面103a-1、與第五表面103a-1相對之第六表面103a-2，及基本上正交於第五表面103a-1及第六表面103a-2之側壁103a-3。 在一些實施例中，第二介電層103b安置於第五表面103a-1上方或上。在一些實施例中，第二介電層103b包括介電材料，例如氧化矽、氮化矽、無摻雜矽玻璃等等。在一些實施例中，第二介電層103b包括聚合材料，例如聚醯亞胺(PI)、聚苯并噁唑(PBO)等等。在一些實施例中，第二介電層103b係藉由旋塗、化學氣相沈積(CVD)、電漿增強CVD (PECVD)、高密度電漿CVD (HDPCVD)或任何其他合適操作而安置。 在一些實施例中，第二導電部件103c形成於第二介電層103b上方或由第二介電層103b環繞。在一些實施例中，第二導電部件103c至少部分地自第二介電層103b曝露。在一些實施例中，第二導電部件103c包括導電材料，例如金、銀、銅、鎳、鎢、鋁、錫及/或其合金。在一些實施例中，藉由移除第二介電層103b之一部分以形成開口且接著將導電材料安置至開口中而形成第二導電部件103c。在一些實施例中，第二介電層103b之部分的移除包括微影、蝕刻或任何其他合適操作。在一些實施例中，導電材料之安置包括濺鍍、電鍍或任何其他合適操作。 在一些實施例中，第二晶粒103包括安置於第二晶粒基板103a上之第三介電層103f，及由第三介電層103f環繞之第三導電部件103g。在一些實施例中，第三介電層103f安置於第二晶粒103之第六表面103a-2上方或上。在一些實施例中，第三介電層103f包括介電材料，例如氧化矽、氮化矽、無摻雜矽玻璃等等。在一些實施例中，第三介電層103f包括聚合材料，例如聚醯亞胺(PI)、聚苯并噁唑(PBO)等等。在一些實施例中，第二介電層103b係藉由旋塗、化學氣相沈積(CVD)、電漿增強CVD (PECVD)、高密度電漿CVD (HDPCVD)或任何其他合適操作而安置。 在一些實施例中，第三導電部件103g形成於第三介電層103f上方或由第三介電層103f環繞。在一些實施例中，第三導電部件103g至少部分地自第三介電層103f曝露。在一些實施例中，第三導電部件103g包括導電材料，例如金、銀、銅、鎳、鎢、鋁、錫及/或其合金。在一些實施例中，藉由移除第三介電層103f之一部分以形成開口且接著將導電材料安置至開口中而形成第三導電部件103g。在一些實施例中，第三介電層103f之部分的移除包括微影、蝕刻或任何其他合適操作。在一些實施例中，導電材料之安置包括濺鍍、電鍍或任何其他合適操作。 在一些實施例中，通路103h形成於第二晶粒103內。在一些實施例中，通路103h延伸穿過第二晶粒基板103a。在一些實施例中，通路103h延伸於第二介電層103b與第三介電層103f之間。在一些實施例中，通路103h與第二導電部件103c及第三導電部件103g電連接且延伸於第二導電部件103c與第三導電部件103g之間。在一些實施例中，通路103h包括導電材料，例如銅、銀、金、鋁等等。在一些實施例中，通路103h係基板通孔或矽通孔(TSV)。在一些實施例中，藉由移除第二晶粒103之一部分以形成延伸於第二晶粒103內之凹槽且將導電材料安置至凹槽中而形成通路103h。在一些實施例中，藉由移除第二晶粒基板103a、第二介電層103b或第三介電層103f之一部分以形成凹槽且將導電材料安置至凹槽中而形成通路103h。在一些實施例中，第二晶粒103之部分的移除包括微影、蝕刻或任何其他合適操作。在一些實施例中，導電材料之安置包括濺鍍、電鍍或任何其他合適操作。 在操作404中，將第二晶粒103安置於基板101上方或上，如圖5E及圖5F所展示。在一些實施例中，第二晶粒103與基板101接合。在一些實施例中，第二介電層103b與基板介電層101b接合以在基板介電層101b與第二介電層103b之間形成第三界面103d。在一些實施例中，第二介電層103b及基板介電層101b係藉由混合式接合或任何其他合適操作而接合。 在一些實施例中，第二導電部件103c與基板導電部件101c電連接及接合。在一些實施例中，第二導電部件103c與基板導電部件101c接合以在基板導電部件101c與第二導電部件103c之間形成第四界面103e。在一些實施例中，基板導電部件101c及第二導電部件103c係藉由混合式接合或任何其他合適操作而接合。 在一些實施例中，第二晶粒103、第二晶粒基板103a、第二介電層103b、第二導電部件103c、第三介電層103f及第三導電部件103g具有與上文所描述或圖1至圖3中之任何者所說明之組態類似的組態。 在一些實施例中，如圖5F所展示，第二導電部件103c與基板導電部件101c係藉由第二導電凸塊108而接合。在一些實施例中，第二導電凸塊108藉由落球、焊膏黏合、模板印刷或任何其他合適操作而安置於第二導電部件103c與基板導電部件101c之間。在一些實施例中，第二導電凸塊108包括導電材料，例如包括焊料、銅、鎳、金等等。在一些實施例中，第二導電凸塊108係微凸塊、支柱等等。在一些實施例中，底膠材料109經安置為環繞第二導電凸塊108。在一些實施例中，底膠材料109係藉由流動、注射或任何其他合適操作而安置。 在操作405中，如圖5G及圖5H所展示而形成模製物104。在一些實施例中，模製物104形成於基板101上方且圍繞第一晶粒102及第二晶粒103。在一些實施例中，藉由如圖5G所展示而將模製材料安置於基板101上方以覆蓋第一晶粒102及第二晶粒103且接著如圖5H所展示而移除模製材料之一部分以曝露第二晶粒103之至少一部分而形成模製物104。在一些實施例中，模製材料係藉由轉移成型、注塑成型、包覆成型或任何其他合適操作而安置。在一些實施例中，模製材料之部分係藉由研磨、蝕刻或任何其他合適操作而移除。在一些實施例中，模製物104接觸第一晶粒102之第四表面102a-2及側壁102a-3。在一些實施例中，模製物104接觸第二晶粒103之側壁103a-3。在一些實施例中，第一晶粒102完全地由模製物104覆蓋。在一些實施例中，第二晶粒103至少部分地自模製物104曝露。在一些實施例中，第三介電層103f至少部分地自模製物104曝露。在一些實施例中，模製物104安置於第一晶粒102a上方。在一些實施例中，模製物104包括各種材料，例如氧化物，模製物具有與上文所描述或圖1至圖3中之任何者所說明之組態類似的組態。 在操作406中，如圖5I所展示而形成互連結構105。在一些實施例中，互連結構105形成於模製物104、第一晶粒102a及第二晶粒103a上方。在一些實施例中，藉由將第四介電層105a安置於模製物104及第二晶粒103上方且形成由第四介電層105a環繞之第四導電部件105b而形成互連結構105。在一些實施例中，第四導電部件105b形成於第四介電層105a上方或內。 在一些實施例中，第四介電層105a包括介電材料，例如氧化矽、氮化矽、無摻雜矽玻璃等等。在一些實施例中，第四介電層105a包括聚合材料，例如聚醯亞胺(PI)、聚苯并噁唑(PBO)等等。在一些實施例中，第四介電層105a係藉由旋塗、化學氣相沈積(CVD)、電漿增強CVD (PECVD)、高密度電漿CVD (HDPCVD)或任何其他合適操作而安置。 在一些實施例中，第四導電部件105b形成於第四介電層105a上方或由第四介電層105a環繞。在一些實施例中，第四導電部件105b至少部分地自第四介電層105a曝露。在一些實施例中，第四導電部件105b包括導電材料，例如金、銀、銅、鎳、鎢、鋁、錫及/或其合金。在一些實施例中，藉由移除第四介電層105a之一部分以形成開口且接著將導電材料安置至開口中而形成第四導電部件105b。在一些實施例中，第四介電層105a之部分的移除包括微影、蝕刻或任何其他合適操作。在一些實施例中，導電材料之安置包括濺鍍、電鍍或任何其他合適操作。在一些實施例中，互連結構105、第四介電層105a及第四導電部件105b具有與上文所描述或圖1至圖3中之任何者所說明之組態類似的組態。 在一些實施例中，凸塊墊106形成於互連結構105上方或上。在一些實施例中，凸塊墊106形成於第四介電層105a上方或由第四介電層105a環繞。在一些實施例中，凸塊墊106形成於第四導電部件105b上方且與第四導電部件105b電連接。在一些實施例中，凸塊墊106係藉由蒸鍍、濺鍍、電鍍或任何其他合適操作而形成。在一些實施例中，凸塊墊106具有與上文所描述或圖1至圖3中之任何者所說明之組態類似的組態。 在操作407中，將第一導電凸塊107安置於互連結構105上方，如圖5J所展示。在一些實施例中，第一導電凸塊107安置於第四導電部件105b上方且與第四導電部件105b電連接。在一些實施例中，第一導電凸塊107與凸塊墊106接合。在一些實施例中，導電凸塊107係藉由落球、焊膏黏合、模板印刷或任何其他合適操作而安置。在一些實施例中，導電凸塊107係焊接點、焊料凸塊、焊球、球柵陣列(BGA)球、可控塌陷晶片連接(C4)凸塊等等。在一些實施例中，導電凸塊107係導電支柱或柱。在一些實施例中，導電凸塊107具有與上文所描述或圖1至圖3中之任何者所說明之組態類似的組態。在一些實施例中，形成如圖1所展示之半導體結構100。 在本揭示中，揭示一種半導體結構。該半導體結構包括：基板；第一晶粒，其安置於該基板上；第二晶粒，其安置於該基板上；若干通路，其延伸於該第二晶粒內；模製物，其環繞該第一晶粒及該第二晶粒；互連結構，其安置於該模製物、該第一晶粒及該第二晶粒上方；及導電凸塊，其安置於該互連結構上方。該基板及該第一晶粒藉由該第二晶粒中之該等通路而與該互連結構及該導電凸塊電連接。可減小半導體結構之整體尺寸，可增加I/O端子之數目，且可增強半導體結構之電氣效能。 在一些實施例中，一種半導體結構包括：基板；第一晶粒，其安置於該基板上方；第二晶粒，其安置於該基板上方；模製物，其安置於該基板上方且環繞該第一晶粒及該第二晶粒；互連結構，其包括介電層及導電部件，其中該介電層安置於該第一晶粒、該第二晶粒及該模製物上方，且該等導電部件由該介電層環繞；及通路，其延伸於該第二晶粒內且延伸於該介電層與該基板之間。 在一些實施例中，該基板藉由該等通路而與該等導電部件電連接。在一些實施例中，該第一晶粒之厚度與該第二晶粒之厚度基本上不同或相同。在一些實施例中，該模製物安置於該第一晶粒與該介電層之間。在一些實施例中，該第二晶粒係功能或虛設晶粒。在一些實施例中，該第一晶粒藉由該基板及該等通路而與該等導電部件電連接。在一些實施例中，該半導體結構進一步包括導電凸塊，其安置於該介電層上方且與該等導電部件電連接。 在一些實施例中，一種半導體結構包括：基板；第一晶粒，其安置於該基板上方且包括第一晶粒基板、安置於該第一晶粒基板與該基板之間的第一介電層，及由該第一介電層環繞之第一導電部件；第二晶粒，其安置於該基板上方且包括第二晶粒基板、安置於該第二晶粒基板與該基板之間的第二介電層、由該第二介電層環繞之第二導電部件、安置於該第二晶粒基板上方的第三介電層，及由該第三介電層環繞之第三導電部件；模製物，其安置於該基板上方且環繞該第一晶粒及該第二晶粒；及複數個通路，其延伸於該第二介電層與該第三介電層之間穿過該第二晶粒基板。 在一些實施例中，該複數個通路垂直地延伸於該第二晶粒內。在一些實施例中，該複數個通路安置於該第二導電部件與該第三導電部件之間。在一些實施例中，該第二導電部件與該第三導電部件藉由該複數個通路中之至少一者而電連接。在一些實施例中，該複數個通路中之兩者之間的距離基本上小於或等於10 um。在一些實施例中，該第三介電層自該模製物曝露。在一些實施例中，基板介電層安置於該基板上方，基板導電部件由該基板介電層環繞，且該基板介電層安置於該基板與該第一介電之間且安置於該基板與該第二介電層之間。在一些實施例中，該半導體結構進一步包括：導電凸塊，其安置於該第一導電部件與該基板導電部件之間或安置於該第二導電部件與該基板導電部件之間；底膠材料，其環繞該導電凸塊、該第一介電層之一部分或該第二介電層之一部分。在一些實施例中，該半導體結構進一步包括：第一界面，其安置於該基板介電層與該第一介電層之間或安置於該基板介電層與該第二介電層之間；及第二界面，其安置於該基板導電部件與該第一導電部件之間或安置於該基板導電部件與該第二導電部件之間。在一些實施例中，該基板導電部件藉由該複數個通路中之至少一者及該第二導電部件而與該第三導電部件電連接。 在一些實施例中，一種製作半導體結構之方法包括：提供基板；將第一晶粒安置於該基板上方；提供第二晶粒，該第二晶粒包括延伸於該第二晶粒內之通路；將該第二晶粒安置於該基板上方；圍繞該第一晶粒及該第二晶粒形成模製物；及形成包括介電層及導電部件之互連結構，其中該介電層安置於該模製物、該第一晶粒及該第二晶粒上方，且該等導電部件由該介電層環繞，其中藉由移除該第二晶粒之一部分以形成延伸於該第二晶粒內之凹槽且將導電材料安置至該凹槽中而形成該等通路。 在一些實施例中，該第二晶粒之該部分的該移除包括蝕刻操作，且該導電材料之該安置包括電鍍或濺鍍操作。在一些實施例中，該第一晶粒完全地由該模製物覆蓋，且該第二晶粒至少部分地自該模製物曝露。 前述內容概述若干實施例之特徵使得熟習此項技術者可更佳理解本揭示之態樣。熟習此項技術者應瞭解，他們可容易地使用本揭示作為設計或修改用於實施本文中所介紹之實施例之相同目的及/或實現本文中所介紹之實施例之相同優點之其他過程及結構的基礎。熟習此項技術者亦應意識到，此類等效構造不脫離本揭示之精神及範疇，且其可在不脫離本揭示之精神及範疇的情況下在本文中做出各種變化、替代及更改。
100‧‧‧半導體結構
101‧‧‧基板
101a-1‧‧‧第一表面
101a-2‧‧‧第二表面
101b‧‧‧基板介電層
101c‧‧‧基板導電部件
101c-1‧‧‧基板連接盤部分
101c-2‧‧‧基板通路部分
102‧‧‧第一晶粒
102a‧‧‧第一晶粒基板
102a-1‧‧‧第三表面
102a-2‧‧‧第四表面
102a-3‧‧‧側壁
102b‧‧‧第一介電層
102c‧‧‧第一導電部件
102c-1‧‧‧第一連接盤部分
102c-2‧‧‧第一通路部分
102d‧‧‧第一界面
102e‧‧‧第二界面
103‧‧‧第二晶粒
103a‧‧‧第二晶粒基板
103a-1‧‧‧第五表面
103a-2‧‧‧第六表面
103a-3‧‧‧側壁
103b‧‧‧第二介電層
103c‧‧‧第二導電部件
103c-1‧‧‧第二連接盤部分
103c-2‧‧‧第二通路部分
103d‧‧‧第三界面
103e‧‧‧第四界面
103f‧‧‧第三介電層
103g‧‧‧第三導電部件
103h‧‧‧通路
104‧‧‧模製物
105‧‧‧互連結構
105a‧‧‧第四介電層
105b‧‧‧第四導電部件
105b-1‧‧‧第四連接盤部分
105b-2‧‧‧第四通路部分
106‧‧‧凸塊墊
107‧‧‧第一導電凸塊
108‧‧‧第二導電凸塊
109‧‧‧底膠材料
110‧‧‧介電質通孔
200‧‧‧半導體結構
300‧‧‧半導體結構
400‧‧‧方法
401‧‧‧操作
402‧‧‧操作
403‧‧‧操作
404‧‧‧操作
405‧‧‧操作
406‧‧‧操作
407‧‧‧操作
D‧‧‧距離
當結合附圖閱讀時，自以下詳細描述更佳理解本揭示之態樣。要強調的是，根據工業中之標準實踐，各種特徵件未按比例繪製。事實上，出於清楚論述，可任意增大或減小各種特徵件之尺寸。 圖1係根據本發明之一些實施例之半導體結構的示意橫截面圖。 圖2係根據本發明之一些實施例之半導體結構的示意橫截面圖。 圖3係根據本發明之一些實施例之半導體結構的示意橫截面圖。 圖4係根據本發明之一些實施例之製作半導體結構之方法的流程圖。 圖5A至圖5J係根據本發明之一些實施例的藉由圖4之方法製作半導體結構的示意圖。

Claims (1)

  1. 一種半導體結構，其包含： 基板； 第一晶粒，其安置於該基板上方； 第二晶粒，其安置於該基板上方； 模製物，其安置於該基板上方且環繞該第一晶粒及該第二晶粒； 互連結構，其包括介電層及導電部件，其中該介電層安置於該第一晶粒、該第二晶粒及該模製物上方，且該等導電部件由該介電層環繞；及 通路，其延伸於該第二晶粒內且延伸於該介電層與該基板之間。
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