TW201913407A - ARM-based server and management method thereof - Google Patents

Abstract

An ARM-based server and a management method thereof. The ARM-based server includes at least one peripheral device, a baseboard management controller (BMC), and an ARM processor including an ARM trusted firmware (ATF). The BMC is configured to monitor and determine whether the at least one peripheral device and the ARM processor is abnormal, and to generate event information according to a determination result, where the event information corresponds to the ARM processor or one of the peripheral device. The ATF is configured to receive the event information from the BMC, and to perform an event handling operation on the ARM processor or the peripheral device corresponding to the event information. In addition, a management method of an ARM-based server is also provided.

Description

ARM architecture server and management method thereof

The present invention relates to a server management method, and in particular to an ARM architecture server capable of automatically removing obstacles and a management method thereof.

The Baseboard Management Controller (BMC) is used to manage the server system. In general, in order to monitor whether the internal operation of the computer system is normal, the user can use the substrate management controller disposed on the motherboard to detect the computer system. Common methods include remotely controlling the baseboard management controller to detect the readings of the various sensors in the computer system that sense the operation of the various components (eg, fan speed or processor temperature, etc.). When the user finds that the sensor reading is abnormal, the server must be repaired in person (for example, replacement of parts, etc.). However, too long a reaction time may cause more serious damage and loss of data after an abnormality occurs in the server. Therefore, in order to maintain the normal operation of the server and good service, too long reaction time after the sensor reading abnormality is not allowed.

The present invention provides an ARM architecture server and a management method thereof, which can automatically perform repair when the BMC detects an abnormality of a component, thereby enabling the server to operate normally without interruption.

The present invention provides an ARM architecture server including at least one peripheral device, a substrate management controller, and an ARM processor. The substrate management controller is coupled to the at least one peripheral device for monitoring and determining whether the at least one peripheral device and the ARM processor are abnormal, and generating an event message corresponding to the ARM processor or one of the peripheral devices according to the determination result. The ARM processor is coupled to the at least one peripheral device and the baseboard management controller, including an ARM Trusted Firmware (ATF). The ARM trusted firmware is used to receive event messages from the baseboard management controller and to perform event processing operations on the ARM processor or peripheral devices corresponding to the event messages.

From another point of view, the present invention proposes a management method of an ARM architecture server. The ARM architecture server includes at least one peripheral device, a substrate management controller, and an ARM processor. The management method includes: the substrate management controller monitors and determines whether the at least one peripheral device and the ARM processor are abnormal; and the substrate management controller generates an event message corresponding to the ARM processor or one of the peripheral devices according to the determination result; The management controller transmits the event message to the ARM processor; and performs an event processing operation on the ARM processor or peripheral device corresponding to the event message by using the ARM trusted firmware in the ARM processor.

In an embodiment of the invention, the event message corresponds to an ARM processor, and the event processing operation includes adjusting an operating frequency of the ARM processor.

In an embodiment of the invention, the peripheral device includes a memory device having at least two memory channels, wherein the event message corresponds to one of the memory channels, and the event processing operation includes closing the memory corresponding to the event message. Body channel.

In an embodiment of the invention, the peripheral device comprises a PCI-E device, the event message corresponds to a PCI-E device, and the event processing operation comprises performing a PCI-E reset.

In an embodiment of the invention, the ARM architecture server includes a plurality of exception levels, wherein the operating system of the ARM architecture server runs at the first exception level, and the ARM trusted firmware runs at no less than the first exception. The second exception level of the hierarchy.

Based on the foregoing, the ARM architecture server and the management method thereof are provided in the embodiment of the present invention, and the substrate management controller notifies the ARM trusted firmware of the abnormal event, and directly processes the device that generates the abnormality by using the ARM trusted firmware. . In this way, the user can repair the ARM server in time without installing the monitoring program in the operating system, and at the same time, the security can be considered at the same time.

The above described features and advantages of the invention will be apparent from the following description.

FIG. 1 is a schematic block diagram of an ARM architecture server according to an embodiment of the invention. The ARM architecture server 100 of the embodiment of the present invention includes a substrate management controller 110, at least one peripheral device 120, and an ARM processor 130. The substrate management controller 110 and the ARM processor 130 are coupled to each. Peripheral device 120. In particular, the substrate management controller 110 is also coupled to the ARM processor.

In an embodiment, the ARM architecture server 100 is, for example but not limited to, an ARMv8-A architecture that includes multiple Exception levels, while a higher exception level indicates a higher privilege. For example, the ARM architecture server 100 includes four exception levels of EL0 to EL3, where EL0 is unprivileged, EL1 is OS kernel mode, and EL2 is virtual machine monitor level (Hypervisor) mode), and EL3 is TrustZone ^® monitoring level (TrustZone ^® monitor mode).

The baseboard management controller 110 is connected to each peripheral device 120 via, for example, an Intelligent Platform Management Bus (IPMB) to monitor each peripheral device 120. In an embodiment, the peripheral device 120 includes a sensor for monitoring fan speed or processor temperature, and a dual-channel dual data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory). , DDR SDRAM), and components such as a PCI-E Ethernet card, but the present invention is not limited thereto. Regarding the description of the substrate management controller 110 and its monitoring server peripheral devices 120, those skilled in the art will be able to obtain sufficient teachings from the prior art, and thus will not be described herein.

The ARM processor 130 is a processor designed in a Reduced Instruction Set Computing (RISC) architecture, such as an ARM Cortex-A, an ARM Cortex-M, a Cortex-A50 series, or a Cortex A-73 processor, but The invention is not limited to this.

In one embodiment, the ARM processor 130 includes an ARM Trusted Firmware (ATF) 131 for providing ATF services. It is worth mentioning that the ARM Trusted Firmware 131 is running at an exception level that is not lower than the operating system. For example, the operating system of the ARM server 100 is, for example, running at a first exception level (eg, EL1), while the ARM trustworthy firmware 131 is running at a second exception level that is not lower than the first exception level (eg, , EL3). Thus, the ARM Trusted Firmware 131 can access all of the ARM processor 130 itself and the plug-in or non-plug-in peripherals 120 of various interfaces (eg, SATA, PCI-E, LAN, GPIO, SPI, or I2C interfaces). Regarding the ARM Trusted Firmware 131 and the ATF services that it can provide, those skilled in the art can obtain sufficient teachings from the prior art related to the ARM architecture, and details are not described herein.

In particular, when the substrate management controller 110 detects that the ARM processor 130 itself or the peripheral component 120 is abnormal, the ARM processor 130 is notified of the abnormal condition. Since the ARM trusted firmware 131 in the ARM processor 130 is running at an exception level not lower than the operating system, the ARM Trusted Firmware 131 can directly process or repair an abnormality in the ARM server 100.

2 is a flow chart of a method for managing an ARM architecture server according to an embodiment of the present invention. The management method in the embodiment of FIG. 2 is applicable to the ARM architecture server 100 of FIG. 1, and the detailed steps of the method of the embodiment of FIG. 2 will be described below with reference to the components of the ARM architecture server 100 of FIG.

Referring to FIG. 2, in step S210, the substrate management controller 110 monitors and determines whether at least one peripheral device 120 and the ARM processor 130 have an abnormality.

For example, the substrate management controller 110 can monitor, for example, a temperature sensor in the ARM processor 130 to determine whether the ARM processor 130 is overheated; the substrate management controller 110 can monitor, for example, the memory device in the ARM server 100 to determine Whether it is in normal operation; or the baseboard management controller 110 can, for example, monitor whether the PCI-E device on the PCI-E bus of the ARM server 100 is operating normally, etc., but not limited thereto. Those skilled in the art can obtain sufficient teachings from the substrate management controller and the related knowledge to set the abnormal state of each component and complete the above operation for judging whether each component has an abnormality, and therefore no longer A narrative.

If the substrate management controller 110 does not find an abnormality, the process proceeds to step S210. On the other hand, if the substrate management controller 110 determines that the ARM processor 130 has an abnormality in one of the peripheral devices 120, the process proceeds to step S220, and the substrate management controller 110 generates an event message according to the determination result, and then, in step S230, Passed to the ARM processor 130.

In detail, the event information generated by the substrate management controller 110 according to the determination result is the ARM processor 130 or the peripheral component 120 corresponding to the occurrence of the abnormality. For example, when the baseboard management controller 110 determines that the ARM processor 130 is overheated, an event message indicating that the ARM processor 130 is overheated is generated; when the baseboard management controller 110 determines that the memory device is not functioning properly (for example, the error bit of the data) When there are too many elements and the error correction code mechanism cannot be corrected, an event message or the like indicating that the memory device cannot operate normally is generated, but the present invention is not limited thereto.

In step S240, the ARM trustworthy firmware 131 in the ARM processor 130 receives the event message from the baseboard management controller 110, and performs an event processing operation on the ARM processor 130 or the peripheral device 120 corresponding to the event message. The ARM architecture server 100 is not interrupted.

In one embodiment, the ARM processor 130 is coupled to the peripheral device 120 (eg, a temperature sensor) and the event message corresponds to the ARM processor 130, for example, to indicate that the ARM processor 130 has overheated. After the ARM trusted firmware 131 receives this event message, it performs an event processing operation on the ARM processor 130. For example, the ARM trustworthy firmware 131 may, for example, reduce the operating frequency of the ARM processor 130 or adjust the level of the CPU temperature regulator in the ARM processor 130 to achieve a cooling effect. In this way, although the ARM processor 130 is abnormal (overheated), it can still be processed in time by the ARM trusted firmware to avoid more serious damage and cause the ARM architecture server 100 to stop running and stop the service.

In an embodiment, the ARM architecture server 100 includes a peripheral device 120 (eg, dual channel double data rate synchronous dynamic random access memory), and the event message corresponds to dual channel double data rate synchronous dynamic random access. One of the memory channels of the memory, for example, indicates that the memory of the memory channel is not functioning properly. After the ARM trusted firmware 131 receives the event message, an event processing operation is performed on the memory channel 130 corresponding to the event message. For example, the ARM trustworthy firmware 131, for example, closes the memory channel corresponding to the event message, while the memory that retains another memory channel can function normally. As a result, the ARM architecture server 100 can continue to operate without interrupting the service.

In an embodiment, the ARM architecture server 100 includes a peripheral device 120 (eg, a PCI-E device), and the event message corresponds to one of the PCI-E devices or terminals (eg, a PCI-E Ethernet card). For example, it indicates that the PCI-E device is not functioning properly. After the ARM trusted firmware 131 receives this event message, it performs an event processing operation on the PCI-E device. For example, the ARM Trusted Firmware 131, for example, performs a PCI-E reset operation to attempt to repair a PCI-E device. In this way, the PCI-E reset operation can be performed without restarting the ARM architecture server 100 to repair the PCI-E device to resume normal operation. A person skilled in the art can obtain sufficient teachings from the related art of PCI-E reset to complete the PCI-E reset operation described in this embodiment, and thus is not described herein.

In summary, the ARM architecture server and the management method thereof according to the embodiments of the present invention use the ATF firmware in the ARM processor to directly process or repair an abnormal component in the ARM architecture server, thereby avoiding the servo. The device caused serious damage and loss of data. On the other hand, the user does not need to install an additional monitoring program in the operating system, which eliminates the risk of the hidden program in the monitoring program causing the outflow of confidential data, and also improves the security of the server service.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ARM architecture server

110‧‧‧Baseboard Management Controller

120‧‧‧At least one peripheral device

130‧‧‧ARM processor

131‧‧‧ARM Trustworthy Firmware

Steps for managing the S210~S240‧‧‧ARM architecture server

FIG. 1 is a schematic block diagram of an ARM architecture server according to an embodiment of the invention. 2 is a flow chart of a method for managing an ARM architecture server according to an embodiment of the present invention.

Claims (10)

An ARM architecture server, comprising: at least one peripheral device; a substrate management controller coupled to the at least one peripheral device; and an ARM processor coupled to the at least one peripheral device and the substrate management controller, wherein The ARM processor includes an ARM trusted firmware, wherein the baseboard management controller is configured to monitor and determine whether the at least one peripheral device and the ARM processor are abnormal, and generate an event message according to a determination result, wherein the ARM may The trusted firmware is configured to receive the event message from the baseboard management controller, wherein the event message corresponds to one of the ARM processor or the at least one peripheral device, wherein the ARM trustworthy firmware is further used to The ARM processor or the peripheral device corresponding to the event message performs an event processing operation. The ARM architecture server of claim 1, wherein the event message corresponds to the ARM processor, wherein the event processing operation comprises adjusting an operating frequency of the ARM processor. The ARM architecture server of claim 1, wherein the at least one peripheral device comprises a memory device, the memory device comprising at least two memory channels, wherein the event message corresponds to the memory channels One of the event processing operations includes closing the memory channel corresponding to the event message. The ARM architecture server of claim 1, wherein the at least one peripheral device comprises a PCI-E device, wherein the event message corresponds to the PCI-E device, and the event processing operation comprises performing a PCI- E reset. The ARM architecture server of claim 1, wherein the ARM architecture server includes a plurality of exception levels, wherein an operating system of the ARM architecture server runs at a first exception level, and the ARM is trustworthy. The firmware runs at a second exception level that is not lower than the first exception level. An ARM architecture server management method, wherein the ARM architecture server includes at least one peripheral device, a substrate management controller, and an ARM processor, the management method includes: the substrate management controller monitors and determines the at least one peripheral device And the ARM management controller generates an event message according to a determination result, wherein the event message corresponds to one of the ARM processor or the at least one peripheral device; the baseboard management controller transmits The event message is sent to the ARM processor; and an ARM processing operation is performed on the ARM processor or the peripheral device corresponding to the event message by an ARM trusted firmware in the ARM processor. The management method of claim 6, wherein the event message corresponds to the ARM processor, wherein the event processing operation comprises: adjusting an operating frequency of the ARM processor. The management method of claim 6, wherein the at least one peripheral device comprises a memory device, the memory device includes at least two memory channels, and the event message corresponds to the memory channels. For example, the event processing operation includes: closing the memory channel corresponding to the event message. The management method of claim 6, wherein the at least one peripheral device comprises a PCI-E device, wherein the event message corresponds to the PCI-E device, and the event processing operation comprises: performing a PCI-E Reset. The management method of claim 6, wherein the ARM architecture server includes a plurality of exception levels, wherein an operating system of the ARM architecture server runs at a first exception level, and the ARM trusted firmware Running at a second exception level that is not lower than the first exception level.