JP5689783B2 - Computer, computer system, and failure information management method - Google Patents

Description

  Embodiments described herein relate generally to a computer, a computer system, and a failure information management method for reliably recording a hardware failure that has occurred in a computer.

  A system management controller for managing a failure occurring in a computer is provided on a motherboard. When a failure occurs, the system management controller stores failure information indicating the content of the failure in the nonvolatile memory. Later, the administrator can easily identify the cause of the failure by analyzing the failure information.

JP 2011-48534 A Japanese Patent Laid-Open No. 10-247911 JP 2009-252006 A

  If the management controller fails or the nonvolatile memory fails, failure information cannot be recorded in the nonvolatile memory, and failure information cannot be managed. Therefore, even when failure information cannot be managed, it is desired to manage failure information for failure in order to analyze a failure that occurred later.

  An object of the present invention is to provide a computer, a computer system, and a failure information management method capable of managing failure information even when the system management controller cannot manage the failure information. is there.

  According to the embodiment, the computer is a computer system including a first computer connected to a network and a management computer, wherein the first computer includes a first storage unit and the first computer. First issue means for issuing a first interrupt notification when a hardware failure occurs, collecting the content of the hardware failure in response to the issue of the first interrupt notification, and collecting the collected content Generating means for generating first failure information based on the first issue information, second issue means for issuing a second interrupt instruction when the first failure information is generated, and issuing the second interrupt instruction A system management controller that acquires the first failure information and records the first failure information in the first storage unit, and the system management controller. And a notification means for notifying the management computer of the first failure information when the first failure information cannot be recorded in the first storage unit. Two storage units, and system management means for writing the first failure information into the second storage unit when the first failure information is notified.

The block diagram which shows an example of a structure of the computer system of embodiment. The block diagram which shows an example of a structure of the server computer of embodiment. The block diagram which shows an example of a structure of the SMI handler shown in FIG. The block diagram which shows an example of a structure of the server computer of embodiment. The block diagram which shows an example of a structure of the management server computer of embodiment. The flowchart which shows the procedure of the process performed by a SMI handler. The flowchart which shows the procedure of the process performed by the BMC proxy program.

  Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 is a block diagram illustrating a configuration of a computer system according to an embodiment.
As shown in FIG. 1, the computer system includes a management server computer 10, a first server computer 20A, a second server computer 20B, and the like connected to a LAN (Local Area Network).

The configuration of the server computer 20 (first server computer 20A, second server computer 20B) will be described with reference to FIG.
The server computer 20 includes a first NIC (Network Interface Card) 21, a second NIC 22, a network controller 23, a BMC (Baseboard Management Controller) 24 as a system management controller, and a non-volatile memory (NVRAM) 25. And a flash ROM 26 and the like.

  The network controller 23 has a function corresponding to the data link layer of the OSI reference model. The first NIC 21 and the second NIC 22 are, for example, OSI reference model physical layer chips. The second NIC 22 is provided in a BMC 24 described later. Note that the first NIC 21 is used by an application program executed by the server computer 20.

  The BMC 24 constantly monitors hardware using a sensor provided in the server computer 20. When a hardware failure occurs, the content of the failure that has occurred is written to a SEL (System Event Log) 251 in the NVRAM 25. In addition, the BMC 24 notifies the administrator terminal 30 set in advance of the content of the failure that has occurred. The BMC 24 notifies the administrator of the content of the failure that has occurred, for example, by sending an e-mail to the e-mail address of the administrator. Further, the BMC 24 notifies the administrator terminal 30 set in advance of the content of the failure that has occurred by sending a message including the content of the failure that has occurred using SNMP (Simple Network Management Protocol).

  The BMC 24 is a special microcontroller that is arranged on a motherboard of a computer (server) and is based on an IPMI (Intelligent Platform Management Interface) architecture. Even if the CPU (OS) is not operating, the BMC 24 operates as long as there is a power source. Different types of sensors built into the computer (not shown) report parameters related to temperature, cooling fan rotation speed, power supply state, OS state, etc. to the BMC 24. The BMC 24 monitors the sensor, and when any parameter falls outside the allowable range, the BMC 24 notifies the administrator terminal 30 of the possibility of system malfunction via the network.

  In the NVMRAM 25, a system event log (SEL) 251, a sensor data record (SDR) 252, and a platform event filtering (PEF) 253 are written. The NVRAM 25 is a serial bus connection type EEPROM (Electrically Erasable and Programmable Read Only Memory) or flash memory. For example, when an abnormality of the information processing apparatus is detected by the BMC 24 or when an error exceeding a threshold is detected by the sensor, the content of the failure is recorded in the SEL 251. In the SDR 252, the type of sensor (temperature, voltage, etc.) managed by the BMC 24, a threshold value for identifying an abnormality, and the like are recorded at the time of manufacture. In the PEF 253, the setting of the type of failure to be notified to the administrator terminal 30 when a failure occurs is recorded.

  A BIOS (Basic Input / Output System) 261 is stored in the flash ROM 26. The BIOS 261 is a system program for hardware control executed by the CPU. The BIOS 261 has an SMI handler 262 that is executed by the CPU when an SMI (System Management Interrupt) event is issued.

  As shown in FIG. 3, the SMI handler 262 has programs such as a failure information generation module 2621, a failure information storage instruction module 2622, and a failure information transmission module 2623.

  The failure information generation module 2621 generates failure information based on the content of the hardware failure when a hardware failure occurs in the server computer. When the failure information is generated, the instruction issue module 2622 transmits an instruction signal for instructing the BMC 24 to store the failure information in the NVRAM 25. The failure information transmission module 2623 transmits the failure information to the management server computer 10 in order to manage the failure information by the management server computer 10 when the failure information has failed to be stored in the NVRAM 25.

A more detailed system configuration of the server computer 20 will be described with reference to FIG.
As shown in FIG. 3, the computer 20 includes a CPU 101, a north bridge 102, a main memory 103, a south bridge 104, a graphics processing unit (GPU) 105, a video memory (VRAM) 105A, a sound controller 106, and a flash ROM 26. , Network controller 23, BMC 24, NVRAM 25, hard disk drive (HDD) 111, PCI device 115, and the like.

  The CPU 101 is a processor that controls the operation of the computer 10. The CPU 101 executes an operating system and various application programs loaded from the hard disk drive (HDD) 111 to the main memory 103. The CPU 101 also executes a basic input output system (BIOS) 261 stored in the flash ROM 109. The BIOS 261 is a program for hardware control.

  The north bridge 102 is a bridge device that connects the local bus of the CPU 101 and the south bridge 104. The north bridge 102 also includes a memory controller that controls access to the main memory 103. The north bridge 102 also has a function of executing communication with the GPU 105 via a PCI EXPRESS standard serial bus or the like.

  The GPU 105 is a display controller that controls the display monitor of the computer 10. The GPU 105 uses the VRAM 105A as a work memory. The video signal generated by the GPU 105 is sent to the display monitor.

  The south bridge 104 controls each device 115A and 115B on each LPC (Low Pin Count) bus and each PCI (Peripheral Component Interconnect) bus. The south bridge 104 includes an IDE (Integrated Drive Electronics) controller for controlling the hard disk drive (HDD) 111 and the DVD drive 112. Further, the south bridge 104 has a function of executing communication with the sound controller 106.

  Further, the south bridge 104 as the first issuing means is a circuit that issues an SMI (System Management Interrupts) event to the CPU upon detection of a PERR (parity error) signal or SERR (system error) signal on the PCI bus 14. Built in.

  The sound controller 106 is a sound source device and outputs audio data to be reproduced to the speakers 18A and 18B.

  The sensor 241 monitors the issuance of a system error signal (SERR signal) / parity error signal (PERR signal) issued from the south bridge 104, the temperature of the CPU, and the like. The sensor 241 is polled by the BMC 24 at predetermined intervals.

  Next, the configuration of the software program executed by the CPU of the management server computer 10 will be described with reference to FIG. In the management server computer 10, the BMC proxy program 501 is executed. In the BMC proxy program 501, the BMC manager 502, the first virtual BMC 503A, and the second virtual BMC 503B are executed. The management server computer 10 also has a storage device 510.

  The first virtual BMC 503A executes the function of the BMC in the first server computer 20A. The second virtual BMC 503B executes the function of the BMC in the second server computer 20B. The management manager 501 sends it to the virtual BMC corresponding to the server that sent the failure information.

  During normal operation, the BMC manager 502 polls and obtains configuration information (such as a trap transmission destination) of the SDR 252, PEF 253, and BMC dedicated LAN port from the BMC 24 via the second NIC 22 of each server computer.

The BMC manager 502 records the acquired SDR and PEF in a folder (511A or 511B) in the storage device 510 associated with the virtual BMC corresponding to the acquired server computer. Further, the BMC manager 502 sets the configuration information of the BMC dedicated LAN port in the corresponding virtual BMC.
The BMC manager 502 registers the management server computer 10 in the SMI handler 262 as the transmission destination of the SMI event when the BMC fails.

  An operation when a hardware failure occurs in the server computer and the failure information is normally written in the NVRAM will be described.

  The sensor 241 detects the SERR signal / PERR signal issued by the PCI device on the PCI bus 114. When the sensor 241 detects the SERR signal / PERR signal, the sensor 241 instructs the south bridge 104 to output the SMI signal to the CPU 101. The south bridge 104 outputs an SMI signal to the CPU 101 in accordance with an instruction from the sensor 241. The SMI handler 262 is activated in response to the SMI signal.

  In response to the SMI signal, the fault information generation module 2621 in the activated SMI handler 262 detects information indicating which device on the PCI bus 114 has output the SERR signal / PERR signal.

  Based on the detected information, the failure information generation module 2621 generates first failure information including the type of error (SERR signal / PERR signal), the bus number, function number, and device number of the device that issued and detected the error. Generate.

  When the first failure information is generated, the failure information storage instruction module 2622 transmits an instruction signal for instructing the BMC 24 to store the first failure information in the NVRAM 25.

  The BMC 24 acquires first failure information from the SMI handler 262 in response to receiving the instruction signal. Then, second failure information in which additional information such as an event serial number, sensor type, and time is added to the first failure information as an error event is recorded in the SEL 251.

  The BMC 24 transmits a trap to the administrator terminal 30 set in advance from the second NIC 22 when the failure that has occurred in the PEF 253 is set.

  The above is the operation when a failure occurs in the hardware of the server computer while the BMC and NVRAM are not broken down.

  The operation of the SMI handler when an SMI event is issued in a state where the BMC or NVRAM is faulty will be described with reference to the flowchart of FIG.

  The sensor 241 detects the SERR signal / PERR signal issued by the PCI device on the PCI bus 114. When the sensor 241 detects the SERR signal / PERR signal, the sensor 241 instructs the south bridge 104 to output the SMI signal to the CPU 101. The south bridge 104 outputs an SMI signal to the CPU 101 in accordance with an instruction from the sensor 241. In response to the SMI signal (step B601), the SMI handler 262 is activated.

  In response to the SMI signal, the fault information generation module 2621 in the activated SMI handler 262 detects which device on the PCI bus 114 has output the SERR signal / PERR signal (step B602).

  The failure information generation module 2621 generates first failure information including the type of error (SERR signal / PERR signal), the bus number of the device that issued / detected the error, the function number, and the device number based on the collected information. Generate (step B603).

  When the first failure information is generated, the failure information storage instruction module 2622 issues an SMI event for instructing the BMC 24 to record the first failure information (step B604).

  If the NVRAM 25 has failed, the BMC issues an error notification indicating that the first failure information could not be recorded in the SEL 251 to the SMI handler. In addition, when the BMC is faulty, the SMI handler displays the fault information in the SEL when there is no response from the BMC until a predetermined time elapses after the SMI handler instructs to record the first fault information. Is not written (step B605).

  When failure information is not written in the SEL 251, the failure information transmission module 2623 of the SMI handler 262 sends the first failure information to the application program of the management server computer 10 via the normal LAN port (NIC 1). A message including the message is transmitted (step B606). In the message, transmission source information indicating the server that sent the message is stored.

  Next, the operation of the BMC proxy program 501 that has received the message will be described with reference to the flowchart of FIG.

  The BMC manager 502 receives a message including the first failure information transmitted from the first server computer 20A (step B701).

  The BMC manager extracts the first failure information and the transmission source information from the message, and sends the first failure information to the first virtual BMC based on the transmission source information included in the message (step B702).

  The first virtual BMC writes the third failure information including the first failure information to the SEL 251A in the folder 511A associated with the first virtual BMC 503A corresponding to the first server computer (step B703). .

  The first virtual BMC 503A determines whether the failure that has occurred in the first server computer 20A is set in the PEF (step B704). If it is determined that a failure has been set (Yes in step B704), a trap is transmitted to the fourth failure information including at least a part of the information included in the first failure information (step B705). ). If it is determined that the failure has not been set (No in step B704), the process ends. Also, when the trap is transmitted (step B705), the process is terminated.

  According to this embodiment, even if the BMC or NVRAM fails and the content of the failure that has occurred in the server computer cannot be recorded in the NVRAM, the content of the failure in the storage device in the management server computer 10 Can be written. Therefore, it is effective for analysis when a failure occurs. In addition, the trap can be transmitted to the administrator terminal 30.

  In the above embodiment, the sensor instructs the South Bridge to issue an SMI event. However, when the value detected by the sensor exceeds a threshold, the BMC instructs the South Bridge to issue an SMI event. You may comprise. In this case, the failure information generation module 2621 acquires the content of the hardware failure from the BMC 24.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Management server computer, 20A ... 1st server computer, 20B ... 2nd server computer, 21 ... 1st NIC, 22 ... 2nd NIC, 23 ... Network controller, 24 ... BMC (system management controller) , 25... Nonvolatile memory (first storage unit), 101... CPU, 104. 115B ... PCI device, 116 ... Keyboard controller IC, 262 ... SMI handler, 501 ... BMC proxy program, 502 ... BMC manager, 503A ... First virtual BMC, 503B ... Second virtual BMC, 510 ... Storage device (second Storage section).

Claims (7)

A computer connected to a management computer via a network,
A storage unit;
Generating means for generating failure information indicating the content of the hardware failure when a hardware failure occurs in the computer;
Issuing means for issuing a first instruction signal when the failure information is generated;
A system management controller that stores the failure information in the storage unit in response to reception of the first instruction signal from the issuing means;
A computer comprising: transmission means for transmitting the failure information to the management computer when storage of the failure information in the storage unit fails. The system management controller
2. The computer according to claim 1, wherein when the failure information includes information indicating a failure designated by notification setting, at least a part of the failure information is transmitted to an administrator terminal based on transmission destination information. A computer system comprising a first computer connected to a network and a management computer connected to the network,
The first computer is
A first storage unit;
Generating means for generating fault information indicating the contents of the hardware fault when a hardware fault occurs in the first computer;
Issuing means for issuing a first instruction signal when the failure information is generated;
A system management controller that stores the failure information in the first storage unit in response to reception of the first instruction signal from the issuing means;
Transmission means for transmitting the failure information to the management computer when storage of the failure information in the first storage unit fails,
The management computer is:
A second storage unit;
A computer system comprising system management means for storing the failure information in the second storage unit. The system management controller
The computer system according to claim 3 , wherein when the failure information includes information indicating a failure specified by notification setting, at least a part of the failure information is transmitted to an administrator terminal based on transmission destination information. The management computer further comprises acquisition means for acquiring the notification setting and the transmission destination information,
When the failure information includes information indicating a failure specified by the acquired notification setting, the system management unit sends at least a part of the failure information to the administrator terminal based on the acquired transmission destination information. The computer system according to claim 4 for transmitting. The computer system further comprises a second computer connected to the network,
The second computer is
A third storage unit;
Generating means for generating second fault information indicating a content of the hardware fault when a hardware fault occurs in the second computer;
First issuing means for issuing a second instruction signal when the second failure information is generated;
A second system management controller that stores the second failure information in the third storage unit in response to reception of the second instruction signal from the first issuing means;
Transmission means for transmitting the second failure information to the management computer when storage of the second failure information in the third storage unit fails,
The computer system according to claim 3 , wherein the management computer stores the second failure information in the second storage unit. A failure information management method by a computer system including a first computer connected to a network and a management computer connected to the network,
The first computer generates failure information indicating a content of the hardware failure when a hardware failure occurs in the first computer;
The first computer issues a first instruction signal when the failure information is generated;
A system management controller provided in the first computer stores the failure information in a first storage unit provided in the first computer in response to receiving the first instruction signal;
When storing the failure information in the first storage unit fails, the system management controller sends the failure information to the management computer,
A failure information management method in which the management computer stores the failure information in a second storage unit provided in the management computer.

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