TW201907564A - Vertical power transistor with improved conductivity and high reverse bias performance - Google Patents
Vertical power transistor with improved conductivity and high reverse bias performance Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 239000000463 material Substances 0.000 claims abstract description 41
- 239000002800 charge carrier Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 56
- 238000000034 method Methods 0.000 description 10
- 239000002184 metal Substances 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- General Physics & Mathematics (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
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Abstract
Description
本發明係關於一種具有溝槽結構之垂直功率電晶體，其中二極體接面及/或異質接面兩者形成於溝槽與至少一個磊晶層之間。 The invention relates to a vertical power transistor with a trench structure, in which both a diode junction and / or a heterojunction are formed between the trench and at least one epitaxial layer.
就垂直功率電晶體而言，在反向偏壓操作中以及在短路之情況下，當在汲極與源極之間存在高正電壓時，自高場強度屏蔽閘極氧化物皆存在問題。此外，難以限制短路電流。 With regard to vertical power transistors, shielding gate oxide from high field strength is problematic when there is a high positive voltage between the drain and the source during reverse bias operation and under short circuit conditions. In addition, it is difficult to limit the short-circuit current.
自現有技術已知屏蔽閘極氧化物之各種可能性。一種可能性為將p型摻雜區域插入或掩埋於功率電晶體之溝槽結構下方的磊晶層中。此等p型摻雜區域電性連接至功率電晶體之源極區域。藉由其在MOS頂部下方之位置，其使MOS頂部保持自高場強度經屏蔽且決定性地促進限制短路電流。 Various possibilities for shielding gate oxides are known from the prior art. One possibility is to insert or bury p-type doped regions in the epitaxial layer below the trench structure of the power transistor. These p-type doped regions are electrically connected to the source region of the power transistor. With its position below the top of the MOS, it keeps the top of the MOS shielded from high field strength and decisively promotes the limitation of short-circuit current.
此處的不足之處為需要額外磊晶步驟以產生經掩埋p型區域。此造成高成本及其他過程風險。 The disadvantage here is that additional epitaxial steps are required to produce buried p-type regions. This causes high costs and other process risks.
另一可能性為藉由植入至MOS頂部之側來產生深度延伸p+區域。在此種情況下，此等區域之植入比MOS頂部之植入更深，且因此MOS頂部自高場強度經屏蔽。 Another possibility is to create deep extended p + regions by implanting to the side of the top of the MOS. In this case, the implantation of these areas is deeper than that of the top of the MOS, and therefore the top of the MOS is shielded from the high field strength.
此處的不足之處為必須消耗較大能量以用於深度植入，且因此 導致高成本。 The disadvantage here is that a large amount of energy must be consumed for deep implantation, and therefore leads to high costs.
本發明之目標為改善垂直功率電晶體之效能。 The goal of the present invention is to improve the performance of vertical power transistors.
垂直功率電晶體具有至少一個磊晶層，該磊晶層包含摻雜有第一電荷載子之第一半導體材料及複數個溝槽。溝槽自磊晶層之表面延伸至磊晶層之內部中。換言之，溝槽基部經配置於磊晶層中或由磊晶層包封。根據本發明，每一溝槽具有自溝槽基部延伸達至某一高度之區域。該區域至少部分地經摻雜有第二電荷載子之第二半導體材料填充。該區域電性連接至源極區域。第一電荷載子不同於第二電荷載子。 The vertical power transistor has at least one epitaxial layer including a first semiconductor material doped with a first charge carrier and a plurality of trenches. The trench extends from the surface of the epitaxial layer into the interior of the epitaxial layer. In other words, the trench base is configured in or enclosed by the epitaxial layer. According to the invention, each trench has an area extending from the trench base to a certain height. This region is at least partially filled with a second semiconductor material doped with second charge carriers. This region is electrically connected to the source region. The first charge carrier is different from the second charge carrier.
此處的優勢為直接p/n接面或n/p接面在每一溝槽與磊晶層之間產生，且因此在反向偏壓的情況下MOS頂部自高場強度經屏蔽。 The advantage here is that a direct p / n junction or n / p junction is created between each trench and the epitaxial layer, and therefore the top of the MOS is shielded from high field strength under reverse bias.
在開發中，第一半導體材料與第二半導體材料不同。特別是，相較於第二半導體材料，第一半導體材料具有較大帶隙。 In development, the first semiconductor material is different from the second semiconductor material. In particular, the first semiconductor material has a larger band gap than the second semiconductor material.
此處有利的為，除p/n接面或n/p接面以外，異質接面形成，從而在電晶體之反向操作中降低傳導損耗，此係因為其降低積體續流二極體之順向電壓。術語反向操作理解為意指電晶體之操作模式為續流二極體，亦即電晶體之電流相對於電流之正常方向反向。換言之，反向傳導性增大。另外，異質接面可直接配置於MOS頂部下方，而無另一磊晶層。因此，可用相對較少之生產努力產生對MOS頂部之良好屏蔽。 It is advantageous here that in addition to p / n junctions or n / p junctions, heterojunctions are formed, thereby reducing conduction losses in the reverse operation of the transistor, because it reduces integrated freewheeling diodes The forward voltage. The term reverse operation is understood to mean that the mode of operation of the transistor is a freewheeling diode, that is, the current of the transistor is reversed relative to the normal direction of the current. In other words, the reverse conductivity increases. In addition, the heterojunction can be directly arranged under the top of the MOS without another epitaxial layer. Therefore, relatively little production effort can be used to produce good shielding of the top of the MOS.
在進一步改進中，在區域之溝槽表面與磊晶層之間配置有包含摻雜有第二電荷載子之第三半導體材料的層，該溝槽表面包含各別溝槽之溝槽基部及側壁。換言之，該層形成位於溝槽表面與磊晶層之間的一種井。 In a further improvement, a layer including a third semiconductor material doped with second charge carriers is disposed between the trench surface of the region and the epitaxial layer, the trench surface includes the trench base of each trench and Sidewall. In other words, this layer forms a kind of well between the trench surface and the epitaxial layer.
此處的優勢為p/n接面定位於第三半導體材料與第一半導體材料 之間，且因此電晶體可暴露於高場強度。因此，可向電晶體施加較高反向偏壓電壓或可使用相同反向偏壓電壓達成較佳傳導性，此係因為該接面定位於具有較高帶隙或較高臨界場強度之材料中。 The advantage here is that the p / n junction is positioned between the third semiconductor material and the first semiconductor material, and therefore the transistor can be exposed to high field strength. Therefore, a higher reverse bias voltage can be applied to the transistor or the same reverse bias voltage can be used to achieve better conductivity because the junction is located on a material with a higher band gap or higher critical field strength in.
在開發中，相較於在各別溝槽之側壁與磊晶層之間，該層在各別溝槽之溝槽基部下方具有較大厚度。 In development, this layer has a larger thickness below the trench base of each trench than between the sidewalls of each trench and the epitaxial layer.
此處有利的為，MOS頂部可以甚至更大程度經屏蔽。 It is advantageous here that the top of the MOS can be shielded even more.
在進一步改進中，區域之高度包含各別溝槽之深度的百分之十至百分之九十。 In a further improvement, the height of the area includes 10% to 90% of the depth of each trench.
在開發中，第一電荷載子為n型傳導且第二電荷載子為p型傳導。 In development, the first charge carrier is n-type conduction and the second charge carrier is p-type conduction.
此處有利的為，由於較大電子遷移率，垂直功率電晶體具有較低傳導損耗。 The advantage here is that the vertical power transistor has a lower conduction loss due to the larger electron mobility.
在進一步改進中，第一半導體材料包含SiC且第二半導體材料包含多晶矽。 In a further improvement, the first semiconductor material includes SiC and the second semiconductor material includes polysilicon.
在開發中，第三半導體材料包含SiC。 In development, the third semiconductor material contains SiC.
在進一步改進中，磊晶層經配置於包含SiC之半導體基板上。 In a further improvement, the epitaxial layer is configured on a semiconductor substrate including SiC.
在開發中，垂直功率電晶體為MOSFET。 In development, the vertical power transistor is a MOSFET.
此處的優勢為低傳導損耗在恆定反向偏壓電阻的情況下發生，例如與諸如IGBT之雙極解決方案相比。 The advantage here is that low conduction losses occur with constant reverse bias resistance, for example compared to bipolar solutions such as IGBTs.
其他優勢自例示性具體實例之以下描述及自從屬專利申請專利範圍而顯現。 Other advantages emerge from the following description of illustrative specific examples and the scope of patent applications from dependent patents.
100‧‧‧垂直功率電晶體 100‧‧‧Vertical power transistor
101‧‧‧半導體基板 101‧‧‧Semiconductor substrate
103‧‧‧磊晶層 103‧‧‧Epitaxial layer
104‧‧‧通道層 104‧‧‧channel layer
105‧‧‧源極區域 105‧‧‧Source area
106‧‧‧區域 106‧‧‧Region
107‧‧‧溝槽 107‧‧‧Groove
108‧‧‧區域 108‧‧‧Region
109‧‧‧第二半導體材料 109‧‧‧Second semiconductor material
110‧‧‧閘極介電質 110‧‧‧Gate dielectric
111‧‧‧閘極電極 111‧‧‧Gate electrode
112‧‧‧結構化絕緣層 112‧‧‧Structured insulating layer
113‧‧‧金屬層 113‧‧‧Metal layer
114‧‧‧汲極金屬化物 114‧‧‧ Drain metallization
200‧‧‧垂直功率電晶體 200‧‧‧Vertical power transistor
201‧‧‧半導體基板 201‧‧‧Semiconductor substrate
203‧‧‧磊晶層 203‧‧‧Epitaxial layer
204‧‧‧通道層 204‧‧‧channel layer
205‧‧‧源極區域 205‧‧‧Source area
206‧‧‧區域 206‧‧‧Region
207‧‧‧溝槽 207‧‧‧groove
208‧‧‧區域 208‧‧‧Region
209‧‧‧第二半導體材料 209‧‧‧Second semiconductor material
210‧‧‧閘極介電質 210‧‧‧ Gate dielectric
211‧‧‧閘極電極 211‧‧‧Gate electrode
212‧‧‧結構化絕緣層 212‧‧‧Structured insulating layer
213‧‧‧金屬層 213‧‧‧Metal layer
214‧‧‧汲極金屬化物 214‧‧‧ Drain metal
215‧‧‧層 215‧‧‧ storey
300‧‧‧方法 300‧‧‧Method
310‧‧‧步驟 310‧‧‧Step
320‧‧‧步驟 320‧‧‧Step
330‧‧‧步驟 330‧‧‧Step
340‧‧‧步驟 340‧‧‧Step
350‧‧‧步驟 350‧‧‧Step
360‧‧‧步驟 360‧‧‧Step
362‧‧‧步驟 362‧‧‧Step
370‧‧‧步驟 370‧‧‧Step
380‧‧‧步驟 380‧‧‧Step
400‧‧‧替代方法 400‧‧‧Alternative method
410‧‧‧步驟 410‧‧‧Step
420‧‧‧步驟 420‧‧‧Step
430‧‧‧步驟 430‧‧‧Step
440‧‧‧步驟 440‧‧‧ steps
452‧‧‧步驟 452‧‧‧Step
454‧‧‧步驟 454‧‧‧Step
456‧‧‧步驟 456‧‧‧Step
458‧‧‧步驟 458‧‧‧Step
470‧‧‧步驟 470‧‧‧Step
480‧‧‧步驟 480‧‧‧Step
本發明基於較佳具體實例及隨附圖式在下文加以解釋。在圖式 中：圖1展示垂直功率電晶體之一實施例。圖2展示垂直功率電晶體之另一實施例，圖3展示一種用於產生根據圖2之垂直功率電晶體的方法，以及圖4展示一種用於產生根據圖2之垂直功率電晶體的替代方法。 The present invention is explained below based on preferred specific examples and accompanying drawings. In the drawings: Figure 1 shows an embodiment of a vertical power transistor. 2 shows another embodiment of a vertical power transistor, FIG. 3 shows a method for generating the vertical power transistor according to FIG. 2, and FIG. 4 shows an alternative method for generating the vertical power transistor according to FIG. .
圖1展示垂直功率電晶體100之一實施例。垂直功率電晶體100包含半導體基板101，在該半導體基板之前側上沈積或配置有至少一個磊晶層103。磊晶層103包含摻雜有第一電荷載子之第一半導體材料。磊晶層103較佳地包含n型摻雜SiC。在磊晶層103之上部區域中，植入p型摻雜離子，例如Al。因此，在磊晶層103之上部區域中，此處形成充當通道區域之通道層104。可替代地，在磊晶層103上可配置有形成通道區域之p型摻雜磊晶層。在通道層104上配置有包含n+摻雜之源極區域105及p+摻雜之區域106的另一半導體層。垂直功率電晶體100具有溝槽結構，亦即複數個或大量溝槽。每一溝槽107具有自溝槽基部延伸達至溝槽之某一高度的區域108。此區域108完全經第二半導體材料109填充。第二半導體材料109以導電方式連接至至少一個源極區域105。在溝槽結構內之第一區域108上方配置有閘極介電質110及閘極電極111。在每一溝槽107上(亦即在溝槽結構上方)配置有使閘極電極111與源極區域105電絕緣之結構化絕緣層112。在結構化絕緣層112上配置有金屬層113。在半導體基板101之背側上配置有汲極金屬化物114。 FIG. 1 shows an embodiment of a vertical power transistor 100. The vertical power transistor 100 includes a semiconductor substrate 101 on which at least one epitaxial layer 103 is deposited or arranged on the front side. The epitaxial layer 103 includes a first semiconductor material doped with first charge carriers. The epitaxial layer 103 preferably includes n-type doped SiC. In the upper region of the epitaxial layer 103, p-type doped ions, such as Al, are implanted. Therefore, in the upper region of the epitaxial layer 103, a channel layer 104 serving as a channel region is formed here. Alternatively, a p-type doped epitaxial layer forming a channel region may be disposed on the epitaxial layer 103. On the channel layer 104, another semiconductor layer including an n + doped source region 105 and a p + doped region 106 is disposed. The vertical power transistor 100 has a trench structure, that is, a plurality or a plurality of trenches. Each trench 107 has a region 108 extending from the trench base to a certain height of the trench. This region 108 is completely filled with the second semiconductor material 109. The second semiconductor material 109 is electrically connected to at least one source region 105. A gate dielectric 110 and a gate electrode 111 are arranged above the first region 108 in the trench structure. A structured insulating layer 112 that electrically insulates the gate electrode 111 and the source region 105 is disposed on each trench 107 (that is, above the trench structure). A metal layer 113 is arranged on the structured insulating layer 112. A drain metallization 114 is arranged on the back side of the semiconductor substrate 101.
溝槽結構具有為例如0.5μm至10μm深之溝槽。不考慮產生公差，溝槽107在此情況下具有相同深度。溝槽107之間的距離實質上為相同大小且處於0.1μm與10μm之間的範圍內，下限由過程規定且上限由MOS錯合物之 其他方面的不充分屏蔽規定。側向位於區域108之間的區域或區域108之間的水平區域(亦即磊晶層103之部分)可具有不同於磊晶層103之其餘部分的摻雜。因此，區域108之間的傳導性可增大，且因此電流較快速地流動。 The trench structure has a trench that is, for example, 0.5 μm to 10 μm deep. Irrespective of the resulting tolerance, the groove 107 has the same depth in this case. The distance between the trenches 107 is substantially the same size and is in the range between 0.1 m and 10 m, the lower limit is specified by the process and the upper limit is specified by insufficient shielding of the MOS complex in other aspects. The regions laterally located between the regions 108 or the horizontal regions between the regions 108 (ie, the portion of the epitaxial layer 103) may have a different doping than the rest of the epitaxial layer 103. Therefore, the conductivity between the regions 108 can be increased, and thus the current flows more quickly.
視情況，另一磊晶層可經配置於至少一個磊晶層103與MOS頂部或MOS錯合物之間。 According to circumstances, another epitaxial layer may be configured between at least one epitaxial layer 103 and the top of the MOS or the MOS complex.
第一半導體材料與第二半導體材料不同。 The first semiconductor material is different from the second semiconductor material.
在一例示性具體實例中，半導體基板101及磊晶層103包含SiC。第二半導體材料包含多晶矽(polycrystalline silicon)，下文中亦稱作多晶矽(poly silicon)或多晶Si。閘極介電質110包含SiO2且閘極電極111包含多晶矽。 In an exemplary embodiment, the semiconductor substrate 101 and the epitaxial layer 103 include SiC. The second semiconductor material includes polycrystalline silicon (polycrystalline silicon), hereinafter also referred to as polycrystalline silicon (poly silicon) or polycrystalline Si. The gate dielectric 110 includes SiO 2 and the gate electrode 111 includes polysilicon.
在另一例示性具體實例中，半導體基板101及磊晶層103包含GaN。 In another illustrative specific example, the semiconductor substrate 101 and the epitaxial layer 103 include GaN.
圖2展示垂直功率電晶體200之另一實施例。垂直功率電晶體200包含垂直功率電晶體100之結構，附圖標號之相同最末數字與圖1中之相同組件相對應。另外，垂直功率電晶體200具有配置於區域208之溝槽表面與磊晶層203之間的層215。層215包含摻雜有第二電荷載子之第三半導體材料。特別是，第三半導體材料為p型摻雜，例如藉由離子植入。有效摻雜劑量通常超過1E13cm^-3。高效摻雜劑量具有改善對MOS頂部之屏蔽的效應。第三半導體材料包含例如SiC。層215之厚度處於0.01μm與4μm之間的範圍內。 FIG. 2 shows another embodiment of the vertical power transistor 200. The vertical power transistor 200 includes the structure of the vertical power transistor 100, and the same reference numerals and the last numbers correspond to the same components in FIG. In addition, the vertical power transistor 200 has a layer 215 disposed between the trench surface of the region 208 and the epitaxial layer 203. Layer 215 contains a third semiconductor material doped with second charge carriers. In particular, the third semiconductor material is p-type doped, for example by ion implantation. The effective doping dose usually exceeds 1E13cm ^ -3. The high doping dose has the effect of improving the shielding on the top of the MOS. The third semiconductor material includes, for example, SiC. The thickness of the layer 215 is in the range between 0.01 μm and 4 μm.
垂直功率電晶體100及200較佳地為MOSFET。然而，其亦可經設計或實施為FIEMT。垂直功率電晶體100及200可用於例如車輛逆變器、光伏打逆變器、牽引驅動器或高壓整流器中。 The vertical power transistors 100 and 200 are preferably MOSFETs. However, it can also be designed or implemented as FIEMT. The vertical power transistors 100 and 200 may be used in, for example, vehicle inverters, photovoltaic inverters, traction drives, or high-voltage rectifiers.
圖3描述一種用於產生根據圖2之垂直功率電晶體之方法300。方法300開始於步驟310，其中至少一個磊晶層經沈積於半導體基板上。磊晶層具有第一電荷載子。在後繼步驟320中，產生垂直功率電晶體之功能層，此係因 為源極區域、p型通道區域及p+區域憑藉各種罩幕及植入產生。在後繼步驟330中，溝槽結構藉助於乾式蝕刻產生。在後繼步驟340中，藉由高溫或犧牲性氧化來執行溝槽側壁之後續處理(例如圓化)以改善表面。在後續步驟350中，藉助於溝槽表面與磊晶層之間的離子植入來產生層，該溝槽表面包含各別溝槽之溝槽基部及側壁部分。各別溝槽之溝槽基部及側壁部分為例如高度p型摻雜。在後續步驟360中，每一溝槽經第二半導體材料填充達至某一高度。第二半導體材料包含例如p型摻雜多晶矽。在後續步驟370中，絕緣層經配置於各別溝槽之經填充區域上，以便使第二半導體材料與MOS頂部絕緣。在後續步驟380中，產生根據現有技術之MOS頂部、結構化絕緣層、金屬層及背側金屬化物。 FIG. 3 depicts a method 300 for generating the vertical power transistor according to FIG. 2. Method 300 begins at step 310, where at least one epitaxial layer is deposited on a semiconductor substrate. The epitaxial layer has a first charge carrier. In the subsequent step 320, a functional layer of vertical power transistors is generated because the source region, p-channel region and p + region are generated by various masks and implants. In the subsequent step 330, the trench structure is produced by means of dry etching. In the subsequent step 340, subsequent processing (eg, rounding) of the trench sidewalls is performed by high temperature or sacrificial oxidation to improve the surface. In a subsequent step 350, a layer is created by means of ion implantation between the trench surface and the epitaxial layer, the trench surface including the trench base and sidewall portions of the respective trenches. The trench base and sidewall portions of the respective trenches are, for example, highly p-type doped. In the subsequent step 360, each trench is filled to a certain height with the second semiconductor material. The second semiconductor material includes, for example, p-type doped polysilicon. In a subsequent step 370, the insulating layer is configured on the filled areas of the respective trenches to insulate the second semiconductor material from the top of the MOS. In a subsequent step 380, the top of the MOS, structured insulating layer, metal layer and backside metallization according to the prior art are generated.
圖4描述一種用於產生根據圖2之垂直功率電晶體的替代方法400。步驟410至430以及步驟470及480與來自圖3之步驟310至330以及步驟370及380相對應。在步驟430之後的步驟440中，藉助於溝槽表面與磊晶層之間的離子植入來產生層，該溝槽表面包含各別溝槽之溝槽基部及整個側壁。在後續步驟452中，每一溝槽用蝕刻罩幕或硬式罩幕(例如SiO2)填充達至某一高度。在後續步驟454中，藉助於乾式蝕刻過程以移除在剩餘未經填充之溝槽之側壁上於步驟440中所產生的層之方式擴寬每一溝槽。在後續步驟456中，硬式罩幕經移除。在後續步驟458中，藉由高溫或犧牲性氧化來執行溝槽側壁之後續處理(例如圓化)以改善表面。在後續步驟362中，溝槽用第二半導體材料填充達至某一高度，例如藉助於沈積方法與乾式蝕刻步驟相組合。第二半導體材料為例如多晶Si。 FIG. 4 depicts an alternative method 400 for generating vertical power transistors according to FIG. 2. Steps 410 to 430 and steps 470 and 480 correspond to steps 310 to 330 and steps 370 and 380 from FIG. 3. In step 440 after step 430, a layer is created by means of ion implantation between the trench surface and the epitaxial layer, the trench surface including the trench base of the respective trench and the entire sidewall. In a subsequent step 452, each trench is filled up to a certain height with an etching mask or a hard mask (eg, SiO 2 ). In a subsequent step 454, each trench is widened by means of a dry etching process to remove the layer created in step 440 on the sidewalls of the remaining unfilled trenches. In a subsequent step 456, the hard mask is removed. In the subsequent step 458, subsequent processing (eg, rounding) of the trench sidewalls is performed by high temperature or sacrificial oxidation to improve the surface. In a subsequent step 362, the trench is filled with a second semiconductor material to a certain height, for example by means of a deposition method combined with a dry etching step. The second semiconductor material is, for example, polycrystalline Si.
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| DE102017207848.0A DE102017207848A1 (en) | 2017-05-10 | 2017-05-10 | Vertical power transistor with improved conductivity and high blocking behavior |
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| US8415671B2 (en) * | 2010-04-16 | 2013-04-09 | Cree, Inc. | Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices |
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