TW201905933A - Methods for reducing data error in transceiving of flash storage interface and apparatuses using the same - Google Patents

Abstract

An embodiment of a method for reducing data error in transceiving of flash storage interface, executed by a processing unit of a first side, is introduced to comprise the following steps: repeatedly monitoring a data frame and/or a control frame received from a second side; and triggering a transmission data rate setting adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects an error of received data.

Description

 Method for reducing transmission data error in flash storage interface and device using the same  

The present invention relates to a flash memory, and more particularly to a method for reducing the error of transmitted data in a flash memory interface and a device using the same.

Flash memory devices are generally classified into NOR flash devices and NAND flash devices. The NOR flash device is a random access device, and the host device can provide any address of the NOR flash device on the address pin, and is instantly stored in the data pin of the NOR flash device. The information on this address. Conversely, NAND flash devices are not random access, but sequential access. The NAND flash device cannot access any random address like the NOR flash device, and the master device needs to write the byte value of the sequence to the NAND flash device to define the request command (command). The type (eg, read, write, erase, etc.) and the address on this command. The address can point to a page (the smallest data block of a write job in flash memory) or a block (the smallest data block of an erase job in flash memory). In fact, NAND flash devices typically read or write complete pages of data from memory cells. When a full page of data is read from the array into a buffer in the device, the main unit can be bitwise or word by sequentially clocking out the content using a strobe signal. A group of words access data.

The flash memory device usually includes a device end and a storage unit, and is connected to the main control terminal by a flash storage interface. As the data transfer speed of the flash storage interface becomes faster and faster, data is more prone to errors when transmitted. Therefore, there is a need for a method and apparatus for using the method for reducing transmission data errors in a flash storage interface.

Embodiments of the present invention provide a method for reducing data errors transmitted in a flash storage interface, which is executed by a processing unit at a first end, and includes the following steps: continuously supervising data frames and/or control frames received from the second end And triggering the data transmission rate setting adjustment when the data frame and/or the control frame includes a message indicating that the bottom layer of the second end detects the received data error.

Embodiments of the present invention provide an apparatus for reducing transmission data errors in a flash storage interface, including a bottom layer and a processing unit. The bottom layer is coupled to the corresponding end, and the processing unit is coupled to the bottom layer. The processing unit continuously monitors the data frame and/or the control frame received from the corresponding end through the bottom layer; and triggers when the information frame and/or the information contained in the control frame indicates that the bottom layer of the corresponding end detects the received data error. Data transfer rate setting adjustment.

110‧‧‧ Computing device

130‧‧‧Master

131‧‧‧ physical layer

133‧‧‧Physical conversion layer

135‧‧‧data connection layer

137‧‧‧Processing unit

150‧‧‧ device side

151‧‧‧ physical layer

153‧‧‧Physical conversion layer

155‧‧‧data connection layer

157‧‧‧Processing unit

170‧‧‧Access interface

170_0~170_ j ‧‧‧Access subinterface

180‧‧‧ storage unit

180_0_0~180_ j _ i ‧‧‧Storage subunit

310_0‧‧‧Information line

320_0_0~320_0_ i ‧‧‧ Chip enable control signal

S411~S499‧‧‧ method steps

50‧‧‧Data Link Layer Frame

51‧‧‧Information frame

511‧‧‧0th Communication Category Information Frame

513‧‧‧1st communication category information frame

53‧‧‧Control frame

533‧‧‧Negative response control frame

61‧‧‧RReq bits

63‧‧‧CCITT CRC-16 check code

80‧‧‧PACP_GET_req frame

81‧‧‧MIBattribute field

1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

2 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention.

Figure 3 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention.

4A to 4B are flowcharts of a data transmission rate setting adjustment method when operating at a low speed according to an embodiment of the present invention.

Figure 5 is a classification tree of control and data frames in accordance with an embodiment of the present invention.

Figure 6 is a diagram showing the data structure of a negative response control frame in accordance with an embodiment of the present invention.

Figure 7 is a diagram showing the data structure of a data frame including an overwritten negative response control frame in accordance with an embodiment of the present invention.

Figure 8 is a diagram showing the data structure of a PACP_GET_req frame in accordance with an embodiment of the present invention.

9A to 9B are flowcharts of a data transmission rate setting adjustment method when operating at a low speed according to an embodiment of the present invention.

The following description is a preferred embodiment of the invention, which is intended to describe the basic spirit of the invention, but is not intended to limit the invention. The actual inventive content must be referenced to the scope of the following claims.

It must be understood that the terms "comprising", "comprising" and "the" are used in the <RTI ID=0.0> </RTI> <RTIgt; </ RTI> to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude Add more technical features, values, method steps, job processing, components, components, or any combination of the above.

The words "first", "second", and "third" are used in the claims to modify the elements in the claims, and are not used to indicate a priority order, an advance relationship, or a component. Prior to another component, or the chronological order in which the method steps are performed, it is only used to distinguish components with the same name.

1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention. The system architecture of the flash memory includes the device end 150 and communicates with the host 130 through a Universal Flash Storage (UFS) interface. UFS is a flash storage specification for achieving higher data transfer speeds and more reliable flash memory storage, and does not require different converters to be configured due to different types of flash memory cells. Flash memory can be used in digital cameras, mobile phones, consumer electronics, and the like. The UFS interface can operate in Pulse-Width Modulation gear (PWM) and High-Speed gear (HS). The pulse width modulation can be 1 Gbps (Gigabits per second) or lower, and the high speed can be 1.4 Gbps or higher. The pulse width modulation file can be referred to as a low speed gear. For example, Table 1 lists the data transfer rates for different high-speed files (HS-GEARs) defined by the UFS specification: For example, the high-speed HS-G1 has a Class A data transmission rate of 1248 Mbps, while the high-speed HS-G1 Class B data transmission rate is 1248 Mbps, and the high-speed file HS-G2 Class A data transmission rate is 2496 Mbps, while the high-speed file HS-G2 has a Class A data transmission rate of 2496 Mbps. G2's Class B data transfer rate is 2915.2 Mbps, and so on. Table 2 lists the data transmission rates of the different pulse width modulation files (PWM-GEARs) defined by the UFS specification: The data transmission rate of the low-speed PWM-G0 is between 0.01 and 3 Mbps, the data transmission rate of the low-speed PWM-G1 is between 3 and 9 Mbps, and the data transmission rate of the low-speed PWM-G2 is between 6 and 18 Mbps. ,So on and so forth.

The flash memory further includes a storage unit 180, and the device end 150 communicates with the storage unit 180 using the access interface 170, and can communicate with the storage unit 180 by using a double data rate (DDR) protocol, for example, open NAND. Open NAND flash interface (ONFI), double data rate switch (DDR toggle) or other interface. The processing unit 157 of the device end 150 writes the data to the specified address in the storage unit 180 through the access interface 170, and reads the data from the specified address in the storage unit 180. In detail, the processing unit 157 of the device end 150 writes the data to the specified address in the storage unit 180 through the access interface 170, and reads the data from the specified address in the storage unit 180. The access interface 170 uses a plurality of electronic signals to coordinate data and command transmission between the processing unit of the device 150 and the storage unit 180, including a data line, a clock signal, and a control signal. . The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transmit chip enable (CE), address latch enable (ALE), command extraction Control signals such as command latch enable (CLE) and write enable (WE).

The storage unit 180 can include a plurality of storage subunits, each of which is implemented on a die, each communicating with the processing unit 157 using an associated access sub-interface. 2 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention. The flash memory may include j + 1 access sub-interfaces 170_0 to 170_ j , the access sub-interfaces may also be referred to as channels, and each access sub-interface is connected to i + 1 storage sub-units. In other words, i + 1 storage subunits share an access subinterface. For example, when the flash memory comprises four channels (j = 3) and each channel connected to a storage unit 4 (i = 3), flash memory has a total of 16 storage units 180_0_0 to 180_ j _ i. The processing unit 157 may drive the sub-access interface 170_0 to 170_ j by one of read data from the specified storage subunit. Each storage subunit has an independent wafer enable (CE) control signal. In other words, when data reading is to be performed on a specified storage subunit, it is necessary to drive the associated access subinterface to enable the wafer enable control signal of the storage subunit. Figure 3 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention. The processing unit 157 may be accessed through the use of separate sub-wafer interface 170_0 enable control signal to 320_0_0 320_0_ i selects from the storage sub-unit connected to 180_0_ i 180_0_0 wherein one out, then, through the sharing of data lines from the selector 310_0 Read the data at the specified location of the storage subunit.

The processing unit 137 of the host 130 can communicate with the computing device 110 through the designated communication protocol using the access interface 120, for example, a universal serial bus (USB), an advanced technology attachment (ATA), Serial advanced technology attachment (SATA), peripheral component interconnect express (PCI-E) or other interface.

The host 130 and the device 150 each include a UFS InterConnect layer (UIC). The UFS interconnect layer is the lowest layer of the UFS layered architecture, and manages the connection between the host 130 and the device 150. The UFS interconnect layer of the host 130 may include a physical layer (PHY, L1 layer) 131, a physical adapter (L1.5 layer) 133, and a data link (L2 layer) 135. The UFS interconnect layer of the device end 150 may include a physical layer 151, a physical conversion layer 153, and a data connection layer 155. Each of the physical layers 131 and 151 may include a differential output pair, such as TXP and TXN of FIG. 1, for transmitting data to the corresponding end, and a differential input pair, such as RXP and RXN of FIG. The corresponding end receives the data. For example, the physical layer 131 of the host 130 can transmit data to the device end 150 through the differential output pair and receive data from the device terminal 150 through the differential input pair. Conversely, the physical layer 131 of the device end 150 can transmit data to the host 130 through the differential output pair and receive data from the host 130 through the differential input pair.

Each of the main control unit 130 and the device end 150 (also referred to as a transmitting end) can continuously monitor the data frame received from the corresponding end through the bottom layer (for example, the UFS interconnect layer) when running at the high speed file. And/or the control frame, and triggering the data transmission when the data frame and/or the control frame information indicates that the bottom layer of the corresponding end (for example, the UFS interconnection layer) detects the receiving data error when running at the low speed file. Rate setting adjustment. For example, the host 130 can continuously monitor the data frame and/or control frame received from the device end 150, and when the data frame and/or control frame indicates that the lowest layer of the device end 150 is running at a low speed, When the received data error is detected, the data transmission rate setting adjustment is triggered, and vice versa. The preset condition means that the UFS interconnect layer at the corresponding end detects a received data error when running at a low speed. Fig. 4 is a flow chart showing a method of adjusting a data transmission rate setting when operating at a low speed in accordance with an embodiment of the present invention. This method is implemented by processing unit 137 or 157 when loading and executing a particular microcode or software instruction. The pulse width modulation can be implemented in the physical layer of the transmitting end using a hardware circuit for encoding the message into a pulse signal. The physical layer of the transmitting end can adjust the frequency of the pulse signal to obtain a higher or lower data transmission rate. This method can be implemented in the processing unit 137 of the host 130 or the processing unit 157 of the device end 150, which is collectively referred to as a processing unit at the transmitting end. The processing unit of the transmitting end may be a general-purpose processor, a microcontroller, a microcontroller unit (MCU), or the like. The data transmission rate setting adjustment method is implemented when the processing unit at the transmitting end loads and executes the relevant firmware from the non-volatile memory of the transmitting end. The processing unit at the transmitting end can continuously monitor the data frames or control frames received from the other end (or may be referred to as the corresponding end or the receiving end) through the differential input, and determine whether the corresponding information is received. The negative acknowledgement control frame (NAC) of the data connection layer of the previous data is transmitted (step S411). Figure 5 is a classification tree of control and data frames in accordance with an embodiment of the present invention. The data connection layer frame 50 includes two types: a data frame (TCx) 51 and a control frame 53. The information frame 51 can be further divided into two categories: a 0th communication category data frame (TC0, Trraffic Class 0 Data Frames); and a first communication category data frame (TC1, Trraffic Class 0 Data Frames). The control frame family 53 contains a negative acknowledgement control frame 533 that can be recognized or parsed by the logic (hardware circuitry) of the transmitting end. When the corresponding end detects an error in any frame or receives a data frame with an incorrect frame sequence number (FSN), a negative acknowledgement control frame 533 is transmitted to the transmitting end. Figure 6 is a diagram showing the data structure of a negative response control frame in accordance with an embodiment of the present invention. The length of the negative response control frame 533 is 2 symbols, and each symbol is 16 bits. The negative acknowledgement control frame 533 contains RReq bits (bit 0 of the 0th symbol) for requesting the transmitting end to reinitialize the transmitted portion in its physical layer. The negative acknowledgement control frame 533 can be protected (the first symbol) using the CCITT CRC-16 check code 63. Figure 7 is a diagram showing the data structure of a data frame including an overwritten negative response control frame in accordance with an embodiment of the present invention. In other embodiments, the negative acknowledgement control frame 533 can overwrite one of the plurality of DL_SDU bytes and be carried in the data frame 511 or 513.

Since the reason why the corresponding end detects that the previously transmitted data has an error is not necessarily caused by the UFS interconnection layer running at a low speed, further inspection is required to avoid the useless data transmission rate setting adjustment. Refer to Figure 4. When receiving a negative acknowledgement control frame (NAC, negative acknowledgement control frame) corresponding to the data connection layer of the previously transmitted data (the path of YES in step S411), the processing unit at the transmitting end sends a request to the corresponding end for requesting A possible cause associated with the negative response control frame is received, and a response is received from the corresponding end (step S413). This request can be PACP_GET_req as defined in the UFS specification. Figure 8 is a diagram showing the data structure of a PACP_GET_req frame in accordance with an embodiment of the present invention. The PACP_GET_req frame 80 contains the MIBattribute field (2nd symbol) 81, which defines which attributes (Attributes) in the corresponding end are to be accessed. The MIBattribute field in the request defines the error code to be accessed in the corresponding end. The reply may contain an error code indicating the type of error of the error event that occurred in the data connection layer. In some embodiments, the error code can be multiplied by the DLErrorCode enumeration (Enumeration) in the DL_LM_SAP status primitive. Table 1 lists examples of parameters for the DL_LM_SAP state primitive: For example, the error code DLErrorCode=5 indicates that the physical conversion layer of the corresponding end generates a Cyclic Redundancy Check (CRC) error when receiving data. The error code DLErrorCode=13 indicates that the physical layer of the corresponding end has a symbol error when receiving the data.

Refer to Figures 4A through 4B. After receiving the reply from the corresponding end (step S413), the processing unit at the transmitting end determines whether a cyclic redundancy check error or a symbol error has occurred at the lowest layer of the corresponding end (step S431). Since the error occurring at the corresponding end may only occur by chance, the processing unit at the transmitting end can maintain a Bit Error Rate Counter (BER), which is initially 1 to record a cyclic redundancy check error or a symbol error at the corresponding end. The number of times, and the data transmission rate setting adjustment is performed after detecting that the corresponding side has a cyclic redundancy check error or a symbol error at least twice. When a cyclic redundancy check error or a symbol error occurs at the corresponding end (the path of YES in step S431), the processing unit at the transmitting end further determines whether the value of the bit error rate counter reaches or is higher than a preset threshold (for example, 2) Any integer to 10) (step S433). When the value of the bit error rate counter is lower than the preset threshold (the path of NO in step S433), the value of the bit error rate counter is incremented by one (step S451), and the judgment of the next negative response control frame is performed ( Step S411). When the value of the bit error rate counter reaches or exceeds the preset threshold ("YES" path in step S433), the processing unit at the transmitting end adjusts the data transmission rate setting of the physical layer in the transmitting end for the subsequent data frame. The transmission is performed with a new data transmission rate setting (steps S435, S437, S453, S455, and S457). The detailed data transmission rate setting adjustment is described as follows: when the current data transmission rate of the physical layer of the transmitting end is set to the first level (the path along the "No" in step S471, the path and the step of "NO" in step S473. In the path of "NO" in S475, the processing unit at the transmitting end drives the physical layer of the transmitting end to adjust the data transmission rate setting to the second level (step S499). When the current data transmission rate of the physical layer of the transmitting end is set to the second level (the path of "NO" in step S471, the path of "NO" in step S473, and the path of "Yes" in step S475), the transmitting end The processing unit drives the physical layer of the transmitting end to adjust the data transmission rate setting to the third level (step S497). When the current data transmission rate of the physical layer of the transmitting end is set to the third level ("YES" in step S471), the processing unit at the transmitting end drives the physical layer of the transmitting end to adjust the data transmission rate setting to the fourth level (step S491). ). When the current data transmission rate of the physical layer of the transmitting end is set to the fourth level (the path of "NO" in step S471, the path of "Yes" in step S473, and the path of "No" in step S477), the transmitting end The processing unit drives the physical layer of the transmitting end to adjust the data transmission rate setting to the fifth level (step S495). When the current data transmission rate of the physical layer of the transmitting end is set to the fifth level (the path of "NO" in step S471, the path of "Yes" in step S473, and the path of "Yes" in step S477), the transmitting end The processing unit drives the physical layer of the transmitting end to adjust the data transmission rate setting to the first level (step S493). Wherein, the first level is higher than the second level, the second level is higher than the third level, the third level is higher than the fourth level, and the fourth level is higher than the fifth level. In some embodiments, the first level is a maximum data transmission rate x60%, the second level is a maximum data transmission rate x55%, the third level is a maximum data transmission rate x50%, and the fourth level is a maximum data transmission rate x45%, And the fifth level is the maximum data transmission rate x40%. It should be noted that the data transmission rate of the physical layer of the transmitting end is set at a higher level. The data amount of the data transmitted at a higher level is lower than the data transmission rate of the physical layer at the transmitting end per unit time (for example, one second). Time. It should also be noted that when the current data transmission rate of the physical layer of the transmitting end is set to the fifth level, the data transmission rate setting of the physical layer of the transmitting end does not need further adjustment, but instead needs to adjust parameters other than the data transmission rate. Increased transmission reliability at low gears. It should be noted here that each of steps S491, S493, S495, S497, and S499 may reset the value of the bit error rate counter to 1.

9A to 9B are flowcharts of a data transmission rate setting adjustment method when operating at a low speed according to an embodiment of the present invention. Overall, the flow of the FIGS. 9A to 9B omits the maintenance of the bit error rate counter compared to the flow of FIGS. 4A to 4B, that is, the steps S433 and S451 are missing. In detail, when a negative response control frame corresponding to the data connection layer of the previously transmitted data is received from the corresponding end, and a cyclic redundancy check error or a symbol error is detected at the corresponding end ("YES" in step S411" The path of the path is YES in step S431. The processing unit at the transmitting end adjusts the data transmission rate setting of the physical layer in the transmitting end, so that the subsequent data frame is transmitted with the new data transmission rate setting (steps S435, S437). , S453, S455 and S457).

Although the above-described elements are included in FIGS. 1 to 3, it is not excluded that more other additional elements are used without departing from the spirit of the invention, and a better technical effect has been achieved. Further, although the flowcharts of FIGS. 4A, 4B and 9A, 9B are executed in a specified order, those skilled in the art can modify these steps without achieving the same effect without violating the spirit of the invention. The order is so, therefore, the invention is not limited to the use of only the order as described above. In addition, those skilled in the art may also integrate several steps into one step, or in addition to these steps, performing more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements that are apparent to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest form to include all obvious modifications and similar arrangements.

Claims (20)

 A method for reducing error in transmitting data in a flash storage interface is performed by a processing unit at a first end, comprising: continuously supervising a data frame received from a second end and/or a control frame; and The information frame and/or the information contained in the control frame indicates that a data transmission rate setting adjustment is triggered when a bottom layer of the second end detects that the received data is incorrect.    The method for reducing the error in transmitting data in the flash storage interface according to the first aspect of the invention, wherein the first end and the second end communicate with each other through a universal flash storage interface.    The method for reducing the error of transmitting data in the flash storage interface according to claim 2, wherein the bottom layer is a general flash storage interconnect layer, and the universal flash storage interconnect layer comprises a physical layer and a physics. The conversion layer includes: when detecting an error code of the second end reply, indicating that the physical conversion layer of the second end generates a cyclic redundancy check error when receiving the data, or the physical layer of the second end is When the symbol error occurs when receiving data, the above data transmission rate setting adjustment is triggered.    The method for reducing the error of transmitting data in the flash storage interface according to claim 3, comprising: sending a request to a negative response control frame corresponding to a data connection layer of the previously transmitted data The second end is configured to request a reason associated with the negative response control frame; and receive a reply from the second end, wherein the reply includes the error code.    The method for reducing the error in transmitting data in a flash storage interface according to claim 2, wherein the universal flash storage interface operates at 1 Gbps or lower.    The method for reducing the error of transmitting data in the flash storage interface according to claim 2, wherein the bottom layer is a general flash storage interconnect layer, and the universal flash storage interconnect layer comprises a physical layer and a physics. a conversion layer, the processing unit maintaining a one-bit error rate counter for recording the number of times the physical layer and the physical conversion layer of the second end generate an error when receiving the data, the method comprising: detecting the second end reply An error code indicates that the physical conversion layer of the second end generates a cyclic redundancy check error when receiving data, or the physical layer of the second end detects a symbol error when receiving data, and determines one of the bit error rate counters. Whether the value reaches or exceeds a threshold; when the above value of the bit error rate counter reaches or exceeds the threshold, the data transmission rate setting adjustment is triggered.    The method for reducing the error of the transmitted data in the flash storage interface according to claim 6, wherein the threshold is any integer between 2 and 10.    The method for reducing the error of transmitting data in the flash storage interface according to the first aspect of the patent application, wherein the data transmission rate setting adjustment comprises: when a data transmission rate of a physical layer of the first end is set to be one a level, driving the physical layer of the first end to adjust the data transmission rate to a second level; when the data transmission rate of the physical layer of the first end is set to the second level, Driving the physical layer of the first end to adjust the data transmission rate to a third level; and when the data transmission rate setting of the physical layer of the first end is at the third level, driving the first The physical layer of the terminal is configured to adjust the data transmission rate to a fourth level; and when the data transmission rate of the physical layer of the first end is set to be at the fourth level, driving the entity at the first end a layer, configured to adjust the data transmission rate set to a fifth level; when the data transmission rate setting of the physical layer of the first end is When the fifth level is described, the physical layer of the first end is driven to adjust the data transmission rate to the first level; wherein the first level is higher than the second level, and the second level is higher than the foregoing At the third level, the third level is higher than the fourth level, and the fourth level is higher than the fifth level.    The method for reducing the error of the transmitted data in the flash storage interface according to the eighth aspect of the patent application, wherein the first level is a maximum data transmission rate x60%, and the second level is the maximum data transmission rate x55%, The third level is the maximum data transmission rate x50%, the fourth level is the maximum data transmission rate x45%, and the fifth level is the maximum data transmission rate x40%.    The method for reducing the error of the transmitted data in the flash storage interface according to the eighth aspect of the patent application, wherein the data transmission rate of the physical layer at the first end is set to a higher level of data transmitted in one unit time. When the data transmission rate of the physical layer higher than the first end is set to a lower level.    An apparatus for reducing transmission data in a flash storage interface includes: a bottom layer coupled to a corresponding end; and a processing unit coupled to the bottom layer and continuously received from the corresponding end through the bottom layer a data frame and/or a control frame; and triggering a data transmission rate setting adjustment when the data frame and/or the information contained in the control frame indicates that a bottom layer of the corresponding end detects a received data error .    The apparatus for reducing the transmission of data in the flash storage interface according to claim 11, wherein the device and the corresponding end communicate with each other through a universal flash storage interface.    The apparatus for reducing the error of the data in the flash storage interface according to claim 12, wherein the bottom layer is a general flash storage interconnect layer, and the universal flash storage interconnect layer comprises a physical layer and a physics. The conversion layer, and the processing unit detecting that the error code of the corresponding end reply indicates that the physical conversion layer of the corresponding end generates a cyclic redundancy check error when receiving the data, or the physical layer of the corresponding end is when receiving the data When the symbol error occurs, the above data transmission rate setting adjustment is triggered.    The apparatus for reducing the error in the flash storage interface according to claim 13 , wherein the processing unit sends when a negative response control frame corresponding to a data connection layer of the previously transmitted data is received. a request to the second end for requesting a reason associated with the negative acknowledgement control frame; and receiving a reply from the second end, wherein the reply includes the error code.    The apparatus for reducing data transmission in a flash storage interface according to claim 12, wherein the universal flash storage interface operates at 1 Gbps or lower.    The apparatus for reducing the error of the data in the flash storage interface according to claim 12, wherein the bottom layer is a general flash storage interconnect layer, and the universal flash storage interconnect layer comprises a physical layer and a physics. a conversion layer, the processing unit maintaining a one-bit error rate counter for recording the number of times the physical layer and the physical conversion layer of the corresponding end generate an error when receiving the data, and the processing unit detects the reply of the corresponding end An error code indicates that the physical conversion layer of the corresponding end generates a cyclic redundancy check error when receiving data, or the physical layer of the corresponding end generates a symbol error when receiving data, and determines whether a value of the bit error rate counter reaches Or higher than a threshold; and when the above-mentioned value of the bit error rate counter reaches or exceeds the threshold, the data transmission rate setting adjustment is triggered.    The device for reducing the transmission data in the flash storage interface according to claim 16, wherein the threshold is any integer between 2 and 10.    The device for reducing the error in the flash memory storage interface according to claim 11, wherein the de-emphasis setting adjustment comprises: when a data transmission rate setting of the physical layer of the device is at a first level Driving the physical layer of the device to adjust the data transmission rate to a second level; when the data transmission rate of the physical layer of the device is set to the second level, driving the physical layer of the device And adjusting the data transmission rate to a third level; when the data transmission rate setting of the physical layer of the device is at the third level, driving the physical layer of the device to adjust the data transmission rate Setting to a fourth level; when the data transmission rate setting of the physical layer of the device is at the fourth level, driving the physical layer of the device to adjust the data transmission rate to a fifth level; When the data transmission rate setting of the physical layer of the device is at the fifth level, driving The physical layer of the device is configured to adjust the data transmission rate to the first level; wherein the first level is higher than the second level, the second level is higher than the third level, and the third level is higher At the fourth level above, and the fourth level above is higher than the fifth level.    The apparatus for reducing the error in transmitting data in the flash storage interface according to claim 18, wherein the first level is a maximum data transmission rate x60%, and the second level is the maximum data transmission rate x55%. The third level is the maximum data transmission rate x50%, the fourth level is the maximum data transmission rate x45%, and the fifth level is the maximum data transmission rate x40%.    The device for reducing the error in transmitting data in the flash storage interface according to claim 18, wherein the de-emphasis setting of the bottom layer of the physical layer of the device is higher than a data transmitted in one unit time. The amount of data is higher than the above-described de-emphasis setting of the above-mentioned lowest layer of the above-mentioned physical layer of the above device at a lower level.