CN109213624B

CN109213624B - Method and apparatus for reducing errors in data transmission and reception in flash memory interface

Info

Publication number: CN109213624B
Application number: CN201810530621.9A
Authority: CN
Inventors: 施富仁
Original assignee: Silicon Motion Inc
Current assignee: Silicon Motion Inc
Priority date: 2017-06-30
Filing date: 2018-05-29
Publication date: 2022-04-05
Anticipated expiration: 2038-05-29
Also published as: CN109213624A

Abstract

The invention relates to a method for reducing data errors transmitted and received in a flash memory interface and a device using the method, which are executed by a processing unit at a first end, and comprise the following steps: continuously supervising the data signal frames and/or control signal frames received from the second end; and triggering the adjustment of the data transmission rate setting when the message contained in the data signal frame and/or the control signal frame indicates that the lowest layer of the second end detects the received data error.

Description

Method and apparatus for reducing errors in data transmission and reception in flash memory interface

Technical Field

The present invention relates to a flash memory, and more particularly, to a method for reducing errors in data transmission and reception in a flash memory interface and a device using the same.

Background

Flash memory devices are generally classified into NOR flash devices and NAND flash devices. The NOR flash device is a random access device, and a host device (host) can provide an arbitrary address for accessing the NOR flash device on an address pin and obtain data stored in the address on a data pin of the NOR flash device in real time. In contrast, NAND flash devices are not random access, but sequential access. NAND flash devices cannot access any random address as NOR flash devices do, but instead the host device needs to write byte values of the sequence into the NAND flash device to define the type of command (e.g., read, write, erase, etc.) requested, and the address on the command. The address may point to one page (the smallest block of data for one write operation in flash memory) or one block (the smallest block of data for one erase operation in flash memory). In practice, NAND flash devices typically read or write a complete page of data from a memory cell (memory cell). After a full page of data is read from the array into a buffer in the device, the main unit can access the data bit-by-bit or word-by-word (words) by sequentially knocking out the contents using a fetch signal (string signal).

The flash memory device generally includes a device side and a storage unit, and is connected to a host side through a flash storage interface. As the data transmission speed of the flash memory interface is faster and faster, errors are more likely to occur during data transmission and reception. Therefore, a method and apparatus for reducing errors in the transmission and reception of data in a flash memory interface are needed.

Disclosure of Invention

The embodiment of the invention provides a method for reducing data errors transmitted and received in a flash storage interface, which is executed by a processing unit at a first end and comprises the following steps: continuously supervising the data signal frames and/or control signal frames received from the second end; and triggering the adjustment of the data transmission rate setting when the message contained in the data signal frame and/or the control signal frame indicates that the lowest layer of the second end detects the received data error.

The embodiment of the invention provides a device for reducing errors of data transmission and reception in a flash storage interface, which comprises a bottom layer and a processing unit. The bottom layer is coupled to the corresponding end, and the processing unit is coupled to the bottom layer. The processing unit continuously supervises the data signal frames and/or the control signal frames received from the corresponding end through the bottommost layer; and triggering the adjustment of the data transmission rate setting when the information contained in the data signal frame and/or the control signal frame indicates that the lowest layer of the corresponding end detects the received data error.

Drawings

FIG. 1 is a block diagram of a flash memory according to an embodiment of the present invention.

FIG. 2 is a block diagram of an interface and a storage unit according to an embodiment of the invention.

FIG. 3 is a schematic diagram of a connection between an access sub-interface and a plurality of storage sub-units according to an embodiment of the invention.

Fig. 4A-4B are flow charts of a method for adjusting a data transmission rate setting when operating in a low gear according to an embodiment of the present invention.

FIG. 5 is a classification tree for control and data signal frames according to an embodiment of the present invention.

Fig. 6 is a diagram illustrating a data structure of a nack control signal frame according to an embodiment of the present invention.

FIG. 7 is a data structure of a data signal frame including an overwritten frame of a negative acknowledgement control signal according to an embodiment of the invention.

Fig. 8 is a diagram illustrating a data structure of a PACP _ GET _ req signal frame according to an embodiment of the present invention.

Fig. 9A to 9B are flowcharts illustrating a method for adjusting a data transmission rate setting when operating in a low gear according to an embodiment of the invention.

Description of the symbols

110 a computing device;

130 a main control end;

131 physical layer;

133 a physical translation layer;

135 a data connection layer;

137 a processing unit;

150 device side;

151 physical layer;

153 a physical translation layer;

155 a data connection layer;

157 a processing unit;

170 accessing the interface;

170_0 to 170_ j access the subinterface;

180 a storage unit;

180_0_0 to 180_ j _ i storage subunits;

310_ 0data line;

320_0_0 to 320_0_ i chip enable control signals;

s411 to S499;

50 data connection layer signal frames;

51 data signal frames;

511 a 0 th communication type data signal frame;

513 a 1 st communication class data signal frame;

53 control signal frames;

533 negative acknowledgement control signal frame;

61 RReq bits;

63 CCITT CRC-16 check code;

80 PACP _ GET _ req signal frames;

the 81 MIBattributton field.

Detailed Description

The following description is of the best mode for carrying out the invention and is intended to illustrate the general spirit of the invention and not to limit the invention. Reference must be made to the following claims for their true scope of the invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of further features, integers, steps, operations, elements, components, and/or groups thereof.

Use of the terms "first," "second," "third," and the like in the claims is used for modifying elements in the claims, and is not intended to distinguish between elements having the same name, priority, or other relationship, whether one element precedes another element, or is a chronological order in which method steps are performed.

FIG. 1 is a block diagram of a flash memory according to an embodiment of the present invention. The system architecture of the Flash memory includes a device side 150, and communicates with a main control side 130 through a Universal Flash Storage (UFS) interface. The UFS is a flash storage specification for achieving higher data transfer speed and more reliable flash memory storage, and does not require different converters for different types of flash memory cells. Flash memory may be provided in digital cameras, mobile phones, consumer electronics, and the like. The UFS interface can operate in Pulse-Width Modulation (PWM) and High-Speed (HS) modes. The PWM range can be 1Gbps (bits per second) or lower, while the high-speed range can be 1.4Gbps or higher. The PWM range may be referred to as a low range. For example, table 1 lists data transfer rates for different high speed GEARs (HS-GEARs) as defined by the UFS specification:

TABLE 1

For example, the level A data transfer rate for the high gear HS-G1 is 1248Mbps, the level B data transfer rate for the high gear HS-G1 is 1248Mbps, the level A data transfer rate for the high gear HS-G2 is 2496Mbps, the level B data transfer rate for the high gear HS-G2 is 2915.2Mbps, and so on. Table 2 lists the data transmission rates of different pulse width modulation (PWM-GEARs) defined by the UFS specification:

TABLE 2

Pulse width modulation gear	Lowest transmission rate (Mbps)	Highest transmission rate (Mbps)
			PWM-G0	0.01	3
PWM-G1	3	9
			PWM-G2	6	18
PWM-G3	12	36
			PWM-G4	24	72
PWM-G5	48	144
			PWM-G6	96	288
PWM-G7	192	576

The data transmission rate of the low-gear PWM-G0 is between 0.01 and 3Mbps, the data transmission rate of the low-gear PWM-G1 is between 3 and 9Mbps, the data transmission rate of the low-gear PWM-G2 is between 6 and 18Mbps, and so on.

The flash memory further includes a storage unit 180, and the device side 150 communicates with the storage unit 180 using the access interface 170, and may communicate with the storage unit 180 using a Double Data Rate (DDR) protocol, such as Open NAND Flash (ONFI), double data rate switch (DDR toggle) or other interface. The processing unit 157 of the device side 150 writes data to the designated address in the storage unit 180 and reads data from the designated address in the storage unit 180 through the access interface 170. In detail, the processing unit 157 of the device side 150 writes data to the designated address in the storage unit 180 and reads data from the designated address in the storage unit 180 through the access interface 170. The access interface 170 uses a plurality of electronic signals to coordinate data and command transmission between the processing unit of the device side 150 and the storage unit 180, including data lines (data lines), clock signals (clock signals) and control signals (control signals). The data lines can be used for transmitting commands, addresses, read-out data and write-in data; the control signal lines may be used to transmit control signals such as Chip Enable (CE), Address Latch Enable (ALE), Command Latch Enable (CLE), Write Enable (WE), and the like.

Storage unit 180 may include multiple storage subunits, each implemented on a die (die), each communicating with processing unit 157 using an associated access subinterface. FIG. 2 is a block diagram of an access interface and a storage unit according to an embodiment of the invention. The flash memory may include j +1 access sub-interfaces 170_0 to 170_ j, which may be referred to as channels (channels), each of which connects i +1 storage sub-units. In other words, i +1 storage subunits share one access sub-interface. For example, when the flash memory includes 4 channels (j ═ 3) and each channel connects 4 storage units (i ═ 3), the flash memory has 16 storage units 180_0_0 to 180_ j _ i in total. The processing unit 157 may drive one of the access sub-interfaces 170_0 through 170_ j to read data from the designated storage sub-unit. Each storage subunit has an independent Chip Enable (CE) control signal. In other words, when data is to be read from the designated storage subunit, the associated access sub-interface needs to be driven to enable the chip enable control signal of the storage subunit. FIG. 3 is a schematic diagram of a connection between an access sub-interface and a plurality of storage sub-units according to an embodiment of the invention. The processing unit 157 may select one of the connected storage sub-units 180_0_0 to 180_0_ i using the independent chip enable control signals 320_0_0 to 320_0_ i through the access sub-interface 170_0, and then read data from a designated location of the selected storage sub-unit through the shared data line 310_ 0.

The processing unit 137 of the host 130 may communicate with the computing device 110 via a specified communication protocol, such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), PCI express (PCI-E), or other interface, using the access interface 120.

The main control terminal 130 and the device terminal 150 each include an UFS InterConnect layer (UIC). The UFS interconnection layer is the bottom layer of the UFS layered architecture, and manages the connection between the main control terminal 130 and the device terminal 150. The UFS interconnection layer of the master 130 may include a physical layer (PHY, L1 layer)131, a physical adapter (L1.5 layer)133, and a data link (L2 layer) 135. The UFS interconnect layer of the device side 150 may include a physical layer 151, a physical translation layer 153, and a data connection layer 155. Each of the

phy layers

131 and 151 may include a differential output pair, such as TXP and TXN of fig. 1, for transmitting data to a corresponding terminal, and a differential input pair, such as RXP and RXN of fig. 1, for receiving data from a corresponding terminal. For example, the phy 131 of the master 130 may transmit data to the device 150 via the differential output pair and receive data from the device 150 via the differential input pair. On the other hand, the phy 131 of the device side 150 can transmit data to the host 130 through the differential output pair and receive data from the host 130 through the differential input pair.

Each of the master 130 and the device 150 (also referred to as a transmitter) can continuously monitor the data signal frames and/or the control signal frames received from the corresponding node through its bottom layer (e.g., UFS interconnect layer) when operating in the high-speed file, and trigger the adjustment of the data transmission rate setting when the data signal frames and/or the control signal frames contain information indicating that the received data errors are detected when the bottom layer (e.g., UFS interconnect layer) of the corresponding node operates in the low-speed file. For example, the master 130 may continuously monitor the data signal frames and/or the control signal frames received from the device 150, and trigger the adjustment of the data transmission rate setting when the data signal frames and/or the control signal frames indicate that the bottom layer of the device 150 operates in the low-speed gear and a received data error is detected, and vice versa. The preset condition refers to that the UFS interconnection layer of the corresponding end detects a received data error when operating in the low-speed gear. Fig. 4 is a flowchart illustrating a method for adjusting a data transmission rate setting when operating in a low gear according to an embodiment of the invention. The method is performed by the

processing unit

137 or 157 when certain microcode or software instructions are loaded and executed. Pulse width modulation may be implemented in the physical layer of the transmitter using hardware circuitry to encode information into a pulse signal (pulse signal). The physical layer at the transmitting end can adjust the frequency of the pulse signal to obtain a higher or lower data transmission rate. The method may be implemented in the processing unit 137 of the host 130 or the processing unit 157 of the device 150, which are collectively referred to as the transmitting processing unit. The processing unit at the transmitting end may be a general-purpose processor (general-purpose processor), a microcontroller (microcontroller), a microcontroller unit (MCU), or the like. The data transfer rate setting adjustment method is implemented when the processing unit of the transmitter loads and executes the related firmware from the non-volatile memory (non-volatile memory) of the transmitter. The processing unit on the transmitting side may continuously monitor the data frames (data frames) or the control frames (control frames) received from the other end (or the corresponding end or the receiving end) through the differential input pair, and determine whether a negative acknowledgement control frame (NAC) corresponding to the data link layer of the previously transmitted data is received (step S411). FIG. 5 is a classification tree for control and data signal frames according to an embodiment of the present invention. The data connection layer signal frame 50 contains two types: a data signal frame (TCx)51 and a control signal frame 53. The data signal frames 51 can be further classified into two categories: class 0Data signal Frames (TC0, Trrafic Class 0Data Frames); and Class 1 Data signal Frames (TC1, Traffic Class 0Data Frames). The control signal frame family 53 includes the nack control signal frames 533 that can be recognized or parsed by the logic (hardware circuitry) of the transmitting end. When the corresponding terminal detects an error in any signal Frame or receives a data signal Frame having an erroneous signal Frame Number (FSN), a negative acknowledgement control signal Frame 533 is transmitted to the transmitting terminal. Fig. 6 is a diagram illustrating a data structure of a nack control signal frame according to an embodiment of the present invention. The nack control signal frame 533 has a length of 2 symbols (symbols), and each symbol is 16 bits. The nack frame 533 contains the RReq bit (0 th bit of the 0 th symbol) to request the transmitting end to reinitiate the transmitting part in its physical layer. The negative acknowledgement control signal frame 533 may be protected (1 st symbol) using a CCITT CRC-16 check code 63. FIG. 7 is a data structure of a data signal frame including an overwritten frame of a negative acknowledgement control signal according to an embodiment of the invention. In other embodiments, the NAK control signal frame 533 may overwrite one of the DL _ SDU bytes carried in the data signal

frame

511 or 513.

Since the reason why the corresponding terminal detects the error of the previously transmitted data is not necessarily caused by the UFS interconnect layer operating in the low gear, further check is needed to avoid useless adjustment of the data transfer rate setting. Refer to fig. 4. When receiving a negative acknowledgement control signal frame (NAC) corresponding to the data connection layer that has previously transmitted data (yes path in step S411), the processing unit of the transmitting end sends a request to the corresponding end for a possible reason associated with the negative acknowledgement control signal frame, and receives a reply (response) from the corresponding end (step S413). This request may be PACP _ GET _ req as defined in the UFS specification. Fig. 8 is a diagram illustrating a data structure of a PACP _ GET _ req signal frame according to an embodiment of the present invention. The PACP _ GET _ req frame 80 contains the MIBattribyte field (2 nd symbol) 81, which defines which Attributes (Attributes) in the corresponding port are to be accessed. The MIBattribyte field in the request defines the error code in the corresponding port to be accessed. The reply may include an error code indicating the type of error corresponding to the error event occurring at the data link layer. In some embodiments, the error code may be multiplied by the DLErrorCode Enumeration (Enoperation) carried in the DL _ LM _ SAP status primitive (status private). Table 1 lists examples of parameters for the DL _ LM _ SAP status primitive:

TABLE 1

For example, the error code DLErrorCode ═ 5 indicates that a Cyclic Redundancy Check (CRC) error occurs when the physical conversion layer at the corresponding end receives data. The error code DLErrorCode 13 indicates that the physical layer at the corresponding end has a symbol error when receiving data.

Refer to fig. 4A to 4B. After receiving the reply from the peer (step S413), the processing unit of the transmitting peer determines whether a crc error or a symbol error occurs at the bottom layer of the peer (step S431). Since the Error occurred at the corresponding end may only happen accidentally, the processing unit at the transmitting end may maintain a Bit Error Rate counter (BER), which is initially 1, to record the number of times of the cyclic redundancy check Error or symbol Error occurred at the corresponding end, and perform the data transmission Rate setting adjustment after detecting that the cyclic redundancy check Error or symbol Error occurred at the corresponding end at least twice. When a cyclic redundancy check error or a symbol error occurs at the corresponding end (yes in step S431), the processing unit at the transmitting end further determines whether the value of the bit error rate counter reaches or exceeds a preset threshold (e.g., any integer between 2 and 10) (step S433). When the value of the bit error rate counter is lower than the preset threshold (no in step S433), the value of the bit error rate counter is incremented by 1 (step S451), and a next negative acknowledgement control signal frame is determined (step S411). When the value of the bit error rate counter reaches or exceeds the predetermined threshold (yes in step S433), the processing unit at the transmitting end adjusts the data rate setting of the physical layer at the transmitting end so that the subsequent data signal frame is transmitted at the new data rate setting (steps S435, S437, S453, S455, and S457). Detailed data rate setting adjustment is described as follows: when the current data transmission rate of the physical layer of the transmitter is set to be at the first level (sequentially along the no path in step S471, the no path in step S473, and the no path in step S475), the processing unit of the transmitter drives the physical layer of the transmitter to adjust the data transmission rate to be set to the second level (step S499). When the current data transmission rate setting of the physical layer of the transmitter is at the second level (sequentially along the no path in step S471, the no path in step S473, and the yes path in step S475), the processing unit of the transmitter drives the physical layer of the transmitter to adjust the data transmission rate setting to the third level (step S497). When the current data rate setting of the tx phy is at the third level (yes in step S471), the tx processing unit drives the tx phy to adjust the data rate setting to the fourth level (step S491). When the current data rate setting of the physical layer of the sender is at the fourth level (sequentially following the no path in step S471, the yes path in step S473, and the no path in step S477), the processing unit of the sender drives the physical layer of the sender to adjust the data rate setting to the fifth level (step S495). When the current data rate setting of the tx phy is at the fifth level (sequentially following the no path in step S471, the yes path in step S473, and the yes path in step S477), the tx processing unit drives the tx phy to adjust the data rate setting to the first level (step S493). Wherein the first level is higher than the second level, the second level is higher than the third level, the third level is higher than the fourth level, and the fourth level is higher than the fifth level. In some embodiments, the first level is a maximum data transmission rate of x 60%, the second level is a maximum data transmission rate of x 55%, the third level is a maximum data transmission rate of x 50%, the fourth level is a maximum data transmission rate of x 45%, and the fifth level is a maximum data transmission rate of x 40%. It should be noted herein that the data rate of the physical layer at the transmitting end is set at a higher level, and the data amount of the transmitted data is set at a lower level per unit time (e.g., one second) than the data rate of the physical layer at the transmitting end. It should be noted that, when the current data rate setting of the physical layer of the transmitter is at the fifth level, the data rate setting of the physical layer of the transmitter does not need to be further adjusted, but rather, parameters other than the data rate need to be adjusted to improve the transmission reliability at the low gear. It should be noted that each of the steps S491, S493, S495, S497 and S499 may further reset the bit error rate counter to 1.

Fig. 9A to 9B are flowcharts illustrating a method for adjusting a data transmission rate setting when operating in a low gear according to an embodiment of the invention. In general, the flow of fig. 9A to 9B omits the maintenance of the bit error rate counter, i.e., steps S433 and S451 are omitted, compared to the flow of fig. 4A to 4B. In detail, when a negative acknowledgement control signal frame of the data link layer corresponding to the previously transmitted data is received from the corresponding end and a cyclic redundancy check error or a symbol error is detected at the corresponding end (yes path in step S411 followed by yes path in step S431), the processing unit of the transmitting end adjusts the data transmission rate setting of the physical layer in the transmitting end so that the subsequent data signal frame is transmitted at the new data transmission rate setting (steps S435, S437, S453, S455, and S457).

Although fig. 1 to 3 include the above-described elements, it is not excluded that more additional elements may be used to achieve better technical results without departing from the spirit of the present invention. In addition, although the flowcharts of fig. 4A and 4B and fig. 9A and 9B are executed in a designated order, the order of the steps may be modified by those skilled in the art without departing from the spirit of the invention, and thus, the invention is not limited to the order of the steps. In addition, one skilled in the art may also integrate several steps into one step, or perform more steps in sequence or in parallel besides these steps, and the invention is not limited thereto.

While the present invention has been described with reference to the above embodiments, it should be noted that the description is not intended to limit the invention. Rather, the invention encompasses modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements as is readily apparent.

Claims

1. A method for reducing errors in data transmission and reception in a flash memory interface, executed by a processing unit of a first end, includes:

continuously monitoring a data signal frame and/or a control signal frame received from a second terminal; and

when the data signal frame and/or the control signal frame includes information indicating that a receiving data error is detected at a bottom layer of the second end, a data transmission rate setting adjustment is triggered,

wherein the first terminal and the second terminal are interconnected via a universal flash memory interconnect layer, and the universal flash memory interconnect layer is the bottom layer,

wherein the universal flash storage interconnect layer includes a physical layer and a physical translation layer, the processing unit maintains a bit error rate counter for recording the number of times of errors occurring when the physical layer and the physical translation layer at the second end receive data, the method includes:

when detecting that an error code replied by the second terminal indicates that the physical layer of the second terminal generates a cyclic redundancy check error when receiving data or that the physical layer of the second terminal generates a symbol error when receiving data, determining whether a value of the bit error rate counter reaches or is higher than a threshold value;

triggering the adjustment of the data transmission rate setting when the value of the bit error rate counter reaches or exceeds the threshold value.

2. The method of claim 1, wherein the method comprises:

when detecting that an error code replied by the second end indicates that the physical layer of the second end generates a cyclic redundancy check error when receiving data or the physical layer of the second end generates a symbol error when receiving data, triggering the data transmission rate setting adjustment.

3. The method of reducing errors in the transmission and reception of data in a flash storage interface of claim 2, comprising:

sending a request to the second end for a reason associated with a nack control signal frame when a nack control signal frame corresponding to a data link layer previously transmitting data is received; and

receiving a reply from the second end, wherein the reply includes the error code.

4. The method of claim 1 wherein the generic flash interconnect layer operates at 1Gbps or less.

5. The method of claim 1, wherein the threshold is any integer between 2 and 10.

6. The method of claim 1, wherein the adjusting the data transfer rate setting comprises:

driving the physical layer of the first end to adjust a data transmission rate setting of the physical layer of the first end to a second level when the data transmission rate setting is at a first level;

driving the physical layer of the first side to adjust the data transmission rate setting to a third level when the data transmission rate setting of the physical layer of the first side is at the second level;

driving the physical layer of the first side to adjust the data transmission rate setting to a fourth level when the data transmission rate setting of the physical layer of the first side is at the third level;

driving the physical layer of the first side to adjust the data transmission rate setting to a fifth level when the data transmission rate setting of the physical layer of the first side is at the fourth level;

driving the physical layer of the first side to adjust the data transmission rate setting to the first level when the data transmission rate setting of the physical layer of the first side is at the fifth level;

wherein the first level is higher than the second level, the second level is higher than the third level, the third level is higher than the fourth level, and the fourth level is higher than the fifth level.

7. The method of claim 6 wherein the first level is a maximum data transfer rate x 60%, the second level is the maximum data transfer rate x 55%, the third level is the maximum data transfer rate x 50%, the fourth level is the maximum data transfer rate x 45%, and the fifth level is the maximum data transfer rate x 40%.

8. The method of claim 6, wherein the data rate setting of the physical layer of the first side is higher than the data rate setting of the physical layer of the first side is lower than the data rate setting of the physical layer of the first side.

9. An apparatus for reducing errors in the transmission and reception of data in a flash memory interface, comprising:

a bottom layer coupled to a corresponding end; and

a processing unit, coupled to the bottom layer, for continuously monitoring a data signal frame and/or a control signal frame received from the corresponding terminal through the bottom layer; and when the data signal frame and/or the control signal frame contains information indicating that the receiving data error is detected at the bottom layer of the corresponding terminal, triggering a data transmission rate setting adjustment,

wherein the device and the corresponding terminal communicate with each other through a universal flash memory interconnect layer, the universal flash memory interconnect layer being the bottom layer,

the processing unit maintains a bit error rate counter for recording the number of times of errors occurring when the physical layer and the physical conversion layer of the corresponding end receive data, and when detecting that an error code returned by the corresponding end indicates that the physical conversion layer of the corresponding end generates a cyclic redundancy check error when receiving data or that the physical layer of the corresponding end generates a symbol error when receiving data, the processing unit determines whether a value of the bit error rate counter reaches or is higher than a threshold value; and triggering the adjustment of the data transmission rate setting when the value of the bit error rate counter reaches or exceeds the threshold value.

10. The apparatus as claimed in claim 9, wherein the processing unit triggers the adjustment of the data rate setting when detecting an error code returned from the corresponding end indicates that the physical layer of the corresponding end has a crc error when receiving data or the physical layer of the corresponding end has a symbol error when receiving data.

11. The apparatus of claim 10, wherein the processing unit sends a request to the corresponding end for a reason associated with the nack control signal frame when receiving a nack control signal frame corresponding to a data link layer of previously transmitted data; and receiving a reply from the corresponding end, wherein the reply comprises the error code.

12. The apparatus of claim 9 wherein the generic flash interconnect layer operates at 1Gbps or less.

13. The apparatus of claim 9 wherein the threshold is any integer between 2 and 10.

14. The apparatus of claim 9, wherein the adjusting the data rate setting comprises:

driving the physical layer of the device to adjust a data transmission rate setting of the device to a second level when the data transmission rate setting of the physical layer of the device is at a first level;

driving the physical layer of the device to adjust the data transmission rate setting to a third level when the data transmission rate setting of the physical layer of the device is at the second level;

driving the physical layer of the device to adjust the data transmission rate setting to a fourth level when the data transmission rate setting of the physical layer of the device is at the third level;

driving the physical layer of the device to adjust the data transmission rate setting to a fifth level when the data transmission rate setting of the physical layer of the device is at the fourth level;

driving the physical layer of the device to adjust the data transmission rate setting to the first level when the data transmission rate setting of the physical layer of the device is at the fifth level;

15. The apparatus of claim 14 wherein the first level is a maximum data transfer rate x 60%, the second level is the maximum data transfer rate x 55%, the third level is the maximum data transfer rate x 50%, the fourth level is the maximum data transfer rate x 45%, and the fifth level is the maximum data transfer rate x 40%.

16. The apparatus of claim 14 wherein the data rate setting of the physical layer of the lowest layer of the apparatus is at a higher level than the data rate setting of the physical layer of the lowest layer of the apparatus is at a lower level.