TW201905692A - Methods for reducing data error in transceiving of flash storage interface and apparatuses using the same - Google Patents

Abstract

An embodiment of a method for reducing data error in transceiving of flash storage interface, executed by a processing unit of a first side, is introduced to comprise the following steps: descrambling first data received from a second side by an enabled descrambler of a lowest layer; repeatedly monitoring descrambled first data to determine whether a reception-data error occurs; each time detecting that the reception-data error occurs, transmitting a NAC (negative acknowledgement) control frame to the second side for notifying the second side information indicating that the reception-data error for the first data has occurred; and when a total amount of occurrences of the reception-data errors reaches a predefined threshold, disabling the descrambler of the lowest layer.

Description

 Method for reducing transmission data error in flash storage interface and device using the same  

The present invention relates to a flash memory, and more particularly to a method for reducing the error of transmitted data in a flash memory interface and a device using the same.

Flash memory devices are generally classified into NOR flash devices and NAND flash devices. The NOR flash device is a random access device, and the host device can provide any address of the NOR flash device on the address pin, and is instantly stored in the data pin of the NOR flash device. The information on this address. Conversely, NAND flash devices are not random access, but sequential access. The NAND flash device cannot access any random address like the NOR flash device, and the master device needs to write the byte value of the sequence to the NAND flash device to define the request command (command). The type (eg, read, write, erase, etc.) and the address on this command. The address can point to a page (the smallest data block of a write job in flash memory) or a block (the smallest data block of an erase job in flash memory). In fact, NAND flash devices typically read or write complete pages of data from memory cells. When a full page of data is read from the array into a buffer in the device, the main unit can be bitwise or word by sequentially clocking out the content using a strobe signal. A group of words access data.

The flash memory device usually includes a device end and a storage unit, and is connected to the main control terminal by a flash storage interface. As the data transfer speed of the storage interface becomes faster and faster, the data is more prone to errors when it is transmitted. Therefore, there is a need for a method and apparatus for using the method for reducing transmission data errors in a flash storage interface.

Embodiments of the present invention provide a method for reducing data errors transmitted in a flash storage interface, which is executed by a processing unit at a first end, and includes the following steps: descrambling a second received by a bottom-enabled descrambler First information; repeatedly supervising the first data after descrambling to determine whether the receiving data is incorrect; each time the first data after descrambling is detected to receive data error, a negative response control frame is sent to the second end, The information for notifying the second end that the first data after the descrambling is received is incorrect; and when the number of times the received data of the first data after the descrambling is detected reaches the preset threshold, the bottom layer is not enabled. The descrambler.

Embodiments of the present invention provide an apparatus for reducing transmission data errors in a flash storage interface, including a bottom layer and a processing unit. The bottom layer is coupled to the corresponding end and includes a descrambler. The processing unit is coupled to the bottom layer, and the first data received from the corresponding end is descrambled through the bottommost enabled descrambler; and the first data after the descrambling is supervised to determine whether a received data error occurs; When detecting that the first data after the descrambling is incorrectly received, sending a negative response control frame to the corresponding end, for notifying the corresponding end that the information about the first data is incorrectly received; and when detecting the descrambling When the number of received data errors reaches the preset threshold, the lowest level of the descrambler is not enabled.

The embodiment of the present invention proposes another method for reducing data error in the flash storage interface, which is executed by the processing unit at the first end, and includes the following steps: when the first end scrambler is in an enabled state, the method is repeatedly detected. Detecting whether a negative acknowledgement control frame is received from the second end; when the number of times the negative acknowledgement control frame is received reaches a preset threshold, the scrambler is not enabled; when the first end scrambler is disabled And repeatedly detecting whether the response control frame is received from the second end; and when the response control frame is received, enabling the scrambler.

Embodiments of the present invention propose another apparatus for reducing errors in transmitted data in a flash storage interface, including a bottom layer and a processing unit. The bottom layer is coupled to the corresponding end and includes a scrambler. The processing unit is coupled to the bottom layer, and when the scrambler is in an enabled state, repeatedly detecting whether a negative response control frame is received from the corresponding end; when the number of times the negative response control frame is received reaches a preset threshold, The scrambler is not enabled; when the scrambler is in the disabled state, it repeatedly detects whether the response control frame is received from the corresponding end; and when the response control frame is received, the scrambler is enabled.

10‧‧‧Flash memory

110‧‧‧ Computing device

130‧‧‧Master

131‧‧‧ physical layer

133‧‧‧Physical conversion layer

135‧‧‧data connection layer

137‧‧‧Processing unit

150‧‧‧ device side

151‧‧‧ physical layer

153‧‧‧Physical conversion layer

155‧‧‧data connection layer

157‧‧‧Processing unit

170‧‧‧Access interface

170_0~170_ j ‧‧‧Access subinterface

180‧‧‧ storage unit

180_0_0~180_ j _ i ‧‧‧Storage subunit

310_0‧‧‧Information line

320_0_0~320_0_ i ‧‧‧ Chip enable control signal

S411~S493‧‧‧ method steps

50‧‧‧Negative response control frame

S610~S690‧‧‧ method steps

1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

2 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention.

Figure 3 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention.

Fig. 4 is a flow chart showing a method for adjusting data transmission setting at the receiving end according to an embodiment of the present invention.

Figure 5 is a diagram showing the data structure of a negative response control frame in accordance with an embodiment of the present invention.

Figure 6 is a flow chart showing a data transmission setting adjustment method at the transmitting end according to an embodiment of the present invention.

The following description is a preferred embodiment of the invention, which is intended to describe the basic spirit of the invention, but is not intended to limit the invention. The actual inventive content must be referenced to the scope of the following claims.

It must be understood that the terms "comprising", "comprising" and "the" are used in the <RTI ID=0.0> </RTI> <RTIgt; </ RTI> to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude Add more technical features, values, method steps, job processing, components, components, or any combination of the above.

The words "first", "second", and "third" are used in the claims to modify the elements in the claims, and are not used to indicate a priority order, an advance relationship, or a component. Prior to another component, or the chronological order in which the method steps are performed, it is only used to distinguish components with the same name.

1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention. The system architecture of the flash memory 10 includes a device end 150 and communicates with the host 130 through a Universal Flash Storage (UFS) interface. UFS is a flash storage specification for achieving higher data transfer speeds and more reliable flash memory storage, and does not require different converters to be configured due to different types of flash memory cells. The flash memory 10 can be equipped with a digital camera, a mobile phone, a consumer electronic device, and the like. The UFS interface can operate in Pulse-Width Modulation gear (PWM) and High-Speed gear (HS). The pulse width modulation can be 1 Gbps (Gigabits per second) or lower, and the high speed can be 1.4 Gbps or higher. The pulse width modulation file can be referred to as a low speed gear. For example, Table 1 lists the data transfer rates for different high-speed files (HS-GEARs) defined by the UFS specification: For example, the high-speed HS-G1 has a Class A data transmission rate of 1248 Mbps, while the high-speed HS-G1 Class B data transmission rate is 1248 Mbps, and the high-speed file HS-G2 Class A data transmission rate is 2496 Mbps, while the high-speed file HS-G2 has a Class A data transmission rate of 2496 Mbps. G2's Class B data transfer rate is 2915.2 Mbps, and so on. Table 2 lists the data transmission rates of the different pulse width modulation files (PWM-GEARs) defined by the UFS specification: The data transmission rate of the low-speed PWM-G0 is between 0.01 and 3 Mbps, the data transmission rate of the low-speed PWM-G1 is between 3 and 9 Mbps, and the data transmission rate of the low-speed PWM-G2 is between 6 and 18 Mbps. ,So on and so forth.

The flash memory 10 further includes a storage unit 180, and the device end 150 communicates with the storage unit 180 using the access interface 170, and can communicate with the storage unit 180 by using a double data rate (DDR) protocol, for example, NAND flash interface (ONFI), double data rate switch (DDR toggle) or other interface. The processing unit 157 of the device end 150 writes the data to the specified address in the storage unit 180 through the access interface 170, and reads the data from the specified address in the storage unit 180. In detail, the processing unit 157 of the device end 150 writes the data to the specified address in the storage unit 180 through the access interface 170, and reads the data from the specified address in the storage unit 180. The access interface 170 uses a plurality of electronic signals to coordinate data and command transmission between the processing unit 157 of the device end 150 and the storage unit 180, including a data line, a clock signal, and a control signal. ). The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transmit chip enable (CE), address latch enable (ALE), command extraction Control signals such as command latch enable (CLE) and write enable (WE).

The storage unit 180 can include a plurality of storage subunits, each of which is implemented on a die, each communicating with the processing unit 157 using an associated access sub-interface. 2 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention. The flash memory 10 may include j + 1 access sub-interfaces 170_0 to 170_ j , the access sub-interfaces may also be referred to as channels, and each access sub-interface is connected to i + 1 storage sub-units. In other words, i + 1 storage subunits share an access subinterface. For example, when the flash memory 10 comprises four channels (j = 3) and each channel connected to a storage unit 4 (i = 3), flash memory 10 has a total of 16 storage units 180_0_0 to 180_ j _ i . The processing unit 157 may drive the sub-access interface 170_0 to 170_ j by one of read data from the specified storage subunit. Each storage subunit has an independent wafer enable (CE) control signal. In other words, when data reading is to be performed on a specified storage subunit, it is necessary to drive the associated access subinterface to enable the wafer enable control signal of the storage subunit. Figure 3 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention. The processing unit 157 may be accessed through the use of separate sub-wafer interface 170_0 enable control signal to 320_0_0 320_0_ i selects from the storage sub-unit connected to 180_0_ i 180_0_0 wherein one out, then, through the sharing of data lines from the selector 310_0 Read the data at the specified location of the storage subunit.

The processing unit 137 of the host 130 can communicate with the computing device 110 through the designated communication protocol using the access interface 120, for example, a universal serial bus (USB), an advanced technology attachment (ATA), Serial advanced technology attachment (SATA), peripheral component interconnect express (PCI-E) or other interface.

The host 130 and the device 150 each include a UFS InterConnect layer (UIC). The UFS interconnect layer is the lowest layer of the UFS layered architecture, and manages the connection between the host 130 and the device 150. The UFS interconnect layer of the host 130 may include a physical layer (PHY, L1 layer) 131, a physical adapter (L1.5 layer) 133, and a data link (L2 layer) 135. The UFS interconnect layer of the device end 150 may include a physical layer 151, a physical conversion layer 153, and a data connection layer 155. Each of the physical layers 131 and 151 may include a differential output pair, such as TXP and TXN of FIG. 1, for transmitting data to the corresponding end, and a differential input pair, such as RXP and RXN of FIG. The corresponding end receives the data. For example, the physical layer 131 of the host 130 can transmit data to the device end 150 through the differential output pair and receive data from the device terminal 150 through the differential input pair. Conversely, the physical layer 131 of the device end 150 can transmit data to the host 130 through the differential output pair and receive data from the host 130 through the differential input pair.

Each of the main control terminal 130 and the device terminal 150 (also referred to as the receiving end) can be enabled by the lowest layer (eg, UFS interconnect layer) to operate the descrambler when operating at high speed or low speed ( Descramler) descrambles the data received from the corresponding end to obtain the descrambled data, and determines whether the descrambled data has an error. For example, the host 130 can descramble the data received from the device end 150 to obtain the data frame and/or the control frame, and determine whether the data frame and/or the control frame have received data errors, and vice versa. When the receiving end detects that the descrambled data has an error, the negative acknowledgement control frame (NAC) is transmitted to the corresponding end. Moreover, when detecting that the descrambled data has an error and reaches a preset number of times, the descrambler is not enabled. On the other hand, when the corresponding end receives the negative response control frame to reach the preset number of times, the scrambler is not enabled. On the other hand, when the bottom layer of the receiving end does not enable the descrambler (that is, when the bottom layer of the corresponding end does not enable the scrambler), the receiving end continuously monitors the received data frame and/or control frame, and when When it is detected that there is no error in receiving data, the descrambler is enabled and an acknowledgment control frame (ACK) is sent to the corresponding end. For example, when the bottom layer of the host 130 is not capable of the descrambler, the host 130 continuously monitors the received data frame and/or the control frame, and when it detects that there is no error in receiving data, the solution is enabled. The scrambler also transmits a response control frame to the device end 150 and vice versa. On the other hand, when the corresponding end receives the response control frame, the scrambler is enabled. The scrambler can be implemented in the physical conversion layer of the transmitting end using a hardware circuit, and the descrambler can be implemented in the physical conversion layer of the receiving end using a hardware circuit. It should be noted here that scrambling data can improve security, but it may increase the chances of data generating errors in transmission.

Fig. 4 is a flow chart showing a method for adjusting data transmission setting at the receiving end according to an embodiment of the present invention. This method is implemented by processing unit 137 or 157 when loading and executing a particular microcode or software instruction. The processing unit at the receiving end may be a general-purpose processor, a microcontroller, a microcontroller unit (MCU), or the like. The adjustment method described below is implemented when the processing unit at the receiving end loads and executes the relevant firmware from the non-volatile memory of the receiving end. The processing unit at the receiving end can receive data from the other end (or can be referred to as a corresponding end or a transmitting end) through the differential input pair, and descramble the data received from the corresponding end through the bottom layer enabled descrambler to obtain descrambling After the information. It is determined whether a physical redundancy layer at the receiving end detects a Cyclic Redundancy Check (CRC) error, or a physical layer detects a symbol error at the receiving end (step S411). When the cyclic redundancy check error or the symbol error of the data after descrambling is not detected or the descrambler is not enabled (NO in step S411), the received data determination for the next round is performed (step S411). . When a cyclic redundancy check or a symbol error of the descrambled data is detected ("YES" in step S411), a negative response control frame is transmitted to the corresponding end (step S413). Figure 5 is a diagram showing the data structure of a negative response control frame in accordance with an embodiment of the present invention. The length of the negative response control frame 50 is 2 symbols, and each symbol is 16 bits.

Since the error of receiving data may only happen by chance, the processing unit at the receiving end can maintain a Bit Error Rate Counter (BER), which is initially 1 to record the detection of a cyclic redundancy check error or a symbol error. The number of times, and then adjust after detecting a cyclic redundancy check error or a symbol error multiple times. For example, when the negative response control frame is transmitted to the corresponding end (step S413), the processing unit at the receiving end further determines whether the value of the bit error rate counter reaches or exceeds a preset threshold (for example, an arbitrary integer between 2 and 10) (Step S431). When the value of the bit error rate counter is lower than the preset threshold (the path of NO in step S431), the value of the bit error rate counter is incremented by one (step S433), and the received data determination for the next round is performed (step S411). ). When the value of the bit error rate counter reaches or exceeds the preset threshold (the path of YES in step S431), the processing unit at the receiving end does not enable the descrambler of the physical conversion layer in the receiving end (step S450). In step S450, it should be noted that the processing unit at the receiving end does not need to send any message to the corresponding end to disable the scrambler of the corresponding end, so as to save the bandwidth used between the receiving end and the corresponding end. Instead, the corresponding end also maintains a counter, and increments the value of the counter each time it receives a negative acknowledgement control frame from the receiving end. For details on the corresponding end of the scrambler, refer to the following description.

In other embodiments, the processing unit at the receiving end may not maintain the bit error rate counter, and steps S431 and S433 are omitted. In other words, when a cyclic redundancy check error or a symbol error is detected, the processing unit at the receiving end determines that the descrambler is not required. In other embodiments, the preset threshold in step S431 can be set to 1, after detecting a cyclic redundancy check error or a symbol error, the processing unit at the receiving end determines that the descrambler is not required. .

When the descrambler of the physical layer is disabled in the receiving end, the processing unit at the receiving end can continuously supervise the data received from the corresponding end through the differential input, and determine whether the cyclic redundancy check is detected at the physical translation layer of the receiving end. An error, or a symbol error is detected at the physical layer of the receiving end (step S470). When the cyclic redundancy check or the symbol error is still detected (the path of YES in step S470), the processing unit at the receiving end maintains the descrambler of the physical layer in the receiving end and the processing unit indicating the corresponding end is not enabled. The scrambler of the physical layer in the corresponding end (step S450). When no cyclic redundancy check or symbol error is detected (NO in step S470), the processing unit at the receiving end enables the descrambler of the physical conversion layer and the transmission response control frame in the receiving end to the corresponding end. (Step S491), and the value of the reset bit error rate counter is 1 (step S493).

Figure 6 is a flow chart showing a data transmission setting adjustment method at the transmitting end according to an embodiment of the present invention. This method is implemented by processing unit 137 or 157 when loading and executing a particular microcode or software instruction. The processing unit at the transmitting end may be a general purpose processor, a microcontroller, a microcontroller unit, or the like. When the scrambler of the physical translation layer of the transmitting end is in the enabled state, the processor of the transmitting end repeatedly detects whether a negative acknowledgement control frame is received from the corresponding end (also referred to as the receiving end) (step S610).

Since the error of receiving data may only happen by chance, the processing unit at the transmitting end can also maintain a negative response counter for recording the number of times the negative response control frame is received, and then adjusting after receiving the negative response control frame multiple times. . For example, when a negative response control frame is received from the corresponding end (the path of YES in step S610), the processing unit at the transmitting end further determines whether the value of the negative response counter has reached or exceeded the preset threshold (step S631). It should be noted here that the preset threshold in step S631 is the same as the preset threshold corresponding to the bit error rate counter in the corresponding end, for example, the preset threshold as shown in step S431. When the value of the negative response counter is lower than the preset threshold (the path of NO in step S631), the value of the negative response counter is incremented by 1 (step S633), and the determination of the next round is made (step S610). When the value of the negative response counter reaches or exceeds the preset threshold (the path of YES in step S631), the processing unit at the transmitting end does not enable the scrambler of the physical conversion layer (step S650). When the scrambler of the physical conversion layer of the transmitting end is in the disabled state, the processor of the transmitting end repeatedly detects whether the response control frame is received from the corresponding end (step S670). When the response control frame is received from the corresponding end (the path of YES in step S670), the processing unit at the transmitting end enables the scrambler of the physical conversion layer (step S690).

It should be noted that the response control frame and the negative response control frame are information used in the universal flash storage specification to allow the receiving end to correctly receive and transmit an error before the reply to the corresponding end. The enabling and disabling of the scrambler and the descrambler based on the standard response control frame and the negative response control frame eliminates the need to additionally generate and interpret the customized request.

Although the above-described elements are included in FIGS. 1 to 3, it is not excluded that more other additional elements are used without departing from the spirit of the invention, and a better technical effect has been achieved. Further, although the flowcharts of FIGS. 4 and 6 are executed in a specified order, those skilled in the art can modify the order among the steps without achieving the same effect without departing from the spirit of the invention. Therefore, the present invention is not limited to the use of only the order as described above. In addition, those skilled in the art may also integrate several steps into one step, or in addition to these steps, performing more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements that are apparent to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest form to include all obvious modifications and similar arrangements.

Claims (20)

 A method for reducing the error of the transmitted data in the flash storage interface is performed by a processing unit at the first end, comprising: descrambling the first data received from a second end through a bottom-deacting descrambler; Supervising the first data after descrambling to determine whether a received data error occurs; each time the first data after the descrambling is detected to have the received data error, sending a negative response control frame to the second end And the second terminal is configured to notify the first data that the received data error occurs; and when the number of times the received data is detected to be a predetermined threshold is detected, The above-mentioned descrambler capable of the above-mentioned bottom layer.    The method for reducing the error of the transmitted data in the flash storage interface according to the first aspect of the patent application includes: when detecting that the number of times the received data error occurs in the first data after the descrambling reaches the preset threshold A request for not enabling a scrambler of the second end is not sent to the second end.    The method for reducing the error of transmitting data in the flash storage interface according to claim 1, wherein the bottom layer is a general flash storage interconnect layer, and the universal flash storage interconnect layer comprises a physical layer and a physics. The conversion layer, the received data error of the descrambled first data indicates that the physical conversion layer detects a cyclic redundancy check error in the descrambled first data or the physical layer is after the descrambling The first data detects a symbol error and the preset threshold is 1.    The method for reducing the error of transmitting data in the flash storage interface according to claim 1, wherein the bottom layer is a general flash storage interconnect layer, and the universal flash storage interconnect layer comprises a physical layer and a physics. The conversion layer, the received data error of the descrambled first data indicates that the physical conversion layer detects a cyclic redundancy check error in the descrambled first data or the physical layer is after the descrambling The first data detects a symbol error and the predetermined threshold is any integer between 2 and 10.    The method for reducing the error of transmitting data in the flash storage interface according to claim 4, wherein the cyclic redundancy check error and the number of the symbol errors are recorded in a one-bit error rate counter, and the method includes: When the above cyclic redundancy check error or the above symbol error is detected, the value of the above bit error rate counter is incremented by one.    The method for reducing the error in transmitting data in the flash storage interface according to claim 5, wherein the second end maintains a negative response counter; when the negative response control frame is received from the first end The value of the negative acknowledgement counter is incremented by one; and when the value of the negative acknowledgement counter reaches the preset threshold, a scrambler is not enabled.    The method for reducing the error of transmitting data in the flash storage interface according to the first aspect of the patent application includes: when the descrambler is disabled, detecting whether a second data received from the second end does not occur The receiving data is incorrect; and when the second data is detected that the receiving data error does not occur, enabling the bottommost descrambler and transmitting a response control frame to the second end.    The method for reducing the error of transmitting data in the flash storage interface according to claim 7, wherein when the second terminal receives the response control frame from the first end, a scrambler is enabled.    A method for reducing the error of the transmitted data in the flash storage interface is performed by a processing unit at the first end, and includes: when the first scrambler of the first end is in a consistent state, detecting whether the second end is from a second end Receiving a negative response control frame; when the number of times the negative acknowledgement control frame is received reaches a preset threshold, the scrambler is disabled; when the first end of the scrambler is in an inactive state And repeatedly detecting whether a response control frame is received from the second end; and when the response control frame is received, enabling the scrambler.    The method for reducing the error in transmitting data in the flash storage interface according to claim 9, wherein the first end maintains a negative response counter, and the method includes: receiving the negative response control from the second end In the frame, the value of the above negative acknowledgement counter is incremented by one.    An apparatus for reducing the error of the transmitted data in the flash memory interface includes: a bottom layer coupled to a corresponding end, including a descrambler; and a processing unit coupled to the bottom layer to enable the bottom layer The above-mentioned descrambler descrambles the first data received from the corresponding end; repeatedly supervises a descrambled first data to determine whether a received data error occurs; each time the descrambled first data is detected When the received data is incorrect, a negative response control frame is sent to the corresponding end to notify the corresponding end that the information about the received data error occurs in the first data; and when the descrambled first data is detected When the number of times the received data error occurs reaches a predetermined threshold, the above-mentioned lowest level of the above-mentioned descrambler is not enabled.    The apparatus for reducing the error of the data in the flash storage interface according to claim 11, wherein the processing unit detects that the number of times the received data is incorrect after the descrambling first data reaches the preset At the threshold, a request for disabling the scrambler of the second end is not sent to the second end.    The apparatus for reducing the error of the data in the flash storage interface according to claim 11, wherein the bottom layer is a general flash storage interconnect layer, and the universal flash storage interconnect layer comprises a physical layer and a physics. The conversion layer, the received data error of the descrambled first data indicates that the physical conversion layer detects a cyclic redundancy check error in the descrambled first data or the physical layer is after the descrambling The first data detects a symbol error and the preset threshold is 1.    The apparatus for reducing the error of the data in the flash storage interface according to claim 11, wherein the bottom layer is a general flash storage interconnect layer, and the universal flash storage interconnect layer comprises a physical layer and a physics. The conversion layer, the received data error of the descrambled first data indicates that the physical conversion layer detects a cyclic redundancy check error in the descrambled first data or the physical layer is after the descrambling The first data detects a symbol error and the predetermined threshold is any integer between 2 and 10.    The apparatus for reducing the error in the flash memory storage interface according to claim 14, wherein the cyclic redundancy check error and the number of the symbol errors are recorded by a one-bit error rate counter, and the processing unit is When the above cyclic redundancy check error or the above symbol error is detected, the value of the bit error rate counter is incremented by one.    The device for reducing the transmission data in the flash storage interface according to claim 15 , wherein the corresponding end maintains a negative response counter; when the negative response control frame is received from the device, the negation is The value of the response counter is incremented by one; and when the value of the negative acknowledgement counter reaches the predetermined threshold, a scrambler is not enabled.    The apparatus for reducing the error of the data in the flash storage interface according to claim 11, wherein the processing unit repeatedly detects whether a second data received from the corresponding end is detected when the descrambler is disabled The above received data error does not occur; and when the second data is detected that the received data error does not occur, the bottommost descrambler is enabled and a response control frame is transmitted to the corresponding end.    The apparatus for reducing transmission data in a flash storage interface according to claim 17, wherein when the corresponding terminal receives the response control frame from the device, a scrambler is enabled.    An apparatus for reducing transmission data in a flash storage interface includes: a bottom layer coupled to a corresponding end, including a scrambler; and a processing unit coupled to the bottom layer, when the scrambler is In the state of consistent energy, it is repeatedly detected whether a negative acknowledgement control frame is received from the corresponding end; when the number of times the negative acknowledgement control frame is received reaches a preset threshold, the scrambler is not enabled; When the scrambler is in a disable state, it repeatedly detects whether a response control frame is received from the corresponding end; and when the response control frame is received, the scrambler is enabled.    The apparatus for reducing the transmission data in the flash storage interface according to claim 19, wherein the processing unit maintains a negative response counter; and when receiving the negative response control frame from the corresponding end, The value of the above negative response counter is incremented by one.