TW201834183A - 隔離金屬化特徵之氣隙 - Google Patents

隔離金屬化特徵之氣隙 Download PDF

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TW201834183A
TW201834183A TW106113769A TW106113769A TW201834183A TW 201834183 A TW201834183 A TW 201834183A TW 106113769 A TW106113769 A TW 106113769A TW 106113769 A TW106113769 A TW 106113769A TW 201834183 A TW201834183 A TW 201834183A
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dielectric material
low
metal lines
air gap
dielectric
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TWI690048B (zh
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哈 高明
孫志國
約瑟夫Ｆ 史帕德二世
張木申Ｍ
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格羅方德半導體公司
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Abstract

本揭示內容係有關於半導體結構，更特別的是，有關於隔離金屬線之氣隙及其製法。該結構包括：複數條金屬線，其形成於絕緣體層上；以及介電材料，其完全填充在該等複數條金屬線的金屬線之間具有第一尺寸的空間以及在該等複數條金屬線的金屬線之間具有第二尺寸的空間提供均勻氣隙。該第一尺寸大於該第二尺寸。

Description

隔離金屬化特徵之氣隙
本揭示內容係有關於半導體結構，且更特別的是，有關於隔離金屬化特徵之氣隙及其製法。
半導體製造的後段(BEOL)製程由互連個別裝置(例如，電晶體、電容器、電阻器等等)至金屬化特徵的後段(BEOL)製程組成。具體而言，BEOL通常包括形成或沉積接觸件、絕緣層(例如，電介質)、金屬層(metal level)、以及用於晶片至封裝件連接的接合部位。
BEOL方案的挑戰是如何使金屬線在正常裝置操作期間與串擾及電阻電容延遲(RC delay)隔離，特別是在較小的技術節點。當前，PECVD超低k介電(ULK)材料用作防止金屬線間之EMF串擾的屏障。與使用ULK及/或奈米多孔材料有關的某些最具挑戰性的問題係在於工業正接近到建造用於較低電介質(亦即，k=2.2及以下)之材料的極限。事實上，當前沒有低於k=2.1的穩定材料。而且，即使有可能合成低於k=2.2的材料，它還是極不穩定、脆弱且容易洩露。
在本揭示內容之一態樣中，一種結構，包含：複數條金屬線，其形成於絕緣體層上；以及介電材料，其完全填充在該等複數條金屬線的金屬線之間具有第一尺寸的空間以及在該等複數條金屬線的金屬線之間具有第二尺寸的空間提供均勻氣隙。該第一尺寸大於該第二尺寸。
在本揭示內容之一態樣中，一種結構，包含：可微調低k介電材料，其完全填充在基板上的金屬線之間具有第一尺寸的空間，以及在同一個沉積製程中，在該基板上的其他金屬線之間具有第二尺寸的空間形成均勻氣隙。
在本揭示內容之一態樣中，一種方法，包含：在絕緣體層上形成數條金屬線；以及在該等金屬線之間沉積低k介電材料於該絕緣體層上，該沉積包含：化學氣相沉積毛細凝結技術，其形成氣隙於以第一尺寸互相隔開的金屬線之間，以及完全填充在金屬線之間具有第二尺寸之空間內。
10、10'‧‧‧結構
12‧‧‧絕緣體材料
14a-14e‧‧‧金屬化特徵、金屬線
16‧‧‧低k介電材料
18‧‧‧均勻氣隙、氣隙
20‧‧‧完全間隙填充
100‧‧‧基板
110‧‧‧介電材料或金屬層
120‧‧‧柱體
130‧‧‧襯裡
135‧‧‧覆蓋襯裡、襯裡
140‧‧‧襯裡、低k介電材料
150‧‧‧溝槽
160‧‧‧金屬材料、銅材料
A‧‧‧固化前曲線
B‧‧‧固化後曲線
以下說明詳述本揭示內容，其中參考多個附圖以不具限定性的方式舉例說明本揭示內容的示範具體實施例。
第1圖根據本揭示內容之數個態樣圖示除其他特徵以外具有氣隙的結構，及各個製程。
第2圖根據本揭示內容之數個態樣圖示除其他特徵以外具有用間隙填充材料形成之均勻氣隙的結 構，及各個製程。
第3圖根據本揭示內容之數個態樣圖示除其他特徵以外具有均勻氣隙的結構以及金屬線之間的填充間隙，及各個製程。
第4圖根據本揭示內容之數個態樣圖示間隙填充材料(例如，低k介電材料)在固化之前及之後的曲線圖。
第5圖的曲線圖圖示氣隙的可微調性，其係藉由改變間隙填充材料的前驅物材料比率。
第6圖圖示低k介電材料使用dHF的濕蝕刻率。
第7圖至第11圖圖示根據本揭示內容之其他態樣的結構及各個製程。
本揭示內容係有關於半導體結構，且更特別的是，有關於隔離金屬化特徵(例如，金屬線)之氣隙及其製法。更特別的是，本揭示內容提供藉由毛細作用來沉積用以形成隔離金屬線之氣隙的低k介電材料。有利的是，利用毛細作用沉積製程，低k介電材料在需要氣隙的特徵上展現優越的間隙填充性能，而且控制良好且可輕易微調。
在數個具體實施例中，係利用化學氣相沉積(CVD)毛細凝結技術形成氣隙，用以產生用於氣隙低k介電材料間隙填充的彎液面(meniscus)。CVD毛細凝結會產 生在金屬線之間的氣隙，以及提供較大特徵的完全間隙填充。因此，低k介電材料展現獨特的間隙填充能力，它在有挑戰性之特徵(例如，較大的特徵)上容易進行間隙填充且同時建立較小特徵的氣隙。再者，利用用於低k介電材料沉積的毛細凝結技術，藉由微調及修改個別間隙結構的參數，可輕易地控制氣隙。
可用使用許多不同工具的許多方法製造本揭示內容的結構。然而，通常該等方法及工具是用來形成具有微米及奈米級尺寸的結構。用來製造本揭示內容之結構的該等方法，亦即，技術，係選自積體電路(IC)技術。例如，該等結構建立於晶圓上以及實現於在晶圓上面用光微影製程(photolithographic process)圖案化的材料膜中。特別是，該等結構的製造使用以下3個基本建造區塊：(i)沉積材料薄膜於基板上，(ii)用光微影成像法鋪設圖案化遮罩於薄膜上面，以及(iii)對於該遮罩選擇性地蝕刻薄膜。
第1圖根據本揭示內容之態樣圖示一種結構及各個製程。如第1圖所示，結構10包括形成於絕緣體材料12上的複數個金屬化特徵14a-14e，例如，配線線路。在數個具體實施例中，絕緣體材料12為低k介電材料，例如，基於氧化物的材料。絕緣體材料12可為層間介電材料。
在具體實施例中，金屬化特徵(以下稱為金屬線)14a-14e可用習知減去法形成。例如，使用任何習知沉積法(例如，化學氣相沉積(CVD)法)，可將金屬或金屬合金材料(例如，銅、鋁等等)毯覆式沉積(blanket deposit)於 絕緣體材料12上方。形成於金屬或金屬合金材料上方的抗蝕劑暴露於能量(光線)以形成圖案(開口)。用選擇性化學物的蝕刻製程，例如，反應性離子蝕刻(RIE)，會用來形成一或多個該等金屬化特徵，例如，金屬線14a-14e。然後，可用習知氧氣灰化製程(oxygen ashing process)或其他習知去膜劑(stripant)移除抗蝕劑。
在移除抗蝕劑後，可沉積低k介電材料16於金屬線14a-14e之間。低k介電材料16可使用毛細凝結技術沉積，例如，CVD毛細凝結技術。在數個具體實施例中，相較於例如電漿增強式CVD(PECVD)的習知沉積法，該CVD毛細凝結技術會產生均勻氣隙18。例如，第2圖圖示均勻氣隙18。
一般而言，該毛細凝結沉積法會允許低k介電材料16形成於金屬線14a-14e的側壁上。當低k介電材料16形成於金屬線14a-14e的側壁上時，它最終會完全囊封空氣，這會形成均勻氣隙18。囊封過程為彎液面形成(meniscus formation)與重力的組合，其中止彎液面形成並且在低k介電材料16滾過空氣時捕捉空氣，完全囊封空氣以及形成氣隙18。
具體而言，毛細凝結為一種過程，從蒸汽進入多孔介質之多層吸附(multilayer adsorption)透過此過程進行到孔隙空間變成填滿來自蒸汽之凝結液體為止。毛細凝結的獨特方面是在液體的飽和蒸氣壓Psat以下發生蒸汽凝結。此結果是由於蒸汽相分子在毛細管之局限空間內 的凡得瓦交互作用(van der Waals interaction)次數增加。一旦發生凝結，彎液面立刻在液汽介面形成，這允許在飽和蒸氣壓以下平衡。彎液面形成取決於材料的表面張力與毛細管的形狀，如楊-拉普拉斯方程式(Young-Laplace equation)所示。藉由形成彎液面，可從彎液面形成毛細管或氣隙，這可利用凝結的附著(adhesion)及凝聚(cohesion)精確地控制。氣隙可採用許多形狀，例如管狀、橢圓形或其他形狀。
請參考第1圖及第2圖，均勻氣隙18形成於金屬線14a、14b，金屬線14c、14d及金屬線14d、14e之間的較小區域(例如，特徵大小約小於80奈米)內；然而，CVD毛細凝結技術會導致在金屬線14b、14d之間的較大區域(例如，特徵大小大於80奈米)內的完全間隙填充(用元件符號20表示)，，如第1圖及第3圖所示。因此，在特徵小於80奈米以及小於有較大尺寸的完全間隙填充時建立氣隙。在具體實施例中，相較於有較高介電常數的介電材料，氣隙18會有k=1的介電常數。
在具體實施例中，低k介電材料16可具有相對低的介電常數，例如，約2.5至3.5；然而藉由調整形成低k介電材料16的前驅物比率，可微調此一介電常數。例如，在具體實施例中，低k介電材料16最好從由甲基組成的前驅物形成，該甲基與TMOS(正矽酸甲酯)及O2反應以在經受某一溫度時產生交聯低k介電材料。具體而言，低k介電材料16可包括在經受固化製程後交聯的下列前驅物(例如，前驅物為八甲基環四矽氧烷 (octamethylcyclotetrasilozane)、TMOS及O2)，亦即：
在具體實施例中，提供溫度範圍在約250℃至約500℃持續約2至10分鐘的固化。該固化(例如，在紫外光及熱之下)會驅散氫及水分，並且會使結構與氧交聯以形成低k介電材料16。例如，可用紫外輻射提供該固化製程。相較於習知ULK介電材料，低k介電材料16在550℃以上穩定，其穩定性由較高的固化速率而加以穩定。
第4圖圖示介電材料16之有機結構在固化前(用“A”表示的曲線)及固化後(用“B”表示的曲線)的曲線圖，例如，交聯結構。如圖示，在處於固化後狀態時，例如，在經歷約250℃至約500℃之溫度範圍持續約2至10分鐘的紫外光處理後，水被驅散以及結構用氧接合在一起以具有改良強度(相較於習知ULK材料)的有機交聯。
此外，在具體實施例中，可調整前驅物(例如，與TMOS及O2反應的甲基)的比率以微調低k介電材 料16的材料特性及流動性。例如，在一設想的具體實施例中，提供比率為10：1：5導致有約5埃至10埃之多孔性的前驅物。
具體而言，如第5圖所示，藉由調整低k介電材料16的前驅物比率，可微調該氣隙。亦即，可微調氣隙的大小使得在特徵之間完全間隙填充至100%氣隙，或在其間的任何百分比氣隙。例如，在正規化O2對前驅物材料(甲基及TMOS)有約1.24的比率時，在較小尺寸的金屬線之間有100%氣隙。因此，相較於奈米多孔材料的沉積，低k介電材料16在氣隙形成及間隙填充方面顯示有改良的可控制性。
此外，低k介電材料16(用CVD毛細凝結技術沉積)提供優於奈米多孔材料的改良機械性質，以及改良的楊氏係數及附著強度。低k介電材料16對於濕蝕刻化學物(例如，dHF)也有高度抵抗力，以及用使用於化學機械研磨(CMP)及RIE製程的泥漿提供改良的移除選擇比(removal selectivity)。例如，第6圖圖示低k介電材料16在100：1dHF的濕蝕刻率。在第6圖中，平均蝕刻率約為每分鐘2埃，以及270秒的平均蝕刻率總共約有6埃。低k介電材料16在熱磷酸中也有低蝕刻率，例如，5分鐘、550℃(UV)約有8.4埃。低k介電材料16的蝕刻選擇比(etch selectivity)也有大約比TEOS慢四倍的蝕刻率。
第7圖至第11圖根據本揭示內容之數個額外態樣圖示數種結構及各個製程。例如，第7圖至第11 圖圖示在金屬化特徵上的襯裡材料形成均勻氣隙，以及用低k介電材料來形成氣隙，但不限於此。在具體實施例中，襯裡材料可具有可微調的介電常數，例如，k=4.0至4.5，以及最好對於濕蝕刻化學物(亦即，DHF、熱磷酸等等)有高度抵抗力。相較於低k介電材料，襯裡材料也是緻密膜(dense film)。
具體而言，第7圖圖示結構10'，其包含含有數個金屬化下層的基板100。使用例如CVD的習知沉積製程沉積介電材料或金屬層110於基板100上。使用習知沉積、微影及蝕刻製程(例如，RIE)，形成柱體120於材料110上。在數個具體實施例中，柱體120可圖案化成具有後續形成的金屬化特徵的尺寸。柱體120由非晶矽(或對襯裡材料及層間介電材料有選擇性的其他材料)形成。
仍參考第7圖，使用共形沉積製程沉積襯裡130於柱體120上。例如，襯裡130用CVD、PECVD或感應耦合型電漿CVD(ICPCVD)製程沉積，提供例如約2.2公克/立方厘米至約2.7公克/立方厘米的緻密膜。襯裡130的厚度約有1奈米至20奈米，這取決於後續形成的金屬化特徵之間的尺寸。
在具體實施例中，襯裡140為低k介電材料，例如，SiCO或SiOC，它提供低於例如SiCN或SiOCN襯裡的k值。再者，在具體實施例中，襯裡140可具有約K=4.0至約4.5的可微調介電常數，有相對優良的楊氏係數，其係彈性的度量，等於作用於物質之應力與所產生之 應變的比率。因此應瞭解，楊氏係數與薄膜的應力及附著間接相關，在薄膜分層之前(例如，SiCO/SiOC材料剝離基板)承受此力，基板可能會破裂。襯裡130對高溫也有高度耐受性，約550℃至約1100℃，以及具有高崩潰電壓。此外，在具體實施例中，襯裡130不受濕式清洗化學物影響且對其他材料的RIE及CMP製程有選擇性，從而提供氣隙18在後續製程期間的保護。
在第8圖中，低k介電材料140使用毛細凝結技術沉積，例如，CVD毛細凝結技術。在具體實施例中，CVD毛細凝結技術會產生在襯裡130之間有均勻氣隙18的多孔材料。再者，CVD毛細凝結技術會產生比襯裡135較不緻密的膜。如本文在其他態樣所述，低k介電材料140可具有相對低的介電常數，例如，約2.5-3.5，其可藉由調整形成低k介電材料16的前驅物比率來進行微調。例如，在具體實施例中，低k介電材料140可從由甲基組成的前驅物形成，該甲基與TMOS(正矽酸甲酯)及O2反應以在經受某一溫度及條件時產生交聯低k介電材料，如前述。在替代具體實施例中，低k介電材料140可為使用毛細凝結技術沉積的其他多孔材料，例如，SiOC、SiCO或其他超低k電介質(ULK)。利用毛細凝結技術，SiOC或SiCO或其他低k電介質會成為比襯裡130較不緻密的多孔層。
在第9圖中，低k介電材料140使用習知CMP製程平坦化。在柱體120上半部上因為CMP製程而暴露的襯裡130也用習知製程移除，從而暴露柱體120的材 料，例如，非晶矽。然後，通過高度選擇性蝕刻製程可移除柱體120以形成溝槽150，而不需要額外的遮罩步驟。本技藝一般技術人員應瞭解，襯裡130不受濕式清洗化學物影響且對RIE及CMP製程有選擇性，因而提供氣隙18的額外保護以及排除額外遮罩步驟的需要。
在第10圖中，視需要的覆蓋襯裡(capping liner)135(例如，SiOC或SiCO)形成於氣隙18上方，例如低k介電材料140上。覆蓋襯裡135提供作為緻密膜(例如，非多孔膜)，如同襯裡130。在具體實施例中，覆蓋襯裡135在非共形沉積製程中沉積，導致在低k介電材料140上面的材料層比溝槽150內的更厚。以此方式，在移除在溝槽150底部之材料110的後續蝕刻步驟期間，如第10圖所示，覆蓋襯裡135會仍在氣隙18之上。襯裡130與覆蓋襯裡135的組合會提供在氣隙18周圍的氣密密封。
如第11圖所示，金屬材料160沉積於該等溝槽內。金屬材料160可為用CVD製程沉積的銅。在沉積銅材料後，可進行CMP製程平坦化銅材料以形成金屬化特徵。覆蓋襯裡135對銅材料160的CMP製程有抵抗力。
上述該(等)方法係使用於積體電路晶片的製造。所得積體電路晶片可由製造者以原始晶圓形式(raw wafer form)(也就是具有多個未封裝晶片的單一晶圓)、作為裸晶粒(bare die)或已封裝的形式來銷售。在後一情形下，晶片裝在單晶片封裝體中(例如，塑膠載體(plastic carrier)，具有固定至主機板或其他更高層載體的引腳(lead))，或多 晶片封裝體中(例如，具有表面互連件(surface interconnection)或內嵌互連件(buried interconnection)任一或兩者兼具的陶瓷載體)。然後，在任一情形下，晶片與其他晶片、離散電路元件及/或其他信號處理裝置整合成為下列任一者的一部分：(a)中間產品(例如，主機板)，或(b)最終產品。該最終產品可為包括積體電路晶片的任何產品，從玩具及其他低端應用到有顯示器、鍵盤或其他輸入裝置及中央處理器的先進電腦產品不等。
為了圖解說明已呈現本揭示內容之各種具體實施例的描述，但是並非旨在窮盡或限定於所揭示的具體實施例。本技藝一般技術人員明白仍有許多修改及變體而不脫離所述具體實施例的範疇及精神。使用於本文的術語經選定成可最好地解釋具體實施例的原理、實際應用或優於在市上可找到之技術的技術改善，或使得本技藝一般技術人員能夠了解揭示於本文的具體實施例。

Claims (20)

  1. 一種結構，包含：複數條金屬線，其形成於絕緣體層上；以及介電材料，其完全填充在該等複數條金屬線的金屬線之間具有第一尺寸的空間以及在該等複數條金屬線的金屬線之間具有第二尺寸的空間提供均勻氣隙，該第一尺寸大於該第二尺寸。
  2. 如申請專利範圍第1項所述之結構，其中，該介電材料為低k介電材料。
  3. 如申請專利範圍第2項所述之結構，其中，該介電材料具有約2.5至3.5的介電常數。
  4. 如申請專利範圍第2項所述之結構，其中，藉由改變該低k介電材料的前驅物比率，可微調該氣隙。
  5. 如申請專利範圍第2項所述之結構，其中，該氣隙具有約為1的介電常數。
  6. 如申請專利範圍第2項所述之結構，其中，在該氣隙周圍的該介電材料用比該介電材料緻密的襯裡材料做襯裡。
  7. 如申請專利範圍第6項所述之結構，其中，該介電材料為多孔低k介電材料。
  8. 申請專利範圍第7項所述之結構，其中，該襯裡材料為SiCO或SiOC。
  9. 如申請專利範圍第1項所述之結構，其中，該介電材料包括有10：1：5之比率以及約5埃至10埃之多孔性的 前驅物。
  10. 一種包含可微調低k介電材料的結構，該可微調低k介電材料完全填充在基板上的金屬線之間具有第一尺寸的空間，以及在同一個沉積製程中，在該基板上的其他金屬線之間具有第二尺寸的空間形成均勻氣隙。
  11. 如申請專利範圍第10項所述之結構，其中，該低k介電材料具有約2.5至3.5的介電常數。
  12. 如申請專利範圍第10項所述之結構，其中，藉由改變該低k介電材料的前驅物比率可微調該氣隙。
  13. 如申請專利範圍第12項所述之結構，其中，該前驅物包括甲基、TMOS及氧。
  14. 如申請專利範圍第10項所述之結構，其中，在該氣隙周圍的該低k介電材料用比該低k介電材料緻密的襯裡材料做襯裡。
  15. 如申請專利範圍第13項所述之結構，其中，該低k介電材料為多孔材料。
  16. 如申請專利範圍第13項所述之結構，其中，該等前驅物具有10：1：5的比率。
  17. 如申請專利範圍第13項所述之結構，其中，該低k介電材料具有約5埃至10埃的多孔性。
  18. 一種方法，包含：在絕緣體層上形成數條金屬線；以及在該等金屬線之間沉積低k介電材料於該絕緣體層上，該沉積包含：化學氣相沉積毛細凝結技術，其 形成氣隙於以第一尺寸互相隔開的金屬線之間，以及形成完全填充於金屬線之間具有第二尺寸之空間內。
  19. 如申請專利範圍第18項所述之方法，更包含：藉由調整該低k介電材料的前驅物比率來微調氣隙填充。
  20. 如申請專利範圍第18項所述之方法，其中，該比率為10：1：5。
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