TW201828481A - 具有鰭型場效電晶體的半導體元件 - Google Patents

具有鰭型場效電晶體的半導體元件 Download PDF

Info

Publication number
TW201828481A
TW201828481A TW107110929A TW107110929A TW201828481A TW 201828481 A TW201828481 A TW 201828481A TW 107110929 A TW107110929 A TW 107110929A TW 107110929 A TW107110929 A TW 107110929A TW 201828481 A TW201828481 A TW 201828481A
Authority
TW
Taiwan
Prior art keywords
layer
region
layer pattern
semiconductor device
fin
Prior art date
Application number
TW107110929A
Other languages
English (en)
Other versions
TWI691082B (zh
Inventor
裵東一
徐康一
Original Assignee
南韓商三星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南韓商三星電子股份有限公司 filed Critical 南韓商三星電子股份有限公司
Publication of TW201828481A publication Critical patent/TW201828481A/zh
Application granted granted Critical
Publication of TWI691082B publication Critical patent/TWI691082B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本發明提供一種半導體元件。基板具有第一區域及第二區域。第一鰭及第二鰭分別在第一及第二區域中從基板突起，且在第一方向上延伸。第一堆疊層在第一鰭上在第一方向上延伸。第二堆疊層在第二鰭上在第一方向上延伸且與第一堆疊層具有相同厚度。第一主動層及第二主動層分別形成於第一及第二堆疊層上。第一閘極結構及第二閘極結構分別位於第一及第二主動層上，且在與第一方向交叉的第二方向上延伸。第一堆疊層包括形成於第一閘極結構下方的第一介電層圖案，及在第一介電層圖案的兩側上在第一方向上彼此分離的第一犧牲層圖案及第二犧牲層圖案。

Description

具有鰭型場效電晶體的半導體元件
本發明概念是關於一種具有鰭型場效電晶體（fin-type field effect transistor；FinFET）之半導體元件及其製造方法。
本申請案主張2014年7月14日在USPTO申請之美國非臨時申請案第14/330,306號之優先權，其揭露內容以全文引用的方式併入本文中。
FinFET元件指三維（three-dimensional；3D）多閘極電晶體，其中導電通道由鰭形或奈米線形矽體形成且閘極在此類矽體上形成。由於特徵尺寸變得愈來愈精細，故因短通道效應所致之高漏電流可能惡化元件效能。
根據本發明概念之一例示性實施例，半導體元件包括基板、第一鰭及第二鰭、第一堆疊層、第二堆疊層、第一主動層及第二主動層以及第一閘極結構及第二閘極結構。基板包括第一區域及第二區域。第一鰭及第二鰭分別在所述第一區域及所述第二區域中從所述基板突起，且在第一方向上延伸。第一堆疊層在所述第一鰭上在所述第一方向上延伸。第二堆疊層在所述第二鰭上在所述第一方向上延伸且與所述第一堆疊層具有相同厚度。第一主動層及第二主動層分別形成於所述第一堆疊層及所述第二堆疊層上。第一閘極結構及第二閘極結構分別位於所述第一主動層及所述第二主動層上，且在與所述第一方向交叉的第二方向上延伸。所述第一堆疊層包括形成於所述第一閘極結構下方的第一介電層圖案，以及在所述第一介電層圖案的兩側上在所述第一方向上彼此分離的第一犧牲層圖案及第二犧牲層圖案。
根據本發明概念之一例示性實施例，半導體元件包括基板、第一鰭及第二鰭、第一堆疊層、第二堆疊層、第一主動層及第二主動層以及第一閘極結構及第二閘極結構。基板包括第一區域及第二區域。第一鰭及第二鰭分別在所述第一區域及所述第二區域中從所述基板突起，且在第一方向上延伸。第一堆疊層在所述第一鰭上在所述第一方向上延伸。第二堆疊層在所述第二鰭上在所述第一方向上延伸且與所述第一堆疊層具有相同厚度。第一主動層及第二主動層分別形成於所述第一堆疊層及所述第二堆疊層上。第一閘極結構及第二閘極結構分別位於所述第一主動層及所述第二主動層上，且在與所述第一方向交叉的第二方向上延伸。所述第一堆疊層包括第一部分及第二部分，所述第一部分位於所述第一閘極結構下方，所述第二部分與所述第一部分在所述第一方向彼此分開。所述第二堆疊層包括第三部分及第四部分，所述第三部分位於所述第二閘極結構下方，所述第四部分與所述第三部分在所述第一方向彼此分開。所述第一部分及所述第三部分彼此相同，所述第二部分及所述第四部分不同。
下文將參考附圖詳細描述本發明概念之例示性實施例。然而，本發明概念可以不同形式實施且不應解釋為限於本文所闡述之實施例。在圖式中，出於明晰之目的，可誇示層及區域之厚度。亦應瞭解，當稱元件在另一元件或基板「上」時，其可直接在另一元件或基體上，或亦可存在介入層。亦將瞭解，當稱元件「耦接於」或「連接於」另一元件時，其可直接耦接於或連接於該另一元件，或亦可存在介入元件。在本說明書及圖式中，相同圖式元件符號可指相同元件。
圖1為說明本發明概念之一例示性實施例的半導體元件的透視圖。圖2及圖3分別為對應於圖1之線A-A及B-B的橫截面視圖。
參看圖1至圖3，半導體元件可包含基板100、鰭結構FS、犧牲層圖案102、主動層圖案104、源極/汲極結構128、介電層圖案140以及閘電極結構150。
在下文中，將關於鰭型場效電晶體（FinFET）詳細描述根據本發明概念之例示性實施例的半導體元件，但不限於鰭型場效電晶體（FinFET）。
基板100可包含塊狀矽基板或矽絕緣體（silicon-on-insulator；SOI）基板。基板100可包含矽（Si）、鍺（Ge）、矽鍺（SiGe）、銻化銦（InSb）、碲化鉛（PbTe）、砷化銦（InAs）、磷化銦（InP）、砷化鎵（GaAs）及/或銻化鎵（GaSb）。
基板100亦可包含在基底基板(base substrate)上形成之磊晶層。若藉由使用磊晶層形成作用鰭圖案，則磊晶層可包含矽（Si）或鍺（Ge）。磊晶層亦可包含化合物半導體，例如第4族-第4族化合物半導體或第3族-第5族化合物半導體。第4族-第4族化合物半導體可為具有碳（C）、矽（Si）、鍺（Ge）以及錫（Sn）中之至少兩種材料的二元化合物或三元化合物。第3族-第5族化合物半導體可為具有鋁（Al）、鎵（Ga）、銦（In）、磷（P）、砷（As）以及銻（Sb）中之至少兩種材料的二元化合物、三元化合物或四元化合物。
鰭結構FS可在基板100上形成且自基板100向第一方向（Z軸）突出。根據本發明概念之一例示性實施例，鰭結構FS可由與基板100相同之材料形成。或者，鰭結構FS可包含與基板100不同之材料。或者，鰭結構FS可藉由部分蝕刻基板100形成。
鰭結構FS可具有底部寬度較大之楔形形狀或頂部及底部之寬度實質上相同之矩形形狀。鰭結構FS之頂部邊緣可具有圓形形狀。
元件隔離結構110可在基板100上形成且可覆蓋鰭結構FS之側壁。元件隔離結構110可由絕緣層形成，例如氧化矽層、氮化矽層或氮氧化矽層，但不限於所述層。
或者，元件隔離結構110可具有淺溝槽隔離（shallow-trench-isolation；STI）結構或深溝槽隔離（deep-trench-isolation；DTI）結構。
犧牲層圖案102可在鰭結構FS上形成。犧牲層圖案120可包含半導體材料，例如矽鍺（SiGe）。若犧牲層圖案102包含矽鍺（SiGe），則犧牲層圖案102中鍺（Ge）之比例可高於犧牲層圖案102中矽（Si）之比例以提高犧牲層圖案102相對於具有較低鍺（Ge）比例之其他層的蝕刻選擇性。犧牲層圖案102可沿第二方向（Y軸）分為左部及右部。
介電層圖案140可在犧牲層圖案102之左部與右部之間形成。
具有第一部分及第二部分之主動層圖案104可在犧牲層圖案102及介電層圖案140上形成。主動層圖案104之第一部分可在介電層圖案140上形成且主動層圖案104之第二部分可在犧牲層圖案102上形成。主動層圖案104可沿第二方向（Y軸）延伸。主動層圖案104可包含藉由使用磊晶生長製程形成之矽層或第3族-第5族化合物半導體。主動層圖案104可由與鰭結構FS實質上相同之材料形成。主動層圖案104之第一部分可作為鰭型場效電晶體（FinFET）之通道區域，且主動層圖案104之第二部分可作為鰭型場效電晶體（FinFET）之源極/汲極區域的一部分。
閘電極結構150可在主動層圖案140上形成。閘電極結構150可橫越(cross over)主動層圖案104之第一部分且沿第三方向（X軸）延伸。閘電極結構150可包含閘極介電層152、功函數控制層154以及金屬閘電極層156。
間隙壁114可分別在閘電極結構150之兩個側壁處形成。間隙壁114可由絕緣層形成，例如氧化矽層、氮化矽層或氮氧化矽層。在此情形下，如圖2中所示，閘極介電層152可在主動層圖案104上形成且向上沿間隙壁114之內部側壁延伸。閘極介電層152可包含高k介電層，例如氧化鉿層、氧化鋁層、氧化鋯層或氧化鉭層。
界面層可在閘極介電層152與主動層圖案104之間形成。界面層可由介電常數小於9之低k介電層形成。舉例而言，界面層可由氧化矽層、氮氧化矽層或其混合物形成。
功函數控制層154可在閘極介電層152上形成。功函數控制層154可沿金屬閘電極層156及間隙壁114之側壁沿第一方向（Z軸）延伸。功函數控制層154可控制鰭型場效電晶體之功函數。
若鰭型場效電晶體為P型金屬氧化物半導體（P-type Metal Oxide Semiconductor；PMOS）電晶體，則功函數控制層154可包含p型功函數控制層，例如氮化鈦（TiN）、氮化鉭（TaN）或其混合物。
金屬閘電極層156可在功函數控制層154上形成。金屬閘電極層156可包含鋁（Al）、鎢（W）或其混合物。
源極/汲極結構128可在主動層圖案104之第二部分及閘電極結構150之兩側形成。源極/汲極結構128可藉由使用選擇性磊晶生長製程形成且可覆蓋主動層圖案104之側壁的一部分，但不限於此。
或者，源極/汲極結構128可在無任何磊晶層之情況下藉由使用離子植入製程向主動層圖案104中注入雜質而在其中形成。舉例而言，若鰭型場效電晶體為PMOS電晶體，則源極/汲極結構128可包含p型雜質。
層間介電層130可在元件隔離結構110上形成。層間介電層130可覆蓋犧牲層圖案102及源極/汲極結構128。
根據本發明概念之一例示性實施例，介電層圖案140可在主動層圖案104之第一部分下形成。相較於平面型場效電晶體，介電層圖案140可用來減少鰭型場效電晶體之漏電流。從而可提高鰭型場效電晶體之可靠性及效能。
圖4為說明根據本發明概念之一例示性實施例的半導體元件的橫截面視圖。為便於描述，省略對於以上實施例之相同元件的描述。
參看圖4，基板100可包含第一區域I及第二區域II。第一鰭型場效電晶體可在第一區域I中形成且第二鰭型場效電晶體可在第二區域II中形成。
第一鰭型場效電晶體可與關於圖2所述之鰭型場效電晶體實質上相同。因此，將省略第一鰭型場效電晶體之詳細描述以簡化說明。
第二區域II中所形成之第二鰭型場效電晶體可包含鰭結構FS、犧牲層圖案240、主動層圖案204、源極/汲極結構228以及閘電極結構250。
主動層圖案204、源極/汲極結構228以及閘電極結構250可與關於圖2所述之相應元件實質上相同，且因此本文將省略其詳細描述。
第二區域II中所形成之第二鰭型場效電晶體的犧牲層圖案240可由絕緣膜形成。因此，絕緣膜可不僅在源極/汲極區域228下形成而且在閘電極結構250下形成。絕緣膜可沿第二方向（Y軸）延伸。
第一區域I中形成之第一鰭型場效電晶體與第二區域II中形成之第二鰭型場效電晶體可彼此具有不同導電類型。舉例而言，第一鰭型場效電晶體可為PMOS電晶體，且第二鰭型場效電晶體可為N型金屬氧化物半導體（N-type Metal Oxide Semiconductor；NMOS）電晶體。或者，第一與第二鰭型場效電晶體可彼此具有相同導電類型。
第一區域I中形成之犧牲層圖案102可包含與第二區域II中形成之犧牲層圖案240中所安置之材料不同的材料。
圖5及圖6為說明本發明概念之一例示性實施例的半導體元件的橫截面視圖。
參看圖5及圖6，基板100可包含第一區域I及第二區域II。第一鰭型電晶體可在第一區域I中形成，且第二鰭型電晶體可在第二區域II中形成。
第一鰭型場效電晶體可與圖2之鰭型場效電晶體實質上相同。本文將省略其詳細描述。
第二區域II中形成之第二鰭型場效電晶體可包含鰭結構FS、犧牲層圖案302、主動層圖案304、源極/汲極結構328、閘電極結構350、間隙壁314以及層間介電層330。
犧牲層圖案302、主動層圖案304、源極/汲極結構328、間隙壁314以及層間介電層330與關於圖2及圖3所述之相應元件實質上相同，且因此本文將省略其詳細描述。
第二區域II中形成之第二鰭型電晶體的閘電極結構350可包圍主動層圖案304之一部分。
圖7為說明根據本發明概念之一例示性實施例的半導體元件的橫截面視圖。
參看圖7，基板100可包含第一區域I及第二區域II。第一鰭型電晶體TR1可在第一區域I中形成，且第二鰭型電晶體TR2可在第二區域II中形成。
第一區域I中形成之第一鰭型場效電晶體TR1可與圖2之鰭型場效電晶體實質上相同。舉例而言，圖7中第一鰭型場效電晶體TR1之主動層圖案104a、源極/汲極結構128a、閘電極結構150a、間隙壁114a以及層間介電層130a可與關於圖2描述之鰭型場效電晶體之其相應元件實質上相同。
第二區域II中形成之第二鰭型場效電晶體TR2可與關於圖2描述之鰭型場效電晶體實質上相同。舉例而言，第二鰭型場效電晶體TR2之主動層圖案104b、源極/汲極結構128b、閘電極結構150b、間隙壁114b以及層間介電層130b可與關於圖2描述之相應元件實質上相同。然而，第一區域I中形成之犧牲層圖案102a之第一鍺濃度可與第二區域II中形成之犧牲層圖案102b之第二鍺濃度不同。
第一區域I中形成之第一鰭型場效電晶體TR1與第二區域II中形成之第二鰭型場效電晶體TR2可彼此具有不同導電類型。舉例而言，第一鰭型場效電晶體TR1可為PMOS電晶體，且第二鰭型場效電晶體TR2可為NMOS電晶體。在此情形下，第一鰭型場效電晶體之第一鍺濃度可大於第二鰭型場效電晶體之第二鍺濃度。
第一區域I中形成之犧牲層圖案102a可包含與第二區域II中形成之犧牲層圖案102b中所安置之材料不同的材料。
圖8至圖20為說明製造根據本發明概念之一例示性實施例的半導體元件的方法的橫截面視圖。圖16為對應於圖15之線C-C的橫截面視圖，圖17為對應於圖15之線D-D的橫截面視圖，圖19為對應於圖18之線E-E的橫截面視圖且圖20為對應於圖18之線F-F的橫截面視圖。
參看圖8，犧牲層102可藉由使用磊晶生長製程在基板100上形成。犧牲層可包含半導體材料，例如矽鍺（SiGe）。主動層104可藉由使用另一磊晶生長製程在犧牲層102上形成。主動層104可包含矽（Si）。
參看圖9，可連續蝕刻主動層104、犧牲層102以及基板100以形成鰭結構FS、犧牲層圖案102以及主動層圖案104。
參看圖10，元件隔離結構110可在基板100上形成。元件隔離結構110可覆蓋鰭結構FS之側壁。
或者，鰭結構FS、犧牲層圖案102以及主動層圖案104可藉由使用多種磊晶生長方法在矽絕緣體（SOI）基板上形成。舉例而言，包含矽（Si）之第一磊晶層可在上面具有絕緣層之基板上形成，包含矽鍺（SiGe）之第二磊晶層可在第一磊晶層上形成，且包含矽（Si）之第三磊晶層可在第二磊晶層上形成。可使用遮蔽圖案連續蝕刻第三、第二以及第一磊晶層以形成主動層圖案104、犧牲層圖案102以及鰭結構，其均在矽絕緣體（SOI）基板上形成。
參看圖11，虛設閘極結構120可在主動層圖案104上形成。虛設閘極結構120可橫越主動層圖案104且沿第三方向（X軸）延伸。虛設閘極結構120可覆蓋主動層圖案104之側壁及犧牲層圖案102之側壁。虛設閘極結構120可包含虛設閘極介電層122、虛設閘極層124以及硬式遮罩126。
虛設閘極介電層122可包含氧化矽層，虛設閘極層124可包含聚矽層，且硬式遮罩126可包含氮化矽層。
參看圖12，絕緣層可在虛設閘極結構120上形成。可使用各向異性蝕刻製程蝕刻絕緣層以在虛設閘極結構120之側壁上形成間隙壁114。源極/汲極結構128可在虛設閘極結構120之兩側形成。源極/汲極結構128可使用磊晶生長製程在主動層圖案104上形成。源極/汲極結構128可覆蓋犧牲層圖案102之側壁的一部分及主動層圖案104之側壁的一部分。磊晶生長製程可在使主動層圖案104之上部凹入(recessing)之後進行。
或者，源極/汲極結構128可使用離子植入製程而非上述磊晶生長製程形成。舉例而言，可將雜質注入安置在虛設閘極結構120之兩側的主動層圖案中以形成源極/汲極結構128。
參看圖13，層間介電層130可在源極/汲極結構128及虛設閘極結構120上形成。可藉由使用平坦化製程（例如化學機械拋光（chemical mechanical polish；CMP）製程）平坦化層間介電層130以暴露虛設閘極結構120之上表面。可在平坦化製程後或期間移除硬式遮罩126。層間介電層130可包含氧化矽層或氮氧化矽層，但不限於所述層。
參看圖14，可移除虛設閘極層124及虛設閘極介電層122以暴露主動層圖案104之一部分及犧牲層圖案102之側壁的一部分。舉例而言，可使用乾式蝕刻製程移除虛設閘極層124，且可使用濕式蝕刻製程移除虛設閘極介電層122，但不限於所述製程。
參看圖15至圖17，可使用選擇性蝕刻製程移除犧牲層圖案102之經暴露部分。
包含矽鍺（SiGe）之犧牲層圖案102可具有相對於由矽（Si）形成之主動層圖案的蝕刻選擇性。舉例而言，可使用鹽酸（HCl）移除經暴露的犧牲層圖案102以形成通孔103，所述通孔103安置在主動層圖案104與元件隔離結構110之間。
參看圖18至圖20，介電層圖案140可在通孔103中形成。介電層圖案140可在經分隔的犧牲層圖案102之間形成。
再次參看圖1至圖3，閘極介電層152可在主動層圖案104之經暴露的上表面及側壁上形成。閘極介電層152可在介電層圖案140之側壁上進一步形成。
功函數控制層154可在閘極介電層152上形成，且金屬閘電極層156可在功函數控制層154上形成。
圖21為說明根據本發明概念之一例示性實施例的半導體元件的方塊圖。圖22為說明根據本發明概念之一例示性實施例的半導體元件的方塊圖。
參看圖21，半導體元件13可包含邏輯區域410及靜態隨機存取記憶體（static random access memory；SRAM）區域420。第一電晶體411可安置於邏輯區域410中，且第二電晶體421可安置於SRAM區域420中。第一電晶體411與第二電晶體421之類型可彼此不同。舉例而言，分別地，圖7之第一鰭型場效電晶體TR1可應用於第一電晶體411，且圖7之第二鰭型場效電晶體TR2可應用於第二電晶體421。或者，第一電晶體411與第二電晶體421之類型可相同。舉例而言，圖7之第一鰭型場效電晶體TR1可應用於第一電晶體411及第二電晶體421。
或者，SRAM區域可替換為動態隨機存取記憶體（Dynamic Random Access Memory；DRAM）區域、磁阻式隨機存取記憶體（Magnetoresistive Random Access Memory；MRAM）區域、電阻式隨機存取記憶體（Resistive Random Access Memory；RRAM）區域或相變隨機存取記憶體（Phase-Change Random Access Memory；PRAM）區域。或者，除SRAM區域及邏輯區域之外，半導體元件亦可包含DRAM區域、MRAM區域、RRAM區域以及PRAM區域中之至少一者。
參看圖22，半導體元件14可包含邏輯區域410，其包含第三電晶體412及第四電晶體422。第三電晶體412與第四電晶體422之類型可彼此不同。舉例而言，分別地，圖7之第一鰭型場效電晶體TR1可應用於第三電晶體412，且圖7之第二鰭型場效電晶體TR2可應用於第四電晶體422。或者，第三電晶體412與第四電晶體422之類型可相同。舉例而言，圖7之第一鰭型場效電晶體TR1可應用於第三電晶體412及第四電晶體422。
圖23為包含根據本發明概念之一例示性實施例的半導體元件的系統晶片（SoC）的系統方塊圖。
參看圖23，系統晶片1000可包含應用程式處理器1001及DRAM元件1060。應用程式處理器1001可包含中央處理單元1010、多媒體系統1020、匯流排1030、記憶體系統1040以及周邊電路1050。
中央處理單元1010可執行驅動系統晶片1000所必需之操作。多媒體系統1020可包含三維引擎模組、視訊編碼解碼器、顯示系統、攝影系統或後處理器。中央處理單元1010、多媒體系統1020、記憶體系統1040及周邊電路1050可經由匯流排1030彼此通信。匯流排1030可具有多層結構，例如多層先進高效能匯流排（advanced high-performance bus；AHB）或多層先進可擴展介面（advanced extensible interface；AXI）。
當應用程式處理器1001與外部元件連接時，記憶體系統1040可提供執行高速操作所必需之環境。外部元件可為DRAM元件。周邊電路1050可使系統晶片1000與外部元件連接。在此情形下，外部元件可為主板。如圖23中所示，DRAM元件1060可安置在應用程式處理器1001外。DRAM元件1060可與應用程式處理器1001一起封裝以形成具有疊層封裝（Package on Package；PoP）之封裝類型。
系統晶片1000之至少一個元件可包含根據本發明概念之一例示性實施例的半導體元件。
圖24為包含根據本發明概念之一例示性實施例的半導體元件的電子系統的方塊圖。
參看圖24，電子系統1100可包含控制器1110、輸入/輸出元件1120、記憶體元件1130、介面1140以及匯流排1150。控制器1110、輸入/輸出元件1120、記憶體元件1130以及介面1140可經由匯流排1150彼此通信。匯流排1150可對應於資料傳遞可經過之信號路徑。
控制器1110可包含微處理器、數位信號處理器、微控制器或可控制執行程式之類似元件。輸入/輸出元件1120可包含小鍵盤、鍵盤或顯示器。記憶體元件1130可不僅儲存用於執行控制器1110之程式碼或資料而且保存由控制器1110執行之資料。記憶體元件1130可包含根據本發明概念之一例示性實施例的半導體元件。
系統1100可應用於如下產品，其包含個人數位助理（personal digital assistant；PDA）、攜帶型電腦、平板電腦、無線電話、行動電話、數位音樂播放器或記憶卡。
圖25至圖27為包含根據本發明概念之例示性實施例的半導體元件的數個電子產品。圖25為說明個人平板電腦1200之視圖，圖26為說明筆記型電腦1300之視圖，且圖27為說明智慧型手機1400之視圖。根據本發明概念之至少一個例示性實施例的半導體元件可應用於個人平板電腦1200、筆記型電腦1300或智慧型手機1400。
儘管本發明概念已參考其例示性實施例展示及描述，但於本領域具有通常知識者應顯而易見，在不背離如由以下申請專利範圍所定義之本發明概念之精神及範疇的情況下可在其中進行形式及細節之各種改變。
13‧‧‧半導體元件
14‧‧‧半導體元件
100‧‧‧基板
102‧‧‧犧牲層
103‧‧‧通孔
104‧‧‧主動層
104a‧‧‧主動層圖案
104b‧‧‧主動層圖案
110‧‧‧元件隔離結構
114‧‧‧間隙壁
114a‧‧‧間隙壁
114b‧‧‧間隙壁
120‧‧‧虛設閘極結構
122‧‧‧虛設閘極介電層
124‧‧‧虛設閘極層
126‧‧‧硬式遮罩
128‧‧‧源極/汲極結構
128a‧‧‧源極/汲極結構
128b‧‧‧源極/汲極結構
130‧‧‧層間介電層
130a‧‧‧層間介電層
130b‧‧‧層間介電層
140‧‧‧介電層圖案
150‧‧‧閘電極結構
150a‧‧‧閘電極結構
150b‧‧‧閘電極結構
152‧‧‧閘極介電層
154‧‧‧功函數控制層
156‧‧‧金屬閘電極層
204‧‧‧主動層圖案
228‧‧‧源極/汲極結構
240‧‧‧犧牲層圖案
250‧‧‧閘電極結構
302‧‧‧犧牲層圖案
304‧‧‧主動層圖案
314‧‧‧間隙壁
328‧‧‧源極/汲極結構
330‧‧‧層間介電層
350‧‧‧閘電極結構
410‧‧‧邏輯區域
411‧‧‧第一電晶體
412‧‧‧第三電晶體
420‧‧‧靜態隨機存取記憶體區域
421‧‧‧第二電晶體
422‧‧‧第四電晶體
1000‧‧‧SoC
1001‧‧‧應用程式處理器
1010‧‧‧中央處理單元
1020‧‧‧多媒體系統
1030‧‧‧匯流排
1040‧‧‧記憶體系統
1050‧‧‧周邊電路
1060‧‧‧DRAM元件
1100‧‧‧電子系統
1110‧‧‧控制器
1120‧‧‧輸入/輸出元件
1130‧‧‧記憶體元件
1140‧‧‧介面
1150‧‧‧匯流排
1200‧‧‧個人平板電腦
1300‧‧‧筆記型電腦
1400‧‧‧智慧型手機
FS‧‧‧鰭結構
I‧‧‧第一區域
II‧‧‧第二區域
TR1‧‧‧第一鰭型電晶體
TR2‧‧‧第二鰭型電晶體
本發明概念之這些及其他特徵將藉由參考附圖詳細地描述其例示性實施例而變得更顯而易見，其中： 圖1為說明根據本發明概念之一例示性實施例的半導體元件的透視圖。 圖2為對應於圖1之線A-A之橫截面視圖。 圖3為對應於圖1之線B-B之橫截面視圖。 圖4為說明根據本發明概念之一例示性實施例的半導體元件的橫截面視圖。 圖5及圖6為說明本發明概念之一例示性實施例的半導體元件的橫截面視圖。 圖7為說明根據本發明概念之一例示性實施例的半導體元件的橫截面視圖。 圖8至圖20為說明製造根據本發明概念之一例示性實施例的半導體元件的方法的橫截面視圖。 圖21為說明根據本發明概念之一例示性實施例的半導體元件的方塊圖。 圖22為說明根據本發明概念之一例示性實施例的半導體元件的方塊圖。 圖23為包含根據本發明概念之一例示性實施例的半導體元件的系統晶片（System on Chip；SoC）的系統方塊圖。 圖24為包含根據本發明概念之一例示性實施例的半導體元件的電子系統的方塊圖。 圖25至圖27為包含根據本發明概念之例示性實施例的半導體元件的數種電子產品。

Claims (20)

  1. 一種半導體元件，包括： 基板，包括第一區域及第二區域； 第一鰭及第二鰭，分別在所述第一區域及所述第二區域中從所述基板突起，且在第一方向上延伸； 第一堆疊層，在所述第一鰭上在所述第一方向上延伸； 第二堆疊層，在所述第二鰭上在所述第一方向上延伸且與所述第一堆疊層具有相同厚度； 第一主動層及第二主動層，分別形成於所述第一堆疊層及所述第二堆疊層上；以及 第一閘極結構及第二閘極結構，分別位於所述第一主動層及所述第二主動層上，且在與所述第一方向交叉的第二方向上延伸， 其中所述第一堆疊層包括形成於所述第一閘極結構下方的第一介電層圖案，以及在所述第一介電層圖案的兩側上在所述第一方向上彼此分離的第一犧牲層圖案及第二犧牲層圖案。
  2. 如申請專利範圍第1項所述的半導體元件，其中所述第二堆疊層形成為單層。
  3. 如申請專利範圍第2項所述的半導體元件，其中所述第二堆疊層包括第二介電層圖案。
  4. 如申請專利範圍第1項所述的半導體元件，其中所述第一犧牲層圖案及所述第二犧牲層圖案包括SiGe。
  5. 如申請專利範圍第4項所述的半導體元件，其中所述第一區域為p型電晶體區域，以及所述第二區域為n型電晶體區域。
  6. 如申請專利範圍第1項所述的半導體元件，其中所述第二閘極結構環繞所述第二主動層的上表面、下表面以及所述第二方向上的側表面。
  7. 如申請專利範圍第6項所述的半導體元件，其中所述第二堆疊層包括在所述第一方向上被所述第二閘極結構分離的第三犧牲層圖案及第四犧牲層圖案。
  8. 如申請專利範圍第1項所述的半導體元件，其中所述第二堆疊層包括形成於所述第二閘極結構下方的第三介電層圖案，以及在所述第三介電層圖案的兩側上在所述第一方向上彼此分離的第五犧牲層圖案及第六犧牲層圖案。
  9. 如申請專利範圍第8項所述的半導體元件，其中所述第一犧牲層圖案及所述第二犧牲層圖案包括半導體材料的第一濃度，以及所述第五犧牲層圖案及所述第六犧牲層圖案包括所述半導體材料的第二濃度。
  10. 如申請專利範圍第9項所述的半導體元件，其中所述半導體材料包括SiGe。
  11. 如申請專利範圍第9項所述的半導體元件，其中所述第二濃度不同於所述第一濃度。
  12. 如申請專利範圍第11項所述的半導體元件，其中所述第二濃度小於所述第一濃度。
  13. 如申請專利範圍第12項所述的半導體元件，其中所述第一區域為p型電晶體區域，以及所述第二區域為n型電晶體區域。
  14. 如申請專利範圍第11項所述的半導體元件，其中所述第一區域所經歷的壓縮應力的強度不同於所述第二區域所經歷的壓縮應力的強度。
  15. 一種半導體元件，包括： 基板，包括第一區域及第二區域； 第一鰭及第二鰭，分別在所述第一區域及所述第二區域中從所述基板突起，且在第一方向上延伸； 第一堆疊層，在所述第一鰭上在所述第一方向上延伸； 第二堆疊層，在所述第二鰭上在所述第一方向上延伸且與所述第一堆疊層具有相同厚度； 第一主動層及第二主動層，分別形成於所述第一堆疊層及所述第二堆疊層上；以及 第一閘極結構及第二閘極結構，分別位於所述第一主動層及所述第二主動層上，且在與所述第一方向交叉的第二方向上延伸， 其中所述第一堆疊層包括第一部分及第二部分，所述第一部分位於所述第一閘極結構下方，所述第二部分與所述第一部分在所述第一方向彼此分開， 其中所述第二堆疊層包括第三部分及第四部分，所述第三部分位於所述第二閘極結構下方，所述第四部分與所述第三部分在所述第一方向彼此分開， 其中所述第一部分及所述第三部分彼此相同， 其中所述第二部分及所述第四部分不同。
  16. 如申請專利範圍第15項所述的半導體元件，其中所述第一部分及所述第三部分包括介電層圖案。
  17. 如申請專利範圍第15項所述的半導體元件，其中所述第二部分包括犧牲層圖案，以及所述第四部分包括介電層圖案。
  18. 如申請專利範圍第15項所述的半導體元件，其中所述第二部分及所述第四部分包括犧牲層圖案，其中所述第二部分及所述第四部分各自包括不同濃度的半導體材料。
  19. 如申請專利範圍第18項所述的半導體元件，其中所述半導體材料包括SiGe。
  20. 如申請專利範圍第18項所述的半導體元件，其中所述第二部分中的所述半導體材料的濃度大於所述第四部分中的所述半導體材料的濃度。
TW107110929A 2014-07-14 2014-12-17 具有鰭型場效電晶體的半導體元件 TWI691082B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/330,306 US9735153B2 (en) 2014-07-14 2014-07-14 Semiconductor device having fin-type field effect transistor and method of manufacturing the same
US14/330,306 2014-07-14

Publications (2)

Publication Number Publication Date
TW201828481A true TW201828481A (zh) 2018-08-01
TWI691082B TWI691082B (zh) 2020-04-11

Family

ID=55068174

Family Applications (2)

Application Number Title Priority Date Filing Date
TW107110929A TWI691082B (zh) 2014-07-14 2014-12-17 具有鰭型場效電晶體的半導體元件
TW103143980A TWI641144B (zh) 2014-07-14 2014-12-17 具有鰭型場效電晶體的半導體元件及其製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW103143980A TWI641144B (zh) 2014-07-14 2014-12-17 具有鰭型場效電晶體的半導體元件及其製造方法

Country Status (3)

Country Link
US (5) US9735153B2 (zh)
KR (1) KR102236557B1 (zh)
TW (2) TWI691082B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9735153B2 (en) * 2014-07-14 2017-08-15 Samsung Electronics Co., Ltd. Semiconductor device having fin-type field effect transistor and method of manufacturing the same
US9425259B1 (en) * 2015-07-17 2016-08-23 Samsung Electronics Co., Ltd. Semiconductor device having a fin
US9735274B2 (en) 2015-11-20 2017-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including a stacked wire structure
US9960275B1 (en) * 2016-10-28 2018-05-01 Applied Materials, Inc. Method of fabricating air-gap spacer for N7/N5 finFET and beyond
US10164106B2 (en) * 2016-12-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US10276680B2 (en) * 2017-07-18 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Gate feature in FinFET device
DE112017008312T5 (de) * 2017-12-29 2020-09-17 Intel Corporation Heterogene ge/iii-v-cmos-transistorstrukturen
US10672983B2 (en) * 2018-06-27 2020-06-02 International Business Machines Corporation Compact resistive random access memory integrated with a pass gate transistor
US11075269B2 (en) 2018-11-30 2021-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11456368B2 (en) * 2019-08-22 2022-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with hard mask layer over fin structure and method for forming the same
US11081489B2 (en) * 2019-11-11 2021-08-03 Xia Tai Xin Semiconductor (Qing Dao) Ltd. Semiconductor structure and method for fabricating the same
US11502087B2 (en) * 2020-01-21 2022-11-15 Xia Tai Xin Semiconductor (Qing Dao) Ltd. Semiconductor structure and method for fabricating the same
CN113224030B (zh) * 2020-01-21 2023-05-12 夏泰鑫半导体(青岛)有限公司 半导体器件及其制造方法
US11594637B2 (en) * 2020-03-27 2023-02-28 Intel Corporation Gate-all-around integrated circuit structures having fin stack isolation
CN113611743B (zh) 2021-06-11 2022-06-07 联芯集成电路制造(厦门)有限公司 半导体晶体管结构及其制作方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100464268B1 (ko) 2003-02-04 2005-01-03 동부아남반도체 주식회사 반도체 소자 제조 방법
WO2004073044A2 (en) 2003-02-13 2004-08-26 Massachusetts Institute Of Technology Finfet device and method to make same
US7078298B2 (en) 2003-05-20 2006-07-18 Sharp Laboratories Of America, Inc. Silicon-on-nothing fabrication process
KR100487567B1 (ko) 2003-07-24 2005-05-03 삼성전자주식회사 핀 전계효과 트랜지스터 형성 방법
KR20050055978A (ko) * 2003-12-09 2005-06-14 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 형성 방법
US7335945B2 (en) * 2003-12-26 2008-02-26 Electronics And Telecommunications Research Institute Multi-gate MOS transistor and method of manufacturing the same
US7223994B2 (en) * 2004-06-03 2007-05-29 International Business Machines Corporation Strained Si on multiple materials for bulk or SOI substrates
KR100555569B1 (ko) * 2004-08-06 2006-03-03 삼성전자주식회사 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법
US7960791B2 (en) 2005-06-24 2011-06-14 International Business Machines Corporation Dense pitch bulk FinFET process by selective EPI and etch
KR100739658B1 (ko) * 2006-07-03 2007-07-13 삼성전자주식회사 반도체 장치의 제조 방법.
US7674669B2 (en) * 2007-09-07 2010-03-09 Micron Technology, Inc. FIN field effect transistor
US7842982B2 (en) 2008-01-29 2010-11-30 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US8264032B2 (en) 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
KR20110078883A (ko) 2009-12-31 2011-07-07 주식회사 동부하이텍 Ｓｏｎ의 제조방법
US8034677B2 (en) 2010-02-25 2011-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated method for forming high-k metal gate FinFET devices
US8609495B2 (en) * 2010-04-08 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid gate process for fabricating finfet device
US8653610B2 (en) * 2010-04-21 2014-02-18 International Business Machines Corporation High performance non-planar semiconductor devices with metal filled inter-fin gaps
US8859389B2 (en) 2011-01-28 2014-10-14 Kabushiki Kaisha Toshiba Methods of making fins and fin field effect transistors (FinFETs)
US8455308B2 (en) 2011-03-16 2013-06-04 International Business Machines Corporation Fully-depleted SON
WO2013095652A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Uniaxially strained nanowire structure
US9147765B2 (en) * 2012-01-19 2015-09-29 Globalfoundries Inc. FinFET semiconductor devices with improved source/drain resistance and methods of making same
US8969149B2 (en) * 2013-05-14 2015-03-03 International Business Machines Corporation Stacked semiconductor nanowires with tunnel spacers
KR102069609B1 (ko) * 2013-08-12 2020-01-23 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9093302B2 (en) * 2013-11-13 2015-07-28 Globalfoundries Inc. Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices
US9136332B2 (en) * 2013-12-10 2015-09-15 Taiwan Semiconductor Manufacturing Company Limited Method for forming a nanowire field effect transistor device having a replacement gate
US9735153B2 (en) 2014-07-14 2017-08-15 Samsung Electronics Co., Ltd. Semiconductor device having fin-type field effect transistor and method of manufacturing the same
US9443978B2 (en) * 2014-07-14 2016-09-13 Samsung Electronics Co., Ltd. Semiconductor device having gate-all-around transistor and method of manufacturing the same

Also Published As

Publication number Publication date
TWI641144B (zh) 2018-11-11
US20160013186A1 (en) 2016-01-14
TWI691082B (zh) 2020-04-11
KR20160008441A (ko) 2016-01-22
KR102236557B1 (ko) 2021-04-06
US9735153B2 (en) 2017-08-15
US20200203340A1 (en) 2020-06-25
TW201603277A (zh) 2016-01-16
US20170271330A1 (en) 2017-09-21
US20180158819A1 (en) 2018-06-07
US20220045059A1 (en) 2022-02-10
US11177260B2 (en) 2021-11-16
US9905559B2 (en) 2018-02-27

Similar Documents

Publication Publication Date Title
US11177260B2 (en) Semiconductor device having fin-type field effect transistor and method of manufacturing the same
US10128246B2 (en) Semiconductor devices including an isolation layer on a fin and methods of forming semiconductor devices including an isolation layer on a fin
US9653361B2 (en) Semiconductor device having gate-all-around transistor and method of manufacturing the same
US9923058B2 (en) Semiconductor device having a fin
TWI600160B (zh) 高電壓電晶體與低電壓非平面電晶體的單體集成
US9698268B2 (en) Methods of forming semiconductor devices, including forming a semiconductor material on a fin, and related semiconductor devices
TWI540721B (zh) 具有多層順應基底之非平面半導體裝置
CN106170867B (zh) 用于垂直型半导体器件的选择性再生长顶部接触部
TWI767809B (zh) 半導體結構及系統晶片（ＳｏＣ）積體電路及其製造方法
KR20160079598A (ko) 반도체 장치 및 그 제조 방법
CN113851473A (zh) 堆叠叉片晶体管
TW201721806A (zh) 混合三閘極和奈米線ｃｍｏｓ裝置架構
TWI544624B (zh) 具有最大化柔度及自由表面鬆弛的鍺及iii-v族通道半導體裝置及其製造方法
US10008493B2 (en) Semiconductor device and method of fabricating the same
TW202416450A (zh) 積體電路及其製造方法
KR20150088701A (ko) 반도체 장치 및 그 제조 방법