TW201824740A - Amplifier circuit - Google Patents

Abstract

Disclosed is an amplifier circuit including a first amplifier circuit and at least one second amplifier circuit. The second amplifier circuit is connected to the first amplifier circuit in serial to form a multi-stage amplifier circuit. The first amplifier circuit includes a first amplifier and a bypass circuit. The bypass circuit includes a first capacitance, a second capacitance and a first transistor. The first end of the first transistor is connected to the input end of the first amplifier through the first capacitance. The second end of the first transistor is connected to the output end of the first amplifier through the second capacitance. The third end of the first transistor is connected to a power supply. In addition, the first end of the first transistor is further connected to a first control terminal to receive a control voltage for controlling the working voltage of the first transistor. Thereby, the operation mode of the amplifier circuit can be switched according to the controlled working voltage of the first transistor.

Description

 amplifying circuit  

The invention relates to an amplifying circuit, in particular to an amplifying circuit for performing signal modulation in different operating modes.

The power amplifier is an important component in the RF transmitting circuit. Its main function is to amplify the signal, so the power amplifier is usually set at the front end of the antenna emitter. At the same time, the power amplifier is also the most power-consuming in the entire RF front-end circuit. Components. At present, power amplifiers used in smart electronic devices (eg, smart phones, tablets, etc.) are dominated by gallium arsenide power amplifiers (GaAs PAs). The reason is that GaAs has high frequency, high insulation, low power consumption and low harmonic and noise reception characteristics, which can respond to 4G signal applications with higher transmission capacity, and even higher-end 5G signal applications in the future.

The invention provides an amplifying circuit for performing signal modulation in different operating modes. Such an amplifying circuit includes a first amplifier circuit and a second stage amplifier. The first stage amplifier is connected in series to the first amplifier circuit to form a cascade amplifier circuit. The first amplifier circuit includes a first stage amplifier and a bypass circuit. The first stage amplifier has an input and an output. The bypass circuit includes a first transistor. The first end of the first transistor is coupled to the input end of the first stage amplifier, the second end of the first transistor is coupled to the output end of the first stage amplifier, and the third end of the first transistor is coupled to voltage. The first end of the first transistor is further coupled to the first control end to receive a control voltage from the first control terminal to control the operating bias of the first transistor, thereby switching the operation mode of the amplifying circuit.

The invention also provides an amplifying circuit comprising an amplifier and a bypass circuit. The amplifier has an input and an output. The bypass circuit includes a first transistor. The first end of the first transistor is coupled to the input end of the amplifier, the second end of the first transistor is coupled to the output end of the amplifier, and the third end of the first transistor is coupled to the power supply voltage. The first end of the first transistor is further coupled to a control terminal, so that the control terminal receives the control voltage to control the operating bias of the first transistor.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

IN‧‧‧ input

OUT‧‧‧ output

10‧‧‧First amplifier circuit

110‧‧‧First stage amplifier

1110’‧‧Amplifier

120, 120'‧‧‧ bypass circuit

20‧‧‧second stage amplifier

V _MODE ‧‧‧ control terminal

V _MODE1 ‧‧‧First control terminal

V _MODE2 ‧‧‧second control terminal

Vb‧‧‧Power supply voltage

C1‧‧‧first capacitor

C2‧‧‧second capacitor

RB‧‧‧First bias resistor

RE‧‧‧second bias resistor

R1‧‧‧first resistance

T1‧‧‧first transistor

T2‧‧‧second transistor

T3‧‧‧ third transistor

T4‧‧‧ fourth transistor

T5‧‧‧ fifth transistor

1 is a block diagram of an amplifying circuit illustrated in accordance with an exemplary embodiment of the present invention.

2 is a circuit diagram of an amplification circuit illustrated in accordance with an exemplary embodiment of the present invention.

FIG. 3A is a circuit diagram of a bypass circuit in an amplifying circuit according to an exemplary embodiment of the present invention.

FIG. 3B is a circuit diagram of a bypass circuit in an amplifying circuit according to another exemplary embodiment of the present invention.

4 is a circuit diagram of a bypass circuit in an amplifying circuit according to still another exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram of an amplifying circuit according to another exemplary embodiment of the present invention.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be in the In the figures, like numerals are used to indicate like elements.

The amplifying circuit provided by the present invention will be described in the following embodiments, however, the following embodiments are not intended to limit the present invention.

[An embodiment of the amplifying circuit]

Please refer to FIG. 1. FIG. 1 is a block diagram of an amplifying circuit according to an exemplary embodiment of the present invention. The amplifying circuit provided in this embodiment includes at least a first amplifier circuit 10 and a second stage amplifier 20. For convenience of explanation, the power amplifying circuit provided in this embodiment is exemplified as a three-stage amplifier circuit in the following description and is explained. That is, as shown in FIG. 1, the second stage amplifier 20 is connected in series to the first amplifier circuit 10, and the third stage amplifier 30 is connected in series to the second stage amplifier 20 to form a three stage amplifier circuit.

The first amplifier circuit 10 includes a first stage amplifier 110 and a bypass circuit 120 connected in parallel to the first stage amplifier 110. The main feature of the amplifying circuit provided in this embodiment is that the bypass circuit 120 is controlled through the control terminal V _MODE , so that the entire amplifying circuit can be selectively operated in the dual mode (Dual Mode), that is, the linear mode (Linear) Mode) and Non-linear Mode. Briefly, through the arrangement of the bypass circuit 120, the three-stage amplifier circuit can be used as a two-stage amplifier circuit, wherein the three-stage amplifier circuit operates in a nonlinear mode, and the two-stage amplifier circuit operates in a linear mode. .

It should be noted that, in this embodiment, the amplifying circuit is a power amplifying circuit, the first stage amplifier 110 is a first stage driving amplifier, the second stage amplifier 20 is a second stage driving amplifier, and the third stage amplifier 30 is Third stage power amplifier.

Next, the working principle of the amplifying circuit provided by the embodiment will be further explained.

Please refer to FIG. 2. FIG. 2 is a circuit diagram of an amplifying circuit according to an exemplary embodiment of the present invention. Therefore, the main circuit structure of the bypass circuit 120 can be further understood through FIG. As shown in FIG. 2, the first stage amplifier 110 has an input terminal IN and an output terminal OUT. In addition, the bypass circuit 120 includes a first transistor T1. The first end of the first transistor T1 (indicated by 1 in FIG. 2) is coupled to the input terminal IN of the first stage amplifier 110, and the second end of the first transistor T1 (marked by 2 in FIG. 2) The output terminal OUT of the first stage amplifier 110 is coupled to the third terminal of the first transistor T1 (indicated by 3 in FIG. 2) to be coupled to a power supply voltage Vb.

In particular, the first end of the first transistor T1 is further coupled to the first control terminal V _MODE1 to receive the control voltage from the first control terminal V _MODE1 to control the operating bias of the first transistor T1, thereby switching the amplifying circuit. The operating mode of T1. In short, in the embodiment, the first transistor T1 is in the role of a switch. When the first transistor T1 is turned off, the entire bypass circuit 120 is regarded as an open circuit, and the amplifying circuit is a three-stage. The amplifier circuit operates in a non-linear mode; however, when the first transistor T1 is turned on, the equivalent resistance of the entire bypass circuit 120 is small compared to the first stage amplifier 110, so that the amplifying circuit is equivalent to a second stage The amplifier circuit operates in linear mode.

As shown in FIG. 2, the bypass circuit 120 further includes a bias circuit, and the bias circuit includes at least a first bias resistor R _B , wherein one end of the first bias resistor R _B is coupled to the first a first end of the transistor T1, and the other end of the first bias resistor R _B is coupled to the first control terminal V _MODE1 . In addition, the bypass circuit 120 further includes a second bias resistor R _E , wherein one end of the second bias resistor R _E is coupled to the second end of the first transistor T1, and the other end of the second bias resistor R _E Then, a reference potential or ground is coupled to stabilize the operating point of the first transistor T1.

In this embodiment, the first transistor T1 is a switch. For example, the first transistor T1 is a bipolar junction transistor, wherein the first end of the first transistor T1 is a base, the second end of the first transistor T1 is an emitter, and the first transistor The third end of T1 is the collector. As can be seen from FIG. 2, the first transistor T1 is disposed in the bypass circuit 120 as an emitter follower. Since the emitter follower has an emitter output voltage that varies with the input voltage and the emitter's output signal is in phase with the input signal, the entire bypass circuit 120 will be good even at high power. Linearity. Because of this, the entire power amplifying circuit is suitable for a material having gallium arsenide (GaAs) as a main component.

According to the above, if the first transistor T1 is a bipolar junction transistor, under the control of the control voltage of the first control terminal V _MODE1 , when the operating bias of the first transistor T1 falls on the first transistor T1 In the cut-off region, the first transistor T1 is turned off, so that the amplifying circuit is maintained as a three-stage amplifier circuit and operates in a non-linear mode. On the other hand, under the control of the control voltage of the first control terminal V _MODE1 , when the operating bias of the first transistor T1 falls in the active region of the first transistor T1, the first transistor is turned on, and thus, as described above, The amplifier circuit is equivalent to a two-stage amplifier circuit and operates in a linear mode.

Next, other embodiments of the bypass circuit 120 in the amplifying circuit provided by the present embodiment will be further explained. For ease of understanding, in the following figures of the embodiments, the first end, the second end, and the third end of each transistor are labeled 1, 2, and 3, respectively.

First, please refer to FIG. 3A, which is a circuit diagram of a bypass circuit in an amplifying circuit according to an exemplary embodiment of the present invention. In order to avoid affecting the normal operation of the amplifying circuit when the amplifying circuit is operated in the non-linear mode, in an embodiment, the bypass circuit 120 is designed as the circuit structure as shown in FIG. 3A.

As shown in FIG. 3A, the bypass circuit 120 further includes a second transistor T2, a third transistor T3, a first resistor R1, a first capacitor C1 and a second capacitor C2. The first capacitor C1 is coupled between the first end of the first transistor T1 and the input end of the first stage amplifier 110, and the second capacitor C2 is coupled to the second end of the first transistor T1 and the first stage amplifier. Between the outputs of 110. The first end of the second transistor T2 is coupled to the first end of the third transistor T3, and the third end of the second transistor T2 is coupled to the first bias resistor R _B and the first resistor R1. A control terminal between V _MODE1 . Furthermore, the third end of the third transistor T3 is coupled between the second end of the first transistor T1 and the second capacitor C2, and the first end of the second transistor T2 is coupled to the third end, and The second ends of the second transistor T2 and the third transistor T3 are coupled to a reference potential or a ground. In addition, the second transistor T2 and the third transistor T3 are both bipolar junction transistors, wherein the first ends of the second transistor T2 and the third transistor T3 are bases, and the second transistors T2 and The second end of the tri-crystal T3 is an emitter, and the third end of the second transistor T2 and the third transistor T3 is a collector.

That is to say, in the present embodiment, the arrangement of the second transistor T2 and the third transistor T3 in the bypass circuit 120 is similar to the architecture of a current mirror. In this way, the equivalent resistance of the output terminal OUT of the first stage amplifier 110 to the bypass circuit 120 can be made a large resistance to avoid affecting the normal operation of the amplification circuit in the nonlinear mode.

However, for a bipolar junction transistor, when its collector-emitter voltage changes, the size of the base-collector's depletion width (or depletion region) will also change (ie, the Eurex effect). (Early Effect) such that the current flowing through the second transistor T2 will not be equal to the current flowing from the output terminal OUT of the first stage amplifier 110. Therefore, in another embodiment, the bypass circuit 120 is also designed as a circuit architecture as shown in FIG. 3B.

In contrast to the bypass circuit 120 shown in FIG. 3A, in FIG. 3B, the bypass circuit 120 further includes a fourth transistor T4. The first end of the fourth transistor T4 is coupled to the third end and coupled between the first bias resistor R _B and the first control terminal V _MODE1 through the first resistor R1, and the fourth transistor T4 The two ends are coupled to the first end and the third end of the second transistor T2. In addition, the fourth transistor T4 is a bipolar junction transistor, wherein the first end of the fourth transistor T4 is a base, the second end of the fourth transistor T4 is an emitter, and the fourth transistor T4 is The third end is the collector.

Since the voltage drop of the fourth transistor T4 is increased, a certain proportion of current flowing through the second transistor T2 can be more accurately reproduced, and the aforementioned effect can be improved.

In the circuit architecture of the bypass circuit 120 shown in FIG. 3B, the voltage drop of the fourth transistor T4 can achieve the effect of accurately replicating a certain proportion of current flowing through the second transistor T2, but also represents the power supply. The voltage Vb needs to provide more voltage drop of the fourth transistor T4. During the operation of the amplifying circuit, the power supply voltage Vb (eg, the battery voltage) is gradually decreased. In order to prevent the power supply voltage Vb from decreasing, the bypass circuit 120 shown in FIG. 3B cannot operate normally. In still another embodiment, The bypass circuit 120 is designed as a circuit architecture as shown in FIG.

Compared with the bypass circuit 120 shown in FIG. 2, in FIG. 4, the bypass circuit 120 further includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a first Capacitor C1 and second capacitor C2. As shown in FIG. 4, the first capacitor C1 is coupled between the first end of the first transistor T1 and the input end of the first stage power amplifier 110, and the second capacitor C2 is coupled to the first transistor T1. The two ends are connected to the output of the first stage amplifier 110. The first end of the second transistor T2 is coupled to the first end of the third transistor T3, and the third end of the third transistor T3 is coupled to the second end of the first transistor T1 and the second capacitor C2. The second end of the second transistor T2 and the third transistor T3 are coupled to a reference potential or ground. Furthermore, the first end of the fourth transistor T4 is coupled to the first end of the first transistor T1 via the first bias resistor R _B and the first capacitor C1, and the second end of the fourth transistor T4 is coupled to the second end. The third end of the second transistor T2 is coupled to the first end of the second transistor T2. In addition, the first end of the fourth transistor T5 is coupled to the third end, and is further coupled to the first end of the fourth transistor T4, and the third end of the fourth transistor T4 is coupled to the first control end. V _MODE1 , and the third end of the fifth transistor T5 is coupled to the second control terminal V _MODE2 to receive the control voltage from the first control terminal V _MODE1 and the second control terminal V _MODE2 , respectively.

In addition, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are both bipolar junction transistors, wherein the second transistor T2, the third transistor T3, and the fourth The first ends of the transistor T4 and the fifth transistor T5 are bases, and the second ends of the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are emitters, and The third ends of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are collectors. It should be noted that, in another embodiment, the foregoing first control terminal V _MODE1 and the second control terminal V _MODE2 are the same control terminal.

For the bypass circuit 120 shown in FIG. 4, if the fifth transistor T5 is not provided, and if the second end of the fourth transistor T4 is coupled to the first end, and the second end of the second transistor T2 The first terminal is coupled to the second terminal, and the voltage of the second terminal of the fourth transistor T4 needs to be greater than the threshold voltage of the two transistors. However, in the circuit architecture of the bypass circuit 120 shown in Fig. 4, the voltage at the second terminal of the fourth transistor T4 needs to be at least greater than the threshold voltage of one of the transistors. As a result, during the operation of the amplifying circuit, even if the power supply voltage Vb gradually decreases, the bypass circuit 120 can be prevented from operating normally due to a decrease in the power supply voltage Vb.

It should be noted that, in the foregoing embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be simultaneously replaced by a plurality of gold oxides. a half field effect transistor, and the first ends of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are gates, and the first transistor T1 The second end of the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 is a drain, and the first transistor T1, the second transistor T2, the third transistor T3, and the first transistor The third ends of the fourth transistor T4 and the fifth transistor T5 are sources.

It should be noted that when the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are both MOS field-effect transistors, the first transistor T1 In the bypass circuit 120 of each embodiment, it is set as a source follower. Since the source follower has a characteristic that the voltage gain is approximately equal to 1, the entire bypass circuit 120 can be made to have good linearity even at high power. Because of this, the entire amplifying circuit is suitable for a material in which gallium arsenide (GaAs) is used as a main element.

[Another embodiment of the amplifying circuit]

Referring to FIG. 5, FIG. 5 is a circuit diagram of an amplifying circuit according to another exemplary embodiment of the present invention. In the present embodiment, the amplifying circuit mainly includes an amplifier 110' and a bypass circuit 120'.

As shown in FIG. 5, the amplifier 110' has an input terminal IN and an output terminal OUT, and the bypass circuit includes a first transistor T1. The first end of the first transistor T1 is coupled to the input terminal IN of the amplifier 110'. The second end of the first transistor T1 is coupled to the output end OUT of the amplifier 110'. The third end of the first transistor T1 It is coupled to the power supply voltage Vb. In particular, the first end of the first transistor T1 is further coupled to a control terminal V _MODE to receive a control voltage from the control terminal V _MODE to control the operating bias of the first transistor T1.

It should be noted that, in this embodiment, the amplifying circuit is a power amplifying circuit, and the amplifier 110' is a driving amplifier.

In addition, the bypass circuit 120' further includes a bias circuit, as shown in FIG. 5, the bias circuit includes at least a first bias resistor R _B , and one end of the first bias resistor R _B is coupled to a first electrical terminal of a first crystal of T1, and the other end of the first bias resistor R _B is coupled to the control terminal V _MODE. In addition, the bypass circuit 120' further includes a second bias resistor R _E , wherein one end of the second bias resistor R _E is coupled to the second end of the first transistor T1, and the second bias resistor R _E is further One end is coupled to a reference potential or ground to stabilize the operating point of the first transistor T1.

As in the embodiment described above with reference to FIG. 1 to FIG. 4, in the embodiment, the first transistor T1 is also a switch. For example, the first transistor T1 is a bipolar junction transistor, wherein the first end of the first transistor T1 is a base, the second end of the first transistor T1 is an emitter, and the first transistor The third end of T1 is the collector. As shown in Fig. 5, the first transistor T1 is disposed in the bypass circuit 120' as an emitter follower. Since the emitter follower has a characteristic that the emitter output voltage varies with the input voltage and the emitter output signal is in phase with the input signal, the entire bypass circuit 120' can be obtained even at high power. Good linearity. Because of this, the entire amplifying circuit is suitable for a material in which gallium arsenide (GaAs) is used as a main element.

It should be noted that the working principle of the amplifying circuit provided in this embodiment is similar to that of the first amplifier circuit 10 provided in the embodiments described above with reference to FIGS. 1 to 4. That is, if the first transistor T1 is a bipolar junction transistor as in the foregoing example, when the control terminal V _MODE controls the operating bias of the first transistor T1 and falls on the first transistor T1. In the region, the first transistor T1 is turned off. Therefore, the signal received by the input terminal IN of the amplifier 110' is modulated by the amplifier 110' and outputted by the output terminal OUT of the amplifier 110'. On the other hand, when the control terminal V _MODE controls the operating bias of the first transistor T1 and causes it to fall in the active region of the first transistor T1, the first transistor T1 is turned on. Thus, the signal received by the input terminal IN of the amplifier 110' is directly output to the output terminal OUT of the amplifier 110' through the bypass circuit 120'.

Therefore, if the amplifying circuit provided in this embodiment is connected in series with other amplifiers into a multi-stage amplifier circuit (for example, the amplifying circuit provided in this embodiment can be connected in series with two amplifiers to form a three-stage amplifier circuit. At this time, by controlling the bypass circuit 120' in the amplifying circuit through the control terminal V _MODE , the entire three-stage amplifying circuit can be selectively operated in the dual mode (Dual Mode), that is, the linear mode (Linear Mode) ) and non-linear mode (Non-linear Mode). That is to say, in this example, through the operation of the amplifying circuit provided in this embodiment, the entire multi-stage amplifier circuit can be selectively used as a three-stage amplifier circuit or a two-stage amplifier circuit, wherein the three-stage amplifier circuit system Operating in a non-linear mode, the secondary amplifier circuit operates in a linear mode.

It should be noted that, in this embodiment, the first transistor T1 can be replaced with a gold-oxygen half field effect transistor, and the first end of the first transistor T1 is a gate, and the second transistor T1 is second. The terminal is a drain, and the third end of the first transistor T1 is a source. At this time, the first transistor T1 is disposed as a source follower in the bypass circuit 120' of the present embodiment. Since the source follower has a characteristic that the voltage gain is approximately equal to 1, the entire bypass circuit 120' can be made to have good linearity even when operating at high power. Because of this, the entire amplifying circuit is suitable for a material in which gallium arsenide (GaAs) is used as a main element.

[Possible effects of the examples]

In summary, the amplifying circuit provided by the present invention can be selectively operated in a linear mode or a non-linear mode according to the operational requirements of the electronic device because the bypass circuit is provided.

Furthermore, the circuit structure of the amplifying circuit provided by the present invention enables the entire amplifying circuit to operate normally and stably in the non-linear mode without being affected by the effect of the force, and the bypass circuit can be gradually reduced when the power supply voltage is gradually lowered. Still functioning properly.

In addition, in the bypass circuit of the amplifying circuit provided by the present invention, the first transistor (such as a bipolar junction transistor or a gold oxide half field effect transistor) is set as an emitter follower or source. The pole follower can make the bypass circuit have good linearity even when operating at high power. As a result, the entire amplifying circuit is suitable for the material of gallium arsenide (GaAs) as the main component.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

Claims (17)

 An amplifying circuit for performing signal modulation in different operating modes, comprising: a first amplifier circuit comprising: a first stage amplifier having an input end and an output end; and a bypass circuit The bypass circuit includes a first transistor, wherein the first end of the first transistor is coupled to the input end of the first amplifier, and the second end of the first transistor is coupled to the first amplifier The output end of the first transistor is coupled to a power supply voltage; and a second stage amplifier is coupled in series with the first amplifier circuit to form a cascade amplifier circuit; wherein the first The first end of the transistor is further coupled to a first control terminal for receiving a control voltage from the first control terminal to control an operating bias of the first transistor to switch the operation mode of the amplifying circuit.    The amplifying circuit of claim 1, further comprising a third stage amplifier connected in series to the second amplifier circuit to form the cascade amplifier circuit, wherein the amplifying circuit is a power amplifying circuit, the first stage amplifier It is a first stage driver amplifier, the second stage amplifier is a second stage driver amplifier, and the third stage amplifier is a third stage power amplifier.    The amplifying circuit of claim 1, further comprising a bias circuit, the bias circuit comprising at least a first bias resistor, wherein one end of the first bias resistor is coupled to the first transistor The other end of the first bias resistor is coupled to the first control end.    The amplifying circuit of claim 1, wherein, under the control of the control voltage, when the operating bias of the first transistor falls within a cut-off region of the first transistor, the first transistor is turned off, such that The power amplifier circuit operates in a non-linear mode.    The amplifying circuit of claim 1, wherein the first transistor is turned on when the operating bias of the first transistor falls within an active region or a saturation region of the first transistor under the control of the control voltage The amplifier circuit is operated in a linear region mode.    The amplifying circuit of claim 3, wherein the bypass circuit further comprises a second transistor, a third transistor, a first resistor, a first capacitor and a second capacitor; wherein the first capacitor The first end of the first transistor is coupled to the input end of the first stage amplifier, and the second end is coupled to the second end of the first transistor and the output of the first stage amplifier The second transistor is coupled to the first end of the third transistor, and the third end of the second transistor is coupled to the first bias resistor and the first through the first resistor The third end of the third transistor is coupled between the second end of the first transistor and the second capacitor, and the first end of the second transistor is coupled to the third end And the second transistor and the second end of the third transistor are coupled to a reference potential.    The amplifying circuit of claim 6, wherein the bypass circuit further includes a fourth transistor, wherein the first end of the fourth transistor is coupled to the third end and coupled to the first resistor through the first resistor A first end of the fourth transistor is coupled to the first end and the third end of the fourth transistor.    The amplifying circuit of claim 3, wherein the bypass circuit further comprises: a second transistor, a third transistor, a first capacitor and a second capacitor, wherein the first capacitor is coupled to the first a second capacitor is coupled between the first end of the first transistor and the input end of the first stage amplifier, and the second end is coupled between the second end of the first transistor and the output end of the first stage amplifier, The second transistor is coupled to the first end of the third transistor, and the third end of the third transistor is coupled between the second end of the first transistor and the second capacitor, and the first a second transistor is coupled to a reference potential of the second transistor, and a fourth transistor, the first end of the fourth transistor is coupled to the first transistor through the first bias resistor The first end is coupled to the first capacitor, the second end of the fourth transistor is coupled to the third end of the second transistor, and the third end of the fourth transistor is coupled to the second transistor a first end; and a fifth transistor, the first end of the fifth transistor is coupled to the third end and further coupled to the fourth transistor End; wherein the third terminal of the fourth power of the crystal coupled to the first control terminal, the third terminal of the fifth transistor is coupled to a second control terminal for receiving the control voltage, respectively.    The amplifying circuit of claim 8, wherein the first control end and the second control end are the same control end.    The amplifying circuit of any one of claims 1 to 9, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are a plurality of bipolar junctions a crystal, and the first transistor, the second transistor, the third transistor, and the first end of the fifth transistor are a base, the first transistor, the second a second end of the crystal, the third transistor, the fourth transistor and the fifth transistor is an emitter, and the first transistor, the second transistor, the third transistor, the fourth The crystal and the third end of the fifth transistor are collectors.    The amplifying circuit of any one of claims 1 to 9, wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are a plurality of MOSFETs a crystal, and the first transistor, the second transistor, the third transistor, the fourth transistor, and the first end of the fifth transistor are gates, the first transistor, the second transistor a second end of the crystal, the third transistor, the fourth transistor and the fifth transistor is a drain, and the first transistor, the second transistor, the third transistor, the fourth The crystal and the third end of the fifth transistor are sources.    An amplifying circuit comprising: an amplifier having an input end and an output end; and a bypass circuit comprising a first transistor, wherein the first end of the first transistor is coupled to the The second end of the first transistor is coupled to the output end of the amplifier, and the third end of the first transistor is coupled to a power supply voltage; wherein the first transistor is One end is further coupled to a control end to receive a control voltage from the control terminal to control an operating bias of the first transistor.    The amplifying circuit of claim 12, wherein the amplifying circuit is a power amplifying circuit, the amplifier is a driving amplifier, and the amplifying circuit further comprises a bias circuit, the bias circuit comprising at least a first bias And a first end of the first bias resistor is coupled to the first end of the first transistor, and the other end of the first bias resistor is coupled to the control end.    The amplifying circuit of claim 12, wherein, under the control of the control voltage, when the operating bias of the first transistor falls within a cut-off region of the first transistor, the first transistor is turned off, such that A signal received at the input of the amplifier is modulated by the amplifier and output by the output of the amplifier.    The amplifying circuit of claim 12, wherein the first transistor is turned on when the operating bias of the first transistor falls within an active region or a saturation region of the first transistor under control of the control voltage The signal received by the input of the amplifier is directly output to the output of the amplifier through the bypass circuit.    The amplifying circuit of any one of claims 12 to 15, wherein the first transistor is a bipolar junction transistor, and the first end of the first transistor is a base, and the second transistor is a second The end is an emitter, and the third end of the first transistor is a collector.    The amplification circuit of any one of claims 12 to 15, wherein the first transistor is a MOS field effect transistor, and the first end of the first transistor is a gate and the second transistor is a second The terminal is a drain, and the third end of the first transistor is a source.