CN214380828U - Power amplifying system - Google Patents
Power amplifying system Download PDFInfo
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- CN214380828U CN214380828U CN202120355148.2U CN202120355148U CN214380828U CN 214380828 U CN214380828 U CN 214380828U CN 202120355148 U CN202120355148 U CN 202120355148U CN 214380828 U CN214380828 U CN 214380828U
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Abstract
The utility model belongs to the technical field of amplifier circuit, especially, relate to a power amplification system. The power amplifying circuit of the power amplifying system comprises at least one power amplifying stage; the first bias circuit comprises a bias transistor and a bias power supply end, and the output end of the bias transistor is coupled to the input end of any one power amplification stage in the power amplification circuit; the bias power supply terminal is connected with the input terminal of the bias transistor and is configured to provide a bias voltage for the input terminal of the bias transistor; the first end of the first feedback circuit is connected to an associated node in the first bias circuit, and the second end of the first feedback circuit is connected to a radio frequency signal transmission path in the power amplification circuit, wherein the voltage of the associated node and the voltage of the bias power supply end are in positive correlation/positive following relation. The utility model discloses introduce first bias circuit and first feedback circuit, effectively delayed power amplifier circuit's gain compression phenomenon, improved radio frequency power amplifier's amplitude imbalance and phase place imbalance.
Description
Technical Field
The utility model belongs to the amplifying circuit field especially relates to a power amplification system.
Background
With the development of mobile communication technology, the demand for power amplifiers in communication systems is higher and higher. A power amplifier may be included in a mobile phone to amplify an RF signal for transmission. For example, in a mobile phone that communicates using a cellular standard, a Wireless Local Area Network (WLAN) standard, and/or any other suitable communication standard, a power amplifier may be used to amplify the RF signal. Managing the amplification of RF signals may be important because amplifying RF signals to incorrect power levels or introducing significant distortion of the original RF signal may result in wireless devices emitting out-of-band or violating compliance with accepted standards. Design criteria of the rf power amplifier generally include output power (Pout), efficiency (PAE), gain (gain), bandwidth, linearity (linearity), and so on. For a mobile communication system adopting a linear modulation technique, a linearity index of a radio frequency power amplifier is very important, however, any nonlinearity of the radio frequency power amplifier is easy to generate an undesired frequency component, and particularly, in a process of amplifying a low-power signal into a high-power signal, a phenomenon that a gain is reduced along with an increase of output power, namely gain compression occurs, so that amplitude imbalance (AM-AM imbalance) is generated to seriously affect the performance of the mobile communication system.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that will solve is: aiming at the problems of amplitude maladjustment and the like generated by a power amplifier in the prior art, a power amplification system is provided.
To solve the above-mentioned problems, embodiments of the present invention provide a power amplifier,
the power amplifier comprises a power amplification circuit, a first bias circuit and a first feedback circuit, wherein the power amplification circuit comprises at least one power amplification stage;
the first bias circuit comprises a bias transistor and a bias power supply end, and the output end of the bias transistor is coupled to the input end of any one power amplification stage in the power amplification circuit; the bias power supply terminal is connected with the input terminal of the bias transistor and is configured to provide a bias voltage to the input terminal of the bias transistor;
the first end of the first feedback circuit is connected to an associated node in the first bias circuit, the second end of the first feedback circuit is connected to a radio-frequency signal transmission path in the power amplification circuit, and the voltage of the associated node and the voltage of the bias power supply end are in a positive following relation.
Optionally, the first bias circuit further includes a serial voltage divider circuit, the serial voltage divider circuit is disposed between the bias power supply terminal and the ground terminal, the serial voltage divider circuit includes a plurality of voltage divider units connected in series, a first end of the first feedback circuit is connected to a connection path of any two of the voltage divider units, and a second end of the first feedback circuit is connected to a radio frequency signal transmission path in the power amplifier circuit.
Optionally, the first bias circuit further comprises a regulating circuit, the regulating circuit comprises a first transistor and a second transistor, a base and a collector of the first transistor are respectively connected with the input terminal of the bias transistor, an emitter of the first transistor is connected with a base of the second transistor, an output terminal of the bias power supply terminal is respectively connected with a collector of the first transistor and a collector of the second transistor, and an emitter of the second transistor is grounded; the first end of the first feedback circuit is connected to a connection path of the emitter of the first transistor and the base of the second transistor, and the second end of the first feedback circuit is connected to a radio frequency signal transmission path in the power amplification circuit.
Optionally, the power amplification circuit comprises a first power amplification stage and a second power amplification stage cascaded in series, the first power amplification stage comprises a first amplification transistor, the second power amplification stage comprises a second amplification transistor, and an output terminal of the first amplification transistor is coupled to an input terminal of the second amplification transistor;
a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an input end of the first amplifying transistor;
or a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an output end of the first amplifying transistor;
or, a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an output end of the second amplifying transistor.
Optionally, the power amplification circuit comprises a first power amplification stage, a second power amplification stage and an interstage matching balun, the first power amplification stage comprises a first amplification transistor and a second amplification transistor, the second power amplification stage comprises a third amplification transistor and a fourth amplification transistor, an output end of the first amplification transistor is connected with a first input end of the interstage matching balun, an output end of the second amplification transistor is connected with a second input end of the interstage matching balun, a first output end of the interstage matching balun is connected with an input end of the third amplification transistor, and a second output end of the interstage matching balun is connected with an input end of the fourth amplification transistor;
a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an input end or an output end of the first amplifying transistor;
or a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an input end or an output end of the second amplifying transistor;
or a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an input end or an output end of the third amplifying transistor;
or, a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an input end or an output end of the fourth amplifying transistor.
Optionally, an output of the bias transistor is coupled to an input of the first amplifying transistor; the first end of the first feedback circuit is connected to an associated node in the first bias circuit, and the second end of the first feedback circuit is connected to the input end or the output end of the fourth amplifying transistor.
Optionally, an output of the bias transistor is coupled to an input of a second amplifying transistor; the first end of the first feedback circuit is connected to an associated node in the first bias circuit, and the second end of the first feedback circuit is connected to the input end or the output end of the third amplifying transistor.
Optionally, the first feedback circuit comprises a first feedback capacitance.
Optionally, the first feedback circuit further comprises a first feedback resistor and/or a second feedback inductor connected in series with the first feedback capacitor.
Optionally, the first bias circuit further includes a bias resistor, and an output terminal of the bias transistor is coupled to an input terminal of any one of the power amplifier stages in the power amplifier circuit through the bias resistor.
The utility model discloses a power amplification system, including power amplifier circuit, first biasing circuit and first feedback circuit, power amplifier circuit includes at least one power amplifier stage; the first bias circuit comprises a bias transistor and a bias power supply end, and the output end of the bias transistor is coupled to the input end of any one power amplification stage in the power amplification circuit; the bias power supply terminal is connected with the input terminal of the bias transistor and is configured to provide a bias voltage to the input terminal of the bias transistor; the first end of the first feedback circuit is connected to an associated node in the first bias circuit, and the second end of the first feedback circuit is connected to a radio frequency signal transmission path in the power amplification circuit, wherein the voltage of the associated node and the voltage of the bias power supply end are in positive correlation/positive following relationship. The utility model discloses introduce first bias circuit and first feedback circuit in power amplifier circuit, effectively delayed the radio frequency power amplifier's of the power amplifier stage in the power amplifier circuit gain compression phenomenon, improved radio frequency power amplifier's amplitude imbalance (AM-AM imbalance) to can improve radio frequency power amplifier's phase place imbalance (AM-PM imbalance).
Drawings
Fig. 1 is a schematic structural diagram of a power amplification system according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a power amplification system according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a power amplification system according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of a power amplification system according to a fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of a power amplification system according to a fifth embodiment of the present invention;
fig. 6 is a schematic structural diagram of a power amplification system according to a sixth embodiment of the present invention;
fig. 7 is a schematic structural diagram of a power amplification system according to a seventh embodiment of the present invention.
The reference numerals in the specification are as follows:
1. a power amplification circuit; 11. a first power amplifier stage; 111. a first amplifying transistor; 112. a second amplifying transistor; 12. a second power amplifier stage; 121. a third amplifying transistor; 122. a fourth amplifying transistor; 13. matching the interstage with a balun; 2. a first bias circuit; 21. a bias power supply terminal; 22. a bias transistor; 23. a series voltage divider circuit; 231. A voltage dividing unit; 24. a regulating circuit; 241. a first transistor; 242. a second transistor; 3. a first feedback circuit; 31. a first feedback capacitor.
Detailed Description
In order to make the technical problem, technical solution and advantageous effects solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to illustrate the present invention in further detail. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 1 and fig. 2, an embodiment of the present invention provides a power amplification system, which includes a power amplification circuit 1, a first bias circuit 2 and a first feedback circuit 3, where the power amplification circuit 1 includes at least one power amplification stage.
Understandably, the power amplification system includes the power amplification circuit 1, the first bias circuit 2 and a first feedback circuit 3, the first bias circuit 2 is electrically connected to the power amplification circuit 1, the first bias circuit 2 is configured to provide a bias current and/or a bias voltage to the power amplification circuit 1, which can be selected according to circuit requirements, the first feedback circuit 3 is electrically connected to the first bias circuit 2 and the power amplification circuit 1, respectively, the first feedback circuit 3 is configured to provide a feedback path from the power amplification circuit 1 to the first bias circuit 2 and provide a feedback signal to the first bias circuit 2, the power amplification circuit 1 includes at least one power amplification stage, the power amplification circuit 1 is configured to amplify an input radio frequency signal, and the power amplification stage includes one or more cascaded power amplification transistors, that is, the power amplifier stage may be a single power amplifier transistor, or may be two or more cascaded power amplifier transistors.
The first bias circuit 2 comprises a bias transistor 22 and a bias power supply terminal 21, wherein an output terminal of the bias transistor 22 is coupled to an input terminal of any one power amplification stage in the power amplification circuit 1; the bias power supply terminal 21 is connected to an input terminal of the bias transistor 22 and is configured to provide a bias voltage/bias current to the input terminal of the bias transistor 22.
Understandably, the bias transistor 22 can be configured according to circuit requirements, such as the bias transistor 22 is an NPN transistor, a PNP transistor, etc., in an embodiment, the bias transistor 22 is an NPN transistor, a base of the bias transistor 22 serves as an input terminal of the bias transistor 22, a collector of the bias transistor 22 is connected to a power supply terminal, and an emitter of the bias transistor 22 is coupled to an input terminal of any one of the power amplifier stages in the power circuit, for example: the emitter of the bias transistor 22 is coupled to the base of the first amplifying transistor 111 in the first power amplifying stage 11 of the power amplifying stages, and a bias current or a bias voltage is supplied to the power amplifying circuit 1 through the output terminal of the bias transistor 22. Wherein, the bias power supply terminal 21 can be connected to a current source or a voltage source according to circuit requirements, the bias power supply terminal 21 is used for providing a bias voltage to the input terminal of the bias transistor 22, and the bias power supply terminal 21 is connected to the base of the bias transistor 22.
A first end of the first feedback circuit 3 is connected to an associated node in the first bias circuit 2, and a second end of the first feedback circuit 3 is connected to a radio frequency signal transmission path in the power amplification circuit 1, wherein a voltage of the associated node and a voltage of the bias power supply terminal 21 are in a positive following relationship.
Understandably, the first feedback circuit 3 comprises the first terminal and the second terminal, the first bias circuit 2 further comprises the associated node, the voltage of the associated node changes in positive correlation/positive following relationship with the change in the voltage of the bias power source terminal 21, i.e., in the case where the voltage of the bias power terminal 21 becomes larger, the voltage of the associated node becomes larger, the first terminal is connected to the relevant node, the second terminal is connected to the radio frequency signal transmission path in the power amplification circuit 1, i.e. the second terminal is connected to an input or output of any one of the power amplifier stages in the power amplifier circuit 1, the input terminal may be the base/gate of any one of the transistors in the power amplifier stage, the output terminal may be a collector/source of any one of the transistors in the power amplifier stage.
Thus, when the radio frequency signal is inputted into the power amplifying system, the radio frequency signal is amplified by the power amplifying circuit 1, and the amplified radio frequency signal outputted by the power amplifying circuit 1 is prevented from being distorted by the first bias circuit 2 and the first feedback circuit 3 according to the change of the radio frequency signal during the amplifying process, the utility model realizes that under the condition that the input power inputted into the power amplifying circuit 1 is increased, the signal fed back to the first bias circuit 2 by the first feedback circuit 3, the first bias circuit 2 can provide the current/voltage increased along with the signal fed back by the first feedback circuit 3, thereby effectively delaying the gain compression phenomenon of the radio frequency power amplifier of the power amplifying stage in the power amplifying circuit 1, and improving the amplitude imbalance (AM-AM imbalance) of the power amplifying circuit 1, and the input parasitic capacitance generated by the power amplifying circuit 1 is reduced by the first feedback circuit 3, and the improvement of the phase offset (AM-PM offset) of the power amplifying circuit 1 is realized.
In an embodiment, as shown in fig. 3, the first bias circuit 2 further includes a serial voltage dividing circuit 23, the serial voltage dividing circuit 23 is disposed between the bias power terminal 21 and a ground terminal, the serial voltage dividing circuit 23 includes a plurality of voltage dividing units 231 connected in series, a first end of the first feedback circuit 3 is connected to a connection path of any two of the voltage dividing units 231, and a second end of the first feedback circuit 3 is connected to a radio frequency signal transmission path in the power amplifying circuit 1. Understandably, the voltage dividing unit 231 is a unit component or a circuit capable of dividing voltage, and the voltage dividing unit 231 can be selected according to circuit requirements, for example, the voltage dividing unit 231 is a diode, a resistor, a triode, or the like, for example: the series voltage divider circuit 23 is two diodes connected in series, and the first end of the first feedback circuit 3 is connected to a path between the two diodes; or the serial voltage dividing circuit 23 is two resistors connected in series, and the first end of the first feedback circuit 3 is connected to a path between the two resistors; or the serial voltage dividing circuit 23 is two serially connected transistors playing a voltage dividing role, the transistors may be HBT transistors or MOS transistors, and the first end of the first feedback circuit 3 is connected to a path between two resistors; or the series voltage dividing circuit 23 is a resistor and a diode connected in series, and the first end of the first feedback circuit 3 is connected to a path between the resistor and the diode.
In one embodiment, as shown in fig. 4, the first bias circuit 2 further includes a regulating circuit 24, the regulating circuit 24 includes a first transistor 241 and a second transistor 242, the base and the collector of the first transistor 241 are respectively connected to the input terminal of the bias transistor 22, the emitter of the first transistor 241 is connected to the base of the second transistor 242, the output terminal of the bias power supply terminal 21 is respectively connected to the collector of the first transistor 241 and the collector of the second transistor 242, and the emitter of the second transistor 242 is grounded; a first terminal of the first feedback circuit 3 is connected to a connection path between the emitter of the first transistor 241 and the base of the second transistor 242, and a second terminal of the first feedback circuit 3 is connected to a radio frequency signal transmission path in the power amplification circuit 1.
Specifically, the adjusting circuit 24 is connected to the first bias circuit 2, the adjusting circuit 24 includes a first transistor 241 and a second transistor 242, and the first transistor 241 and the second transistor 242 form a current mirror, so that the AM-PM offset of the power amplification system is improved, and the linearity is improved, where the first transistor 241 and the second transistor 242 may be set according to circuit requirements, for example, the first transistor 241 and the second transistor 242 are both HTB transistors.
Further, the adjusting circuit 24 may also implement dynamic performance adjustment of the power amplifying circuit 1 by the first bias circuit 2, and improve dynamic EVM of the power amplifying system. In the above circuit structure, when the bias power supply terminal 21 is controlled to switch from the off state to the on state, the first bias circuit 2 is turned on, the current flowing to the power amplifier circuit 1 increases, and at the same time, the temperature of the power amplifier stage in the power amplifier circuit 1 increases, the transconductance decreases, the voltage between the base and the emitter in the power amplifier stage decreases due to the temperature characteristic of the transistor, which further causes the quiescent current of the power amplifier stage to increase, the transconductance decreases, and the gain decreases, which directly causes the linear distortion of the circuit, and if the quiescent current of the power amplifier stage cannot be stabilized within the time of the switching process of the power amplifier circuit 1, the dynamic EVM of the circuit will be deteriorated. Therefore, in the present invention, in order to improve the dynamic EVM performance of the whole power amplification system, the second transistor 242 is configured as a thermal sensing transistor and is located near the power amplification stage, that is, the distance between the second transistor 242 and other devices is greater than the distance between the second transistor 242 and the power amplification stage, when the power amplification circuit 1 is turned on, the temperature of the second transistor 242 will also increase with the increase of the temperature of the power amplification stage due to the conduction of heat in a short-distance space, and at this time, the current of the second transistor 242 will increase with the increase of temperature to cause the increase of bias current, thus adding a negative feedback action to the whole circuit during the operation, and increasing a negative feedback action through the first feedback circuit 3 to accelerate the speed of thermal equilibrium, thereby inhibiting the increase of current of the power amplification stage during the temperature increase, therefore, the current state rapidly reaches thermal balance, the static current finally reaches stability, the current of the power amplification circuit 1 rapidly reaches the stable state in the switching process, and the dynamic EVM performance of the whole power amplification system is improved.
In an embodiment, as shown in fig. 4, the power amplification circuit 1 includes a first power amplification stage 11 and a second power amplification stage 12 cascaded in series, the first power amplification stage 11 includes a first amplification transistor 111, the second power amplification stage 12 includes a second amplification transistor 112, an output terminal of the first amplification transistor 111 is coupled to an input terminal of the second amplification transistor 112; a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an input end of the first amplifying transistor; or a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an output end of the first amplifying transistor; or, a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an output end of the second amplifying transistor.
Understandably, the power amplifier circuit 1 comprises two power amplifier stages cascaded in series, the two power amplifier stages are the first power amplifier stage 11 and the second power amplifier stage 12, respectively, an output terminal of the first amplifier transistor 111 is coupled to an input terminal of the second amplifier transistor 112, so as to form the cascaded power amplifier circuit 1, wherein the first power amplifier stage 11 comprises the first amplifier transistor 111, the second power amplifier stage 12 comprises the second amplifier transistor 112, the first amplifier transistor 111 and the second amplifier transistor 112 can be selected according to circuit requirements, such as an NPN type triode, an HTB triode, and the like, the first amplifier transistor 111 and the second amplifier transistor 112 are preferably transistors of the same type, and linearity is kept consistent, for example: the first amplifying transistor 111 and the second amplifying transistor 112 are selected to be NPN type triodes, a collector of the first amplifying transistor 111 is connected to a base of the second amplifying transistor 112, and an emitter of the first amplifying transistor 111 and an emitter of the second amplifying transistor 112 are both grounded; the collector of the first amplifier transistor 111 may be connected to the emitter of the second amplifier transistor 112, the emitter of the first amplifier transistor 111 may be grounded, and the base of the second amplifier transistor 112 may be grounded via a dc blocking capacitor.
In the above circuit structure, after an input radio frequency signal is input to the first power amplifier stage 11, the first power amplifier stage 11 performs a first-stage amplification process on the radio frequency signal to obtain a first-stage amplified radio frequency signal, the first-stage amplified radio frequency signal is input to the second power amplifier stage 12, and the second power amplifier stage 12 performs a second-stage amplification process on the first-stage amplified radio frequency signal to obtain a first-stage amplified and second-stage amplified radio frequency signal output by the power amplifier circuit 1.
Understandably, the second terminal of the first feedback circuit 3 is connected to the input terminal of the first power amplifier stage 11 or the input terminal of the second power amplifier stage 12, i.e. to the base of the first amplifier transistor 111 of the first power amplifier stage 11 or the base of the second amplifier transistor 112 of the second power amplifier stage 12, and the second terminal of the first feedback circuit 3 is also connected to the output terminal of the first power amplifier stage 11 or the output terminal of the second power amplifier stage 12, i.e. to the collector of the first amplifier transistor 111 of the first power amplifier stage 11 or the collector of the second amplifier transistor 112 of the second power amplifier stage 12, and as the input power of the input radio frequency signal increases, the power of the base and the collector of the first amplifier transistor 111 increases, the power of the base and the collector of the second amplifying transistor 112 will also increase accordingly, so that the voltage of the associated node in the first bias circuit 2 can be increased through the connected first feedback circuit 3, and the voltage of the input terminal of the bias transistor 22 can be increased, and therefore, the bias current provided to the power amplifying circuit 1 through the bias transistor 22 is increased, thereby delaying the gain compression phenomenon of the power amplifying stage in the power amplifying circuit 1, improving the AM-AM imbalance of the whole power amplifying circuit 1, and also improving the linearity.
In one embodiment, as shown in fig. 5, the power amplification circuit 1 includes a first power amplification stage 11, a second power amplification stage 12 and an interstage matching balun 13, the first power amplification stage 11 includes a first amplification transistor 111 and a second amplification transistor 112, the second power amplification stage 12 includes a third amplification transistor 121 and a fourth amplification transistor 122, an output terminal of the first amplification transistor 111 is connected to a first input terminal of the interstage matching balun 13, an output terminal of the second amplification transistor 112 is connected to a second input terminal of the interstage matching balun 13, a first output terminal of the interstage matching balun 13 is connected to an input terminal of the third amplification transistor 121, and a second output terminal of the interstage matching balun 13 is connected to an input terminal of the fourth amplification transistor 122; a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an input end or an output end of the first amplifying transistor; or a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an input end or an output end of the second amplifying transistor; or a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an input end or an output end of the third amplifying transistor; or, a first end of the first feedback circuit is connected to an associated node in the first bias circuit, and a second end of the first feedback circuit is connected to an input end or an output end of the fourth amplifying transistor.
Understandably, the first amplifying transistor 111, the second amplifying transistor 112, the third amplifying transistor 121 and the fourth amplifying transistor 122 may be selected according to circuit requirements, such as NPN type triode, HTB triode, etc., the first power amplifying stage 11, the second power amplifying stage 12 and the interstage matching balun 13 form a push-pull type power amplifying circuit 1, which performs push-pull type amplification on an input radio frequency signal and performs phase change through the interstage matching balun 13, so as to output a push-pull type amplified radio frequency signal with phase change, where the phase change corresponds to existence of phase offset, i.e. phase offset, and the second end of the first feedback circuit 3 is connected to a radio frequency signal transmission path in the power amplifying circuit 1, i.e. the second end of the first feedback circuit 3 is connected to the base or collector of the first amplifying transistor 111, the base or collector of the second amplifying transistor 112, the base or collector of the third amplifying transistor 121, or the base or collector of the fourth amplifying transistor 122, i.e. the power before and after the inter-stage matching balun 13, can be fed back to the first bias circuit 2 through the first feedback circuit 3 for adjustment, that is, as the input power of the input rf signal increases, the power of the base and collector of the first amplifying transistor 111 increases, and the power of the base and collector of the second amplifying transistor 112 increases, so that the voltage of the associated node in the first bias circuit 2 can be increased through the connected first feedback circuit 3, thereby increasing the voltage of the input terminal of the bias transistor 22, and therefore, the bias current provided to the power amplifying circuit 1 by the bias transistor 22 increases, thereby delaying the gain compression phenomenon of the power amplifier stage in the power amplifier circuit 1, improving the AM-AM imbalance of the whole power amplifier circuit 1 and also improving the linearity; as the input power of the input rf signal increases, the power and phase offset of the base and collector of the third amplifying transistor 121 increase, and the phase offset also increases, and the power and phase offset of the base and collector of the fourth amplifying transistor 122 increase, so that the voltage of the associated node in the first bias circuit 2 can be increased by the connected first feedback circuit 3, and the input parasitic capacitance is reduced by the connected first feedback circuit 3, so that the phase of the associated node in the first bias circuit 2 is compensated for by the phase offset, and finally, the AM-AM offset of the whole power amplifying circuit 1 is improved, the linearity is also improved, and the phase offset of the power amplifying circuit 1 is improved.
In one embodiment, as shown in fig. 6, the output terminal of the bias transistor 22 is coupled to the input terminal of the first amplifying transistor 111, the first terminal of the first feedback circuit 3 is connected to the associated node in the first bias circuit 2, and the second terminal of the first feedback circuit 3 is connected to the input terminal or the output terminal of the fourth amplifying transistor 122. Understandably, after the input radio frequency signal is amplified by the first power amplifier stage 11, and after the input radio frequency signal is subjected to the phase inversion conversion by the inter-stage matching balun 13, the phase inversion conversion is performed to perform 180-degree phase inversion conversion on the input radio frequency signal, the radio frequency signal after the phase inversion conversion is input into the fourth amplifying transistor 122 and is amplified by the fourth amplifying transistor 122, and in the process, the radio frequency signal is connected to the bias transistor 22 through the first feedback circuit 3, so that a negative feedback behavior is provided, and the input end of the first amplifying transistor 111 is adjusted by the bias transistor 22, so that the AM-AM offset of the whole power amplifying circuit 1 is improved, the linearity is also improved, and the phase offset of the power amplifying circuit 1 is improved.
In one embodiment, as shown in fig. 7, the output terminal of the bias transistor 22 is coupled to the input terminal of the second amplifying transistor 112, the first terminal of the first feedback circuit 3 is connected to the associated node in the first bias circuit 2, and the second terminal of the first feedback circuit 3 is connected to the input terminal or the output terminal of the third amplifying transistor 121. Understandably, the input rf signal is amplified by the first power amplifier stage 11, and then is subjected to the positive phase conversion of the inter-stage matching balun 13, the positive phase conversion is a phase conversion close to zero degree, the rf signal after the positive phase conversion is input into the third amplifying transistor 121, and is amplified by the third amplifying transistor 121, and in this process, the rf signal is connected to the bias transistor 22 through the first feedback circuit 3, so as to provide a positive feedback behavior, and the input end of the first amplifying transistor 111 is adjusted by the bias transistor 22, so as to improve the AM-AM imbalance of the whole power amplifier circuit 1.
In an embodiment, the first feedback circuit 3 comprises a first feedback capacitor 31. Understandably, the capacitance value of the first feedback capacitor 31 can be set according to the circuit requirements, and the first feedback capacitor 31 can quickly and effectively reduce the parasitic capacitance of the whole power amplification circuit 1, and also plays a role of feeding back a signal, so as to improve the amplitude imbalance and the phase imbalance of the power amplification circuit 1.
In an embodiment, the first feedback circuit further comprises a first feedback resistor and/or a second feedback inductor connected in series with the first feedback capacitor. Understandably, the series combination of the first feedback capacitor 31 and the first feedback resistor, or the series combination of the first feedback capacitor 31 and the second feedback inductor, which is included in the first feedback circuit 3, can all function as an effective feedback signal, so as to improve the amplitude offset and the phase offset of the power amplification circuit 1.
In an embodiment, the first bias circuit 2 further includes a bias resistor, and the output terminal of the bias transistor 22 is coupled to the input terminal of any one of the power amplifier stages in the power amplifier circuit 1 through the bias resistor. Understandably, the bias resistor can select a resistance value according to circuit requirements, and plays a role in limiting the current in the bias current or/and the voltage provided by the bias circuit to the power amplification circuit 1, thereby playing a role in protecting the power amplification circuit 1.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A power amplification system comprising a power amplification circuit, a first bias circuit and a first feedback circuit, the power amplification circuit comprising at least one power amplification stage;
the first bias circuit comprises a bias transistor and a bias power supply end, and the output end of the bias transistor is coupled to the input end of any one power amplification stage in the power amplification circuit; the bias power supply terminal is connected with the input terminal of the bias transistor and is configured to provide a bias voltage to the input terminal of the bias transistor;
the first end of the first feedback circuit is connected to an associated node in the first bias circuit, the second end of the first feedback circuit is connected to a radio-frequency signal transmission path in the power amplification circuit, and the voltage of the associated node and the voltage of the bias power supply end are in a positive following relation.
2. The power amplification system of claim 1, wherein the first bias circuit further comprises a series voltage dividing circuit provided between the bias power supply terminal and a ground terminal, the series voltage dividing circuit comprising a plurality of voltage dividing cells connected in series, a first terminal of the first feedback circuit being connected to a connection path of any two of the voltage dividing cells.
3. The power amplification system of claim 1, wherein the first bias circuit further comprises a regulation circuit comprising a first transistor and a second transistor, the base and collector of the first transistor being connected to the input terminal of the bias transistor, respectively, the emitter of the first transistor being connected to the base of the second transistor, the output terminal of the bias power supply terminal being connected to the collector of the first transistor and the collector of the second transistor, respectively, the emitter of the second transistor being grounded; the first end of the first feedback circuit is connected to a connection path of the emitter of the first transistor and the base of the second transistor.
4. The power amplification system of claim 1, wherein the power amplification circuit comprises a first power amplification stage and a second power amplification stage cascaded in series, the first power amplification stage comprising a first amplification transistor, the second power amplification stage comprising a second amplification transistor, an output of the first amplification transistor coupled to an input of the second amplification transistor;
a second end of the first feedback circuit is connected to an input end of the first amplifying transistor;
or the second end of the first feedback circuit is connected to the output end of the first amplifying transistor;
or, the second end of the first feedback circuit is connected to the output end of the second amplifying transistor.
5. A power amplification system according to claim 1, wherein the power amplification circuit comprises a first power amplification stage comprising a first amplification transistor and a second amplification transistor, a second power amplification stage comprising a third amplification transistor and a fourth amplification transistor, and an interstage matching balun, an output of the first amplification transistor being connected to a first input of the interstage matching balun, an output of the second amplification transistor being connected to a second input of the interstage matching balun, a first output of the interstage matching balun being connected to an input of the third amplification transistor, a second output of the interstage matching balun being connected to an input of the fourth amplification transistor;
the second end of the first feedback circuit is connected to the input end or the output end of the first amplifying transistor;
or the second end of the first feedback circuit is connected to the input end or the output end of the second amplifying transistor;
or the second end of the first feedback circuit is connected to the input end or the output end of the third amplifying transistor;
or, the second end of the first feedback circuit is connected to the input end or the output end of the fourth amplifying transistor.
6. The power amplification system of claim 5, wherein an output of the bias transistor is coupled to an input of the first amplification transistor.
7. The power amplification system of claim 5, wherein an output of the bias transistor is coupled to an input of a second amplification transistor.
8. The power amplification system of claim 1, wherein the first feedback circuit comprises a first feedback capacitor.
9. The power amplification system of claim 8, wherein the first feedback circuit further comprises a first feedback resistor and/or a second feedback inductor connected in series with the first feedback capacitor.
10. The power amplification system of claim 1, wherein the first bias circuit further comprises a bias resistor, and wherein the output of the bias transistor is coupled to the input of any one of the power amplification stages in the power amplification circuit through the bias resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120355148.2U CN214380828U (en) | 2021-02-08 | 2021-02-08 | Power amplifying system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120355148.2U CN214380828U (en) | 2021-02-08 | 2021-02-08 | Power amplifying system |
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|---|---|
| CN214380828U true CN214380828U (en) | 2021-10-08 |
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|---|---|---|---|
| CN202120355148.2U Active CN214380828U (en) | 2021-02-08 | 2021-02-08 | Power amplifying system |
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| CN (1) | CN214380828U (en) |
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- 2021-02-08 CN CN202120355148.2U patent/CN214380828U/en active Active
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Address after: 518000 room 2001, building 3, Shenzhen new generation industrial park, 136 Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen City, Guangdong Province Patentee after: Ruishi Chuangxin (Shenzhen) Technology Co.,Ltd. Address before: 518000 room 2001, building 3, Shenzhen new generation industrial park, 136 Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen City, Guangdong Province Patentee before: AN ADVANCED RF POWER AMPLIFIER AND COMMUNICATION DEVICE |
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