TW201824263A - Storage device and method for setting reading voltage thereof - Google Patents

Abstract

A storage device and a method for setting a reading voltage thereof are provided. The storage device includes a NAND flash memory and an access circuit. The NAND flash memory is used to store a first data. The access circuit is coupled to the NAND flash memory for recording a power-on non-update time and a power-off non-update time of the first data, and determines a read voltage of the first data according to the power-on non-update time and the power-off non-update time.

Description

Storage device and read voltage setting method thereof

The present invention relates to a storage device, and more particularly to a storage device and a method for setting the read voltage thereof.

Semiconductor memory is usually classified into a volatile semiconductor memory or a non-volatile memory. Moreover, the development of self-power erasable programmable read only memory (EEPROM) technology, NAND flash memory has been widely used in a large number of non-volatile data storage devices. However, since the storage device using the anti-gate flash memory has reduced the data reading performance due to the problem of data retention, some manufacturers have proposed a method of sacrificing the service life to maintain the reading performance of the storage device. (eg periodic data rewriting), but the above approach does not address the underlying problem of the storage device and introduces new problems.

The invention provides a storage device and a reading voltage setting method thereof, which can determine the reading voltage of the data according to the power-on time and the power-off time and the power-off time, so as to reduce the frequency of data updating.

The storage device of the present invention comprises a reverse flash memory and an access circuit. The gate flash memory is used to store a first data. The access circuit is coupled to the gate flash memory for recording a power-on unupdate time of the first data and a power-off unupdate time, and determining the first data according to the power-on time and the power-off time. A read voltage.

The reading voltage setting method of the storage device of the present invention includes the following steps. A power-on unupdated time and a power-off unupdated time of a first data stored in a reverse flash memory are recorded through an access circuit. A read voltage of the first data is determined by the access circuit according to the power-on time and the power-off time.

Based on the above, the storage device of the example of the present invention and the read voltage setting method thereof record the power-on-update time and the power-off unupdate time of the first data, and the power-on-update time and the power-off time are not updated according to the first data. Determine the reading voltage of the data to reduce the frequency of data updates.

The above described features and advantages of the invention will be apparent from the following description.

1 is a system diagram of a storage device in accordance with an embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the storage device 100 is coupled to the host 10 to receive the data XDD provided by the host 10 or controlled by the host 10 to provide the required data XDD. The storage device 100 includes an access circuit 110 and an anti-gate flash memory 120. The anti-gate flash memory 120 can be a single level cell (TLC), a gate flash memory, or a multi-layer memory. Multi Level Cell (TLC) and Gate Flash Memory, or Triple Level Cell (TLC) and Gate Flash Memory.

The access circuit 110 is coupled to the host 10 and the anti-gate flash memory 120 for storing (or writing) the data XDD (corresponding to the first data) to the anti-gate flash after receiving the data XDD from the host 10. In the memory 120, the access circuit 110 records the power-on unupdated time Ton and the power-off unupdated time Toff after the data XDD is written. Next, when the access circuit 110 is controlled by the host 20 to read the data XDD, the read voltage of the data XDD is determined according to the power-on unupdated time Ton and the power-off unupdated time Toff.

Further, since the voltage level of the data XDD stored in the anti-gate flash memory 120 is elongated along with the unupdated time (including the sum of the power-on unupdate time Ton and the power-off unupdate time Toff) The lower, that is, the longer the sum of the power-on unupdated time Ton and the power-off unupdated time Toff, the lower the voltage level of the data XDD, so the read voltage of the data XDD also needs to be lower.

Wherein, the power-on unupdated time Ton and the power-off unupdated time Toff can be directly added to obtain a voltage attenuation coefficient, that is, n is proportional to (Ton+Toff)/Tth, and then the reading voltage of the data XDD is determined according to the voltage attenuation coefficient. , that is, Vread=Vro-n×ΔV, where Tth is a time threshold, Vread is the read voltage, Vro is the preset value of the read voltage, and ΔV is the adjusted voltage range (ie, several volts), n Is the voltage attenuation coefficient. Alternatively, the power-on unupdated time Ton and the power-off unupdated time Toff may be respectively multiplied by corresponding weight values to add a voltage attenuation coefficient, that is, n is proportional to (Ton×a+Toff×b)/Tth, where the coefficient The sum of a and b can be set to 1 to facilitate calculation.

In the embodiment of the present invention, a memory location of a logical block address (LBA) may be defined in the anti-gate flash memory 120 to store the system time, so that the host 10 will system time. Write to the above memory location, for example, periodically, or when the system is booting up and shutting down the program. The access circuit 110 can actively retrieve the system time written by the host 10 to determine the time stamp of the system power-on and power-off, and then know the length of time after the system is powered off, and then update the power-off unupdated time Toff correspondingly.

In the embodiment of the present invention, after the system is powered on, the host 10 may first write to the memory location, that is, first update the system time of the memory location, and the access circuit 110 reads the update. After the system time. Moreover, the access circuit 110 will grasp the time itself to avoid interference with the operation of the host 10 after updating the power-off unupdated time Toff until the next power-off of the system. Before the system is powered off, the host 10 will inform the access circuit 110 by the next system standby command CMS. At this time, the access circuit 110 reads the memory location to update the power supply according to the obtained system time. Time Ton.

According to the above, when the access circuit 110 receives the system standby command CMS, the access circuit 110 records the current system time as the first time stamp T1. When the system is powered on, the host 10 notifies the access circuit 110 to update the system time (i.e., update the time stamp). When the access circuit 110 receives the second time stamp T2 of updating the system time, the power-off unupdated time Toff is updated according to the time difference between the first time stamp T1 and the second time stamp T2, wherein the access circuit 110 will be powered off. The original time of the update time Toff plus the above time difference is substituted for the power failure unupdated time Toff.

In the embodiment of the present invention, the access circuit 110 can record the first time stamp T1, the power-on unupdated time Ton, and the power-off unupdated time Toff through a Flash Translation Layer (FTL).

2 is a flow chart of a method for setting a read voltage of a storage device according to an embodiment of the invention. Referring to FIG. 2, in the embodiment, the reading voltage setting method of the storage device includes the following steps. In step S210, the power-on unupdated time and the power-off unupdated time of the first data stored in the anti-gate flash memory are recorded through the access circuit. Next, in step S220, a read voltage of the first data is determined by the access circuit according to the power-on unupdated time and the power-off unupdated time. The order of the steps S210 and S220 is used for the description, and the embodiment of the present invention is not limited thereto. For details of the steps S210 and S220, reference may be made to the embodiment of FIG. 1 , and details are not described herein again.

In summary, the storage device and the read voltage setting method of the example of the present invention record the power-on-update time and the power-off time of the first data, and the power-on and update time and the power-off according to the first data are not The update time determines the read voltage of the data to reduce the frequency of data updates.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Host

100‧‧‧ storage device

110‧‧‧Access circuit

120‧‧‧Anti-gate flash memory

CMS‧‧‧ system standby instruction

Toff‧‧‧ power failure has not been updated

Ton‧‧‧Powered up time

XDD‧‧‧Information

S210, S220‧‧‧ steps

1 is a system diagram of a storage device in accordance with an embodiment of the present invention. 2 is a flow chart of a method for setting a read voltage of a storage device according to an embodiment of the invention.

Claims (10)

A storage device includes: a reverse flash memory for storing a first data; and an access circuit coupled to the anti-gate flash memory for recording a power of the first data The time is not updated and the power is not updated, and a read voltage of the first data is determined according to the power-on-update time and the power-off time. The storage device of claim 1, wherein the anti-gate flash memory further stores a system time, and when the access circuit receives a system standby command, the access circuit records the current system. The time is used as a first time stamp. When the access circuit receives a second time stamp for updating the system time, the power failure unupdated time is updated according to a time difference between the first time stamp and the second time stamp. The storage device of claim 2, wherein the access circuit records the first time stamp, the power-on-update time, and the power-off unupdated time through a Flash Translation Layer (FTL) . The storage device of claim 2, wherein the access circuit replaces the power-off unupdated time by adding the time difference to an original time of the power-off unupdated time. The storage device of claim 1, wherein the longer the sum of the power-on-update time and the power-off time is, the lower the read voltage of the first data. A method for setting a read voltage of a storage device includes: recording, by an access circuit, a power-on unupdated time and a power-off unupdated time of a first data stored in a flash memory; and The access circuit determines a read voltage of the first data according to the power-on-update time and the power-off time. The method for setting a read voltage of the storage device according to claim 6, wherein the anti-gate flash memory further stores a system time, and the read voltage setting method further comprises: when the access circuit receives When the system standby command is issued, the current system time is recorded as a first time stamp through the access circuit; and when the access circuit receives a second time stamp for updating the system time, the access circuit is transmitted through the access circuit And updating the power failure unupdated time according to a time difference between the first time stamp and the second time stamp. The method for setting a read voltage of a storage device according to claim 7, wherein the access circuit records the first time stamp, the power-on-update time, and a flash translation layer (FTL) The power failure has not been updated. The method for setting a read voltage of a storage device according to claim 7, wherein the step of updating the power-off unupdated time by the access circuit according to a time difference between the first time stamp and the second time stamp comprises: And replacing, by the access circuit, an original time of the power-off unupdated time by the time difference and replacing the power-off unupdated time. The method for setting a read voltage of a storage device according to claim 6, wherein the longer the sum of the power-on-update time and the power-off time is, the lower the read voltage of the first data.