JP2011159138A - Storage device and method of controlling the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To find ways to increase vacant memory cells using a limited number from an operational standpoint, in view of the fact that, if a semiconductor disk device is installed as a storage region of an information processor, the reliability of data could deteriorate due to the life of memory cells and that there is a limit to the number of memory parts to be installed, despite the need to increase the number of vacant memory cells in order to prolong the life. <P>SOLUTION: This control method includes recording written data information such as the number of writes to a physical position and a logical position of a memory cell when data is written. After a physical/logical position control part 105 determines a physical position where a write is made, a recording method control part 106 determines a recording method that matches the frequency of data updates. Data is written according to this determination, and a function to preferentially allocate vacant memory cells to data with high frequencies of updates is newly provided. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention is a semiconductor disk storage device equipped with a NAND flash memory, and has a function of counting the number of writes to a certain range of memory cells, and in order to realize a low price and long life, the number of writes is determined. The present invention relates to a storage device that controls a memory cell recording system and optimizes the recording state of the entire disk.

  The mainstream of semiconductor disk storage devices is to record data in NAND flash memory cells. The memory cell has a MOS transistor structure, and charges are injected into a floating gate layer that is sandwiched between insulating layers by voltage control of the gate layer and electrically isolated, and data is recorded by maintaining a charged state. Yes. One bit is maintained for one floating gate layer with one type of charge state. A recording method called SLC (Single Level Cell) is used, and the charge state of the floating gate layer is partially managed to maintain multiple charge states. Is a recording method called MLC (Multi Level Cell) that maintains 2 bits or more. When data is written / erased, charges pass through the insulating layer. Therefore, if the writing operation is repeated, the insulating layer is damaged and cannot perform the function of insulation.

  From the above, it is general that the number of times of writing exists in the NAND flash memory cell. Although the memory cells used in the SLC method and the MLC method are the same, the MLC method manages a plurality of charged states, so that the voltage control becomes strict and is sensitive to the damage of the insulating layer. Therefore, in general, the life of the MLC method is shorter than that of the SLC method, and the life is shortened as the charged state to be managed increases, that is, the number of bits to be recorded on the floating gate layer increases. In semiconductor disk devices, the SLC method and MLC method are properly used according to the application, and the life management is performed by the memory controller. Japanese Patent Application Laid-Open No. 8-16482 describes life management and write control technology in a storage device using a NAND flash memory.

JP-A-8-16482

  In recent years, NAND flash memory has been miniaturized and increased in capacity due to process miniaturization, and a semiconductor disk device having an interface such as SATA / SAS has been used as an alternative to a conventional magnetic disk device. The semiconductor disk device has high data access performance and low power consumption, and is actively installed in information processing devices such as personal computers and servers. However, it has a complicated configuration and system characteristics that accompany many data accesses. There is concern about the deterioration of data reliability. As means for solving this problem, the semiconductor disk device implements wear leveling control that preferentially writes to a memory cell with a small number of writes. By equalizing the number of times of writing for each memory cell, the number of times of writing of more memory cells can be utilized and the life of the semiconductor disk device itself is extended.

  With the above control, the longer the number of empty memory cells, the longer the life of the semiconductor disk device. However, the number of memory cells per unit area is limited, and as the number of memory components increases, the price increases and becomes less common. Even if high integration is advanced by miniaturization of the semiconductor process, there is a problem that damage to the insulating layer is accelerated by miniaturization. A device for increasing the number of empty memory cells within a limited number of memory cells is required.

  When a write command is received from the host device, the number of times of writing to the physical position and logical position where writing is performed is counted and stored as write data information. In addition, the semiconductor disk device itself has a function of reading out already stored write data information and determining whether the write data is frequently updated data. The semiconductor disk device records data in an optimal memory cell by an optimal recording method based on the determination.

  That is, a logical position, which is an access unit viewed from the host device, is assigned to a physical position in the flash memory, and in a storage device control method using a flash memory in which the SLC method and the MLC method are selectively used as a recording method, At this time, physical position determination and recording method determination are performed.

  In the physical position determination, the first management for managing the number of times the flash memory is written to a plurality of physical positions, the physical position information of the memory block in which the information on the logical position to be written is recorded, and the physical position The difference between the second management for managing the number of times of writing, the number of times of writing at the physical position managed by the second management, and the number of times of writing at the physical position that is the smallest of the number of times of writing managed by the first management Is compared with a predetermined threshold, and if the difference does not exceed the predetermined threshold, the physical position of the memory block in which the information on the logical position to be written is recorded is determined as the write position, and the difference is When the predetermined threshold value is exceeded, the data of the block with the minimum write count is copied to the block with the maximum write count among the empty blocks of the memory block. The data of the minimum write count block is erased and determined as a new write position, and the physical position where the information on the logical position to be written managed by the second management is recorded is the new write position. To the physical position of the block with the minimum number of writes.

  In the recording method determination, the number of times of writing of the logical position to be written is referred to, the recording method of the physical position of the memory block in which the information of the logical position to be written is written is confirmed, and the writing of the logical position is performed. When the number of times of writing at the logical position does not exceed the predetermined threshold, the SLC method is selected. When the number of times of writing at the logical position exceeds the predetermined threshold, the MLC method is selected. .

  The information processing apparatus does not always write to the storage area, and there is a large amount of information that only reads basic software, application data, and the like. These pieces of information are generally recorded for a long time in the same logical position.

  The semiconductor disk device of the present invention records data that is not updated thereafter from its own write data information by the MLC method, and suppresses the consumption of memory cells. As a result, the number of empty memory cells can be increased, and by combining with wear leveling control, empty memory cells can be preferentially allocated to data with a high update frequency. As a result, the life of the semiconductor disk device having the same number of memory cells can be extended as compared with the conventional case.

Overall view of information processing apparatus equipped with semiconductor disk device of embodiment Wear leveling control block diagram of semiconductor disk device Data processing block diagram of semiconductor disk device of embodiment Physical position determination processing flowchart of semiconductor disk device of embodiment Memory cell recording method and recording state diagram of semiconductor disk device Recording method determination processing flowchart of the semiconductor disk device of the embodiment Write processing flowchart of semiconductor disk device of embodiment Recording system and data transition diagram of semiconductor disk device of embodiment

  Hereinafter, embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 1 is an overall view of an information processing apparatus equipped with a semiconductor disk device according to an embodiment of the present invention. The constituent elements include a CPU 101, a main memory 102, an interface control IC 103, a SATA bus 104, and a semiconductor disk device 105. The interface control IC 103 includes a main controller 106 that supervises information from each interface, a SATA controller 107 that converts processing requests into SATA standard commands and data, and a command control unit 108 that manages commands sent to the SATA standard disk device. Is done.

  The semiconductor disk device 105 includes a SATA controller 109 that receives and responds to SATA commands and data, a command control unit 110 that manages the received SATA commands, a memory controller 111 that controls the actual operation of the semiconductor disk device, and a data storage location. The semiconductor memory 112 is configured.

  This information processing apparatus is realized by the CPU 101 executing the program and data expanded in the main memory 102. When new information that is not on the main memory 102 is necessary, or when information cannot be stored in the main memory 102, the CPU 101 makes a processing request to the main controller 106 of the interface control IC 103. When a processing request arrives, it is sent from the SATA controller 107 to the semiconductor disk device 105 as a SATA command. At this time, the command control unit 108 manages the command response contents and response time from the semiconductor disk device 105 in cooperation with the SATA controller 107.

  The semiconductor disk device 105 receives the SATA command by the SATA controller 109 and develops the information to the command control unit 110 and the memory controller 111. The memory controller 111 executes a processing request to the semiconductor memory 112 and returns a result to the interface control IC 103 via the SATA controller 109. The main controller 106 sends the response result from the semiconductor disk device 105 to the CPU 101, and if there is data, sends it to the main memory 102. It can operate as an information processing apparatus by repeating without repeating the above.

  FIG. 2 is a block diagram showing wear leveling control of the semiconductor magnetic disk. As described above, the semiconductor disk device preferentially writes to a memory cell having a physically small number of times of writing when writing. In the overall view of the embodiment of the present invention shown in FIG. 1, the memory controller 111 controls this wear leveling control. In this figure, the flash memory 205 has twelve memory addresses, and two of them are described as one block, which is a writing unit of the semiconductor memory, and is composed of six memory blocks 206 to 211. The memory blocks 209 and 210 are empty blocks with no data.

  In more detail, a write request 201 from a higher-level device is first delivered to the memory controller 203 together with write data 202. This data is assumed to be new data of the memory address 212. The memory controller 203 refers to the write count table 204 and searches the semiconductor memory 205 for a memory block with a small physical write count and a memory block with a large write count.

  As a result of the search for the number of writes, if the number of writes in the memory block 211 is small, the data in the memory block 211 is copied to the empty block 210. As a free block at the time of copying, a block with a large number of writing times is preferentially selected. Thereafter, the data of the memory block 208 to be written is read, the data at the memory address 212 is rewritten to the write data 202, and the data is written into the memory block 211.

  As described above, in the semiconductor disk device, the number of times of physical position writing is made uniform by replacing the position where the physical number of times of writing is small and the position where the number of physical writes is large. Since wear leveling control always uses empty blocks, the longer the number of empty blocks with a small number of physical writes, the longer the lifetime of the semiconductor disk device as a whole. The disadvantage is that since the semiconductor memory performs writing in units of memory blocks in which several memory cells are gathered, the entire memory block must be rewritten when it is partially rewritten. Even if data that is frequently rewritten and data that is not rewritten are mixed, the entire data must be rewritten. Therefore, optimization of the data position on the memory and securing of free blocks are important for efficient wear leveling control.

FIG. 3 is a data processing block diagram of read / write of the semiconductor disk device in the embodiment of the present invention. This block diagram illustrates data processing performed by the command controller 110 and the memory controller 111 when a read / write process is requested to the semiconductor disk device 105. Read / write by the command execution controller 301 in the command controller 110. When the request is received, it is expanded in each part of the memory controller 111 as a processing request 302 from the host device. In the case of reading, the read / write control unit 304 expands a logical address indicating a logical position to be read from the physical / logical position control unit 305, and obtains the physical position of the semiconductor memory where the data is actually stored. Based on the information obtained here, the requested data is read from the corresponding position in the memory chip 308 and temporarily recorded in the data buffer 303.

  The temporarily recorded data is checked for errors by the error detection / correction control unit 309. If no error is detected, the data is transmitted to the command response control unit 310. If an error is detected, error data correction or retry is attempted, and if it can be repaired, the repair data is sent to the command response control unit 310 if it cannot be repaired.

  In the case of writing, first, the data transferred as the processing request 302 from the host device is temporarily recorded in the data buffer 303. After that, as in the case of reading, the read / write control unit 304 expands a logical address indicating a logical position where writing is performed with respect to the physical / logical position control unit 305.

  The physical / logical position control unit 305 controls the number of physical position writes in the entire semiconductor memory in consideration of the write number limit, determines a memory block with a small number of physical position write times, and reads and writes the physical position. To the unit 304. At the same time, the logical address is developed in the recording method control unit 306.

  The recording method control unit 306 counts the number of times of writing for each logical address in order to control the number of times of writing at the logical position, and determines the recording method to be used for the current writing from the number of times of writing at the logical position and the latest writing logical address. Then, the data is transmitted to the read / write control unit 304.

  The write data information table 307 manages the number of physical position writes controlled by the physical / logical position control unit 305, the number of logical position writes controlled by the recording method control unit 306, and the latest write logical address in separate tables. is doing.

  Based on the information obtained above, the data temporarily recorded in the data buffer 303 is written to the corresponding position in the memory chip 308, and the execution result is transmitted to the command response control unit 310 in the command control unit 110. The command response control unit 310 sends the received execution results and data to the higher-level device and makes a response to the processing request.

  FIG. 4 is a processing flow diagram of physical position determination in consideration of the number of times of writing of the physical position of the memory block performed by the physical / logical position control unit 305 when performing the writing process in the present embodiment.

  First, as a periodic process that does not depend on a request from the host device, the write data information recorded in the write data information table 307 is read, and the physical location of the memory block with the minimum number of writes and the number of times are recorded ( Step 401).

  When the logical address to be written is expanded from the read / write control unit 304, the physical position of the memory block including the memory cell in which the expanded logical address information is recorded is determined from the physical position / logical address association information. Find out. The current execution of writing to the memory block at this physical location is recorded in the write data information, and the current number of writes to this memory block is read (step 402).

  Next, the difference between the write count value of the memory block read in step 402 and the write count value of the minimum block read in step 401 is collated with a predetermined threshold (step 403).

  If the threshold is not exceeded, the physical location of the memory block in step 402 is finally determined as the write location as it is (step 404).

  If the threshold is exceeded, the memory block read in step 402 indicates that the number of times of writing is large, and the writing position needs to be changed. Therefore, the data of the smallest block is copied to the block with the maximum number of writes among the empty blocks (step 405), and the data of the smallest block is erased. The physical position of the minimum block is determined as a new write position, and the logical address of the memory block read in step 402 and the logical address of the minimum block are changed (step 406).

  This threshold is a value that determines the frequency with which physical position determination is performed. The smaller the threshold value, the more frequently the writing position is changed in steps 405 and 406, and the number of times of writing in all the memory blocks is controlled to be uniform, and the accuracy of controlling the number of times of writing is increased. However, if the writing position is changed too much, the writing process becomes complicated, and the influence on the writing process performance cannot be ignored. It is necessary to set a threshold value in consideration of performance and lifetime required for the apparatus.

  As described above, the logical address to be written this time is written in a memory block with a small physical write count, and the write memory limit of the semiconductor memory can be effectively utilized.

  FIG. 5 shows a memory cell recording method (a) and a recording state diagram (b) at the time of a writing process controlled by the read / write control unit 304 and the recording method control unit 306 in this embodiment.

FIG. 5A is a recording state diagram of the SLC method. The memory cell records data in a charged state of the floating gate layer. In order to represent the recorded state, when the number of memory cells is plotted on the vertical axis and the threshold voltage V _th is plotted on the horizontal axis, the state is not charged [0]. 501 and charged state [1] 502. Since the threshold voltage varies depending on the memory cell, the threshold voltage distribution is almost normal. The read / write control unit 304 records 1-bit data of 0 or 1 by controlling the charging state of the memory cell as [0] and [1] (503).

  FIG. 5B is a recording state diagram of the MLC method. In the MLC system, in addition to the uncharged state [0] 504, there are three types of charged states [1] to [3] depending on the voltage (505 to 507). The read / write control unit 304 records the 2-bit data in one memory cell as in 504 by finely controlling the charging state to be [0] to [3]. The recording method control unit 306 selects an optimum recording method for each writing from these two types of recording methods.

  FIG. 6 is a processing flowchart of recording method determination in consideration of the number of times of writing at the logical position performed by the recording method control unit 306 when performing the writing processing in the present embodiment.

  The logical address is expanded from the physical / logical position control unit 305, and the execution of the current write is recorded in the write data information recorded in the write data information table 307, and this logical address is used to know the number of times the logical position is written. Is read out (step 601).

  Further, the physical position of the memory block including the memory cell to which the logical address information is written is determined, and the recording method of the memory block is confirmed (step 602).

  Next, the write count read in step 601 is collated with a determined threshold value (step 603).

  This threshold value is calculated from the physical write count limit of the memory cell in the MLC method and the device operating time. In this embodiment, when the number of physical writes in the MLC method of the memory cell is 10,000 times and the device life is assumed to be 5 years, the write frequency per day is calculated 10,000 times / (365 days × 5 years) = Even if the same memory cell is continuously updated at a rate of about 5 times per day, the device life can be satisfied. Based on the writing frequency that can satisfy the device life, the threshold for the number of times of writing for each logical address is calculated by the standard writing frequency per day × the number of working days and set. A logical address exceeding the threshold is determined as a logical address in which data having a high update frequency is stored, and an SLC method having a physical write frequency limit of about 10 times is selected as a recording method (step 604). Conversely, the logical address below the threshold is determined as the logical address where data with a low update frequency is stored, and the MLC method is selected as the recording method (step 605).

  However, when it is confirmed that there are a plurality of the same address or surrounding addresses by referring to the write address table that records the most recent write logical address in the write data information (step 606), a large number of the latest writes are performed. The SLC method is selected regardless of the number of times of writing for each logical address. As described above, the writing method is determined (step 607), and at the same time, the logical address to be written this time is registered in the writing address table (step 608), which is used as a judgment material for determining the recording method for the subsequent writing. The data update frequency of the information processing apparatus varies from those updated every hour, such as program log data and management data, to those having an update frequency of once a month or less, such as software program body data. Since these are continuously recorded at the same logical address, the update frequency of the write data can be determined from the number of times of writing for each logical address.

  FIG. 7 is a processing flow of the semiconductor disk device when the writing process is performed in this embodiment. As described above, the physical position of the memory block to be written and the recording method are determined before performing the writing process (steps 701 to 702).

  Here, the processing flow changes depending on the recording method of the physical position where writing is performed (step 703).

  If the recording method does not change, writing and erasing are performed on the determined physical position as they are (step 704), and the process ends.

  When the recording method changes from before, the processing flow further changes depending on whether the MLC method is changed to the SLC method or vice versa (step 705).

  When the MLC method is changed to the SLC method, more memory blocks are required even if the same data is recorded. Therefore, in addition to the physical position determined in step 701, a spare block for a defective block is allocated for the shortage, and writing and erasing are performed (step 706). Thereafter, the logical address is appropriately associated with the physical position corresponding to the memory block in which writing has been performed (step 707), and the processing ends. In this way, the SLC method is positively used for addresses with a high update frequency to suppress the deterioration of the semiconductor memory.

  On the other hand, when the SLC method is changed to the MLC method, the memory cells in the memory block remain. Therefore, the number of times of writing at the logical position of the nearby logical address where the same type of data is considered to be recorded is searched (step 708), and the data of the logical address with the lower number of times of writing is read (step 709). By writing the newly read data together, erasing the memory block of the original logical address with a small number of physical location writes (step 710), appropriately associating the logical address (step 711), and completing the process, Free blocks can be increased. An empty block can be used as a spare block for an address with a high update frequency.

  FIG. 8 is a recording system (a) and data transition diagram (b) when the writing process is performed in the present embodiment.

  FIG. 8A is a data transition diagram when the write target memory block is changed from the MLC method to the SLC method as a result of determining that the update frequency of the data to be written is high in step 702 (steps 706 and 707). .

  In the following description, it is assumed that data for four addresses is recorded in the memory blocks 801 to 804 by the MLC method, the memory blocks 805 and 806 are empty blocks, and new write data 807 updates partial data in the memory block 804.

  If it is determined in step 701 that the memory block 803 is determined as a write physical location, first, the data in the memory block 803 is copied to the empty block 805. At the same time, in order to change the recording method from the MLC method of 2-bit recording to the SLC method of 1-bit recording, the data in the memory block 804 is divided into two.

  Thereafter, one of the two divided data is written into the memory block 803 and the other is written into the empty block 806. After the writing is completed, the data in the memory block 804 is erased, and the logical address is completed by associating with the new physical location. As described above, it is possible to subdivide frequently updated data by recording in the SLC method, but it consumes empty blocks.

  On the other hand, FIG. 8B shows the data transition when the write target memory block is changed from the SLC method to the MLC method (steps 708 to 711) as a result of determining that the update frequency of the data to be written is low in step 702. FIG.

  In the following description, it is assumed that data for two addresses is recorded in the memory blocks 808 to 813 by the SLC method, the memory blocks 812 and 813 are vacant blocks, and new write data 814 updates the data in the memory block 811.

  If it is determined in step 701 that the memory block 810 is determined as a write physical location, the data in the memory block 810 is copied to the empty block 812 as in the case of FIG. Since the recording method changes from the SLC method of 1-bit recording to the MLC method of 2-bit recording, twice the data is required for recording. Therefore, the memory block 809 in which data with a small number of logical position writes is recorded is searched for in the write number search in step 708.

  Thereafter, the data in the memory block 809 is read and written together with the new data 814 in the memory block 810. After the writing is completed, the data in the memory blocks 809 and 811 are erased, and the logical address is completed by associating it with the new physical location. By recording in the MLC method in this way, data with low update frequency can be written together and free blocks can be increased.

  As described in the present embodiment, it is possible to control the recording method based on the update frequency from the data update frequency element derived from the number of writes for each logical address. Data with a low update frequency is written together by the MLC method to secure a free block, and the free block formed thereby is used for data with a high update frequency, so that the substantial device life can be extended.

  In general, data with high update frequency has a small amount of data, and software / program body data with low update frequency has a large amount of data, and it can be expected that a large number of free blocks can be secured by this embodiment. Further, since the data in the memory block is grouped according to the update frequency, the operation of rewriting a part of the memory block as in the conventional wear leveling control is reduced, and there is an effect of suppressing unnecessary rewriting. Combining with the conventional concept of wear leveling control that replaces the memory block based on the number of writes at the physical position of the memory block enables more optimized write control.

  In the embodiment described above, the SATA specification has been described as the interface specification. However, other specifications can be realized regardless of the interface of the semiconductor disk device. Further, as a physical position determination method, a specification in which a portion where data has already been recorded is a target of the number of times of writing search, but a specification using only empty blocks may be used in consideration of the effect on performance due to data copy overhead. In addition, the recording method determination is made with two types of recording methods, the SLC method and the MLC method, but it can also be realized by subdividing the threshold and increasing the recording method such as 2-bit MLC, 3-bit MLC.

101: CPU, 102: main memory, 103: interface control IC, 104: SATA bus, 105: semiconductor disk device, 106: main controller, 107: SATA controller of interface control IC, 108: command control unit of interface control IC, 109: SATA controller of semiconductor disk device, 110: Command control unit of semiconductor disk device, 111: Memory controller, 112: Semiconductor memory, 201: Write request from host device, 202: Write data, 203: Memory controller, 204: Write count table, 205: Semiconductor memory, 206 to 211: Memory block, 212: Write target memory address, 301: Command execution control unit, 302: Processing request from host device 303: Data buffer, 304: Read / write control unit, 305: Physical / logical position control unit, 306: Recording method control unit, 307: Write data information table, 308: Memory chip, 309: Error detection / correction control unit, 310 : Command response control section

Claims (5)

In the storage device control method using flash memory, which assigns the logical position, which is the access unit seen from the host device, to the physical location of the flash memory, and uses the SLC method and the MLC method as the recording method.
During the writing process, physical position determination and recording method determination are performed,
In the physical position determination,
A first management for managing the number of writes to a plurality of physical locations of the flash memory;
Second management for managing the physical position information of the memory block in which the information of the logical position to be written is recorded and the number of times the physical position is written;
The difference between the number of writes at the physical position managed in the second management and the number of writes at the physical position that is the minimum of the number of writes managed in the first management is checked against a predetermined threshold,
When the difference does not exceed a predetermined threshold, the physical position of the memory block in which the information on the logical position to be written is recorded is determined as the writing position,
If the difference exceeds a predetermined threshold, copy the block data with the minimum write count to the block with the maximum write count among the empty blocks in the memory block, erase the data in the block with the minimum write count, and perform a new write Determining the position, and changing the physical position where the information of the logical position to be written, which is managed in the second management, is recorded, to the physical position of the block of the minimum number of times of writing that is the new writing position,
In the recording method determination,
Refer to the write count of the logical position to be written,
Confirm the recording method of the physical position of the memory block to write the information of the logical position to be written,
Collating the number of writes of the logical position with a predetermined threshold,
If the number of writes of the logical position does not exceed a predetermined threshold, select the SLC method,
A method for controlling a storage device, wherein the MLC method is selected when the number of times the logical position is written exceeds a predetermined threshold. The storage device
A physical / logical position control unit for performing the physical position determination;
A recording method determination unit for performing the recording method determination;
A write data information table for managing the number of writes of the physical position and the number of writes of the logical position;
2. The storage device according to claim 1, further comprising: a write control unit that performs a recording process with a recording method selected by the recording method determination unit at a writing position determined by the physical / logical position control unit. Control method. In the recording method determination,
3. The storage device control method according to claim 2, wherein the SLC method is selected when there is a plurality of the same logical position or surrounding logical positions with reference to the write data information table. The recording method selected in the recording method determination is
If there is no change from the previous writing process, continue writing / erasing to the determined physical location,
When changing from the previous writing process and switching from the MLC method to the SLC method, further assigning a spare block, performing writing and erasing, appropriately associating a logical address with the physical position corresponding to the memory block that has been written,
If the SLC method changes to the MLC method from the previous writing process, the number of times of writing at the logical position of the nearby logical address where the same type of data is supposed to be recorded is searched, and the data of the logical address with a low number of times of writing is searched. 2. The method of controlling a storage device according to claim 1, wherein newly read data is written together, the memory block of the original logical address with a small number of physical position writes is erased, and the logical address is associated. . In the storage device using the flash memory that assigns the logical position, which is the access unit seen from the host device, to the physical position of the flash memory and uses the SLC method and the MLC method separately as the recording method,
The storage device includes a physical / logical position control unit that performs physical position determination, a recording method determination unit that performs recording method determination, a write data information table that manages the number of physical position writes and the number of logical position writes, A write control unit that performs a recording process with a recording method selected by the recording method determination unit at a writing position determined by the physical / logical position control unit;
The physical / logical position control unit, as the physical position determination,
A first management step for managing the number of writes to a plurality of physical locations of the flash memory;
A second management step for managing the physical position information of the memory block in which the information of the logical position to be written is recorded and the number of times of writing the physical position;
A step of comparing a difference between the number of times of writing at the physical position managed by the second management and the number of times of writing at the physical position that is the minimum of the number of times of writing managed by the first management with a predetermined threshold value. Run,
When the difference does not exceed a predetermined threshold, the physical position of the memory block in which the information on the logical position to be written is recorded is determined as the writing position,
If the difference exceeds a predetermined threshold, copy the block data with the minimum write count to the block with the maximum write count among the empty blocks in the memory block, erase the data in the block with the minimum write count, and perform a new write Determining the position, and changing the physical position where the information of the logical position to be written, which is managed in the second management, is recorded, to the physical position of the block of the minimum number of times of writing that is the new writing position,
The recording method determination unit, as the recording method determination,
A reference step for referring to the number of times of writing at the logical position to be written;
A confirmation step of confirming a recording method of a physical position of a memory block in which information on a logical position to be written is written;
Performing a collation step of collating the number of writes of the logical position with a predetermined threshold;
If the number of writes of the logical position does not exceed a predetermined threshold, select the SLC method,
The memory device, wherein the MLC method is selected when the number of times the logical position is written exceeds a predetermined threshold.

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