JP6329185B2 - Memory control circuit, memory control system, memory control method, and memory control program - Google Patents

Description

  The present invention relates to a technique for controlling data writing to a rewritable nonvolatile memory.

  In embedded systems and the like, a rewritable nonvolatile memory such as a NOR (Negative OR) type flash memory or a NAND (Negative AND) type flash memory is widely used. The embedded system operates based on a control program, setting information, and the like stored in such a flash memory (rewritable nonvolatile memory). Hereinafter, in the present application, such a flash memory is referred to as FROM (Flash Read Only Memory).

  It is known that the nonvolatile performance of the FROM gradually deteriorates as data is written and erased many times. FIG. 6 is a diagram conceptually illustrating the relationship between the number of rewrites to the FROM, the guaranteed data retention time by the FROM, and the FROM temperature. The data retention guarantee time (hereinafter referred to as guarantee time) is an elapsed time that can guarantee that the data is not lost due to volatilization after the data is stored in the FROM.

  As shown in FIG. 6, when the FROM temperature is, for example, 55 ° C. (° C. represents a Celsius temperature), the guaranteed time varies depending on the number of rewrites to the FROM. That is, while the rewriting of data is performed N times (N is any natural number determined by the characteristics of FROM), the guaranteed time of FROM is 10T hours (T is any number determined by the characteristics of FROM), The guaranteed time of FROM in which data is rewritten 10N times decreases to 1T time. Further, as shown in FIG. 6, the guaranteed time decreases as the temperature of the FROM increases. Therefore, in a system using FROM, a technique for performing data writing control considering that the non-volatile performance of the FROM gradually deteriorates is necessary so that important data is not lost.

  As an example of such a technique, in Patent Document 1, when an update data write request is received for the first logical storage area to be backed up, the first data is maintained in a state where the data before update is maintained. A storage system for managing the physical storage area as a backup storage area is disclosed. At this time, the storage system newly allocates a second physical storage area to the first logical storage area and writes update data. When this storage system receives an update data write request for the second logical storage area that is not targeted for backup, the storage system stores the third physical storage area allocated to the second logical storage area as invalid. Manage as an area. At this time, the storage system writes update data to the fourth physical storage area newly allocated to the second logical storage area.

  Japanese Patent Laid-Open No. 2004-228561 divides a data recording area into a plurality of independently rewritable storage blocks, and assigns a semiconductor storage allocated to an active block used for data recording during normal operation and a spare block not used during normal operation. An apparatus is disclosed. This semiconductor memory device counts the number of rewrites for each block or for all blocks, and averages the rewrite frequency by replacing one of the active blocks with a spare block for each preset number of times. As a spare block to be replaced, a block that has become the spare in the past or has the smallest number of rewrites is selected.

Special Table 2013-541743 Japanese Unexamined Patent Publication No. 08-096589

  For example, in an embedded system in which a control program is stored in the FROM, the nonvolatile memory included in the FROM deteriorates, and the system cannot be operated when the control program is lost. Therefore, it is necessary to store data in the FROM so as to avoid such a problem.

  FIG. 7 is a diagram illustrating a first example of a general method for updating stored data in consideration of a case where data stored in the FROM is lost. The FROM 50 illustrated in FIG. 7 includes 512 storage unit blocks 50-1 to 50-512. The storage unit blocks 50-1 to 50-512 can be independently rewritten.

  As shown in FIG. 7A, initially, the storage blocks 50-1 and 50-512 store a shipping program, and the storage block 50-2 stores setting data related to the shipping program. The storage blocks 50-3 to 50-511 are assumed to be empty. When the shipping program is updated in this state, as shown in FIG. 7B, the updated program is stored in the storage block 50-3 in an empty state and stored in the storage block 50-1. The existing factory program is deleted. The storage block 50-512 continuously stores the shipping program regardless of the update of the program. In the state shown in FIG. 7B, when the program is further updated, the updated program is stored in an empty storage block 50-4 (not shown) and stored in the storage block 50-3. The program that is being deleted is deleted.

  In the method illustrated in FIG. 7, each time the program is updated, the storage destination is moved to one of the empty storage blocks 50-1 to 50-511 by the round robin method. Since the storage block 50-512 continuously stores the program at the time of shipment regardless of the update of the program, data rewriting to the storage block 50-512 does not occur. In this case, since the non-volatile performance of the storage block 50-512 is hardly deteriorated, the possibility that the shipping program stored in the storage block 50-512 is lost is very small. Therefore, even if the latest program stored in any of the storage blocks 50-1 to 50-511 whose nonvolatile performance gradually deteriorates every time the program is updated is lost in the storage block 50-512. The stored shipping program can be used to operate the system. However, when there is a large amount of update from the shipping program, there is a problem that the system may not function normally with the shipping program.

  FIG. 8 is a diagram illustrating a second example of a general method for updating stored data in consideration of a case where data stored in the FROM is lost. The second method example shown in FIG. 8 also uses the FROM 50 shown in FIG.

  As shown in FIG. 8A, initially, the storage blocks 50-1 and 50-2 store a shipping program, and the storage block 50-3 stores setting data related to the shipping program. The storage blocks 50-4 to 50-512 are assumed to be empty. When the shipping program is updated in this state, the updated program is stored in the empty storage block 50-4 and stored in the storage block 50-1, as shown in FIG. 8B. The existing factory program is deleted. At this time, the storage block 50-2 continuously stores the shipping program. In the state shown in FIG. 8B, when the program is further updated, the updated program is stored in an empty storage block 50-5 (not shown) and stored in the storage block 50-2. The shipped program is deleted.

  Also in the second method example shown in FIG. 8, each time the program is updated, the storage destination is moved to one of the empty storage blocks 50-1 to 50-512 by the round robin method. At this time, the FROM 50 stores the latest program and the previous version of the program in any of the storage blocks 50-1 to 50-512. In the second method example shown in FIG. 8, it is possible to avoid the problem that the system may not function normally in the shipping program, which the first method example shown in FIG. 7 has. However, in this second method example, each time the program is updated, the non-volatile performance of the storage blocks 50-1 to 50-512 gradually deteriorates. There is a problem that both versions of the program may be lost.

  As described above, when a storage block that is not updated after shipment is provided so that the nonvolatile performance does not deteriorate, the latestness of the data stored in the storage block is lowered. In the present application, the term “newness” represents the degree of newness of data based on the latest state. And when updating data so that the newness of data does not fall, there exists a problem that the non-volatile performance of a storage block falls. In an actual system, it is required to avoid both the loss of data and the decrease in data freshness, and it is a problem to realize this. Patent documents 1 and 2 do not mention this subject. The main object of the present invention is to provide a memory control circuit or the like that solves this problem.

  A memory control circuit according to an aspect of the present invention includes the first and second memory blocks each having a first and a second memory block each having a non-volatile performance depending on the number of times data has been written. When data is written to the storage block, the number of times measuring means for measuring the number of times of writing to the first storage block, and the number of times of writing measured by the number of times measuring means are predetermined. When the determination unit determines whether or not the number of times condition is satisfied, and the determination unit determines that the number of times of writing satisfies the number of times, the data written to the first storage block is And writing means for writing to the second storage block.

  In another aspect of achieving the above object, a memory control method according to an aspect of the present invention provides first and second memories each having a non-volatile performance depending on the number of times data has been written by an information processing device. When data is written to the first storage block in the rewritable nonvolatile memory having a block, the number of times of writing to the first storage block is measured, and the measured It is determined whether or not the number of times of writing satisfies a predetermined number of times, and when it is determined that the number of times of writing satisfies the number of times, the data written to the first storage block is Write to the storage block.

  Further, in a further aspect to achieve the above object, a memory control program according to an aspect of the present invention has first and second storage blocks that individually have nonvolatile performance depending on the number of data writes up to now. When the data is written to the first storage block in the rewritable nonvolatile memory, the number measurement process for measuring the number of times of writing to the first storage block, and the number measurement A determination process for determining whether or not the number of times of writing measured by the process satisfies a predetermined number of times, and when the determination process determines that the number of times of writing satisfies the number of times, A writing process for writing the data written in the storage block to the second storage block; Is a program for executing.

  Furthermore, the present invention can also be realized by a computer-readable non-volatile recording medium storing such a memory control program (computer program).

  The present invention makes it possible to avoid the loss of the data while avoiding a decrease in the freshness of the data stored in the rewritable nonvolatile memory.

1 is a block diagram showing a configuration of a memory control system 1 according to a first embodiment of the present invention. 4 is a flowchart showing an operation in which the memory control circuit 10 according to the first embodiment of the present invention writes data received from the CPU 2 to the FROM 20. 4 is a flowchart showing an operation in which the memory control circuit 10 according to the first embodiment of the present invention writes data stored in a normal access block to an emergency access block 22; It is a block diagram which shows the structure of the memory control circuit 30 which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the information processing circuit which can execute the memory control circuit which concerns on each embodiment of this invention. It is a figure which illustrates notionally the relationship between the frequency | count of rewriting of flash memory, data retention guarantee time, and the temperature of flash memory. It is a figure which shows the example of the general 1st method of updating the stored data in consideration of the case where the data stored in flash memory lose | disappear. It is a figure which shows the example of the 2nd general method of updating the stored data in consideration of the case where the data stored in flash memory lose | disappear. It is a figure which illustrates notionally the relationship between the time after starting use about the FROM20 which concerns on 1st Embodiment, and data retention guarantee time.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram conceptually showing a memory control system 1 according to the first embodiment of the present invention. The memory control system 1 roughly includes a memory control circuit 10 and a FROM 20. The memory control system 1 is communicably connected to a CPU (Central Processing Unit) 2. A plurality of CPUs 2 may be connected to be communicable with the memory control system 1. The memory control circuit 10 is a circuit that processes data read requests and data write requests from the CPU 2 to the FROM 20. The memory control system 1 may be constructed, for example, in one semiconductor chip.

  The FROM 20 is a flash memory that stores data used by the CPU 2. The FROM 20 includes a normal access block (first storage block) 21 and an emergency access block (second storage block) 22. The normal access block 21 and the emergency access block 22 can rewrite stored data independently of each other. The normal access block 21 is a storage block for storing data updated in response to a request from the CPU 2. The emergency access block 22 is a storage block that stores a backup of the data in case the data stored in the normal access block 21 is lost.

  The normal access block 21 includes 511 sub-blocks 21-1 to 21-511. The sub blocks 21-1 to 21-511 can rewrite stored data independently of each other. The number of sub-blocks included in the normal access block 21 is not limited to 511, and can take different values depending on the storage capacity of the FROM 20 or the like. The number of subblocks may be one.

  As described above, the sub-blocks 21-1 to 21-511 and the emergency access block 22 can rewrite stored data independently of each other. Therefore, each of these storage blocks has a non-volatile performance that depends on the number of times data is written to the own storage block up to the present.

  When the memory control circuit 10 according to the present embodiment updates data stored in the subblock 21-i (i is an integer from 1 to 511) in accordance with a request from the CPU 2, the unused subblock The updated data is stored in 21-j (j is an integer from 1 to 511 different from i). At this time, the memory control circuit 10 deletes the pre-update data stored in the sub-block 21-i. For example, each time the memory control circuit 10 updates data, the storage destination of the data is moved to one of the empty sub blocks 21-1 to 21-511 by the round robin method. Select the sub-block that is the storage destination. Note that the memory control circuit 10 may select a sub-block that is a storage destination by a different method.

  The memory control circuit 10 according to the present embodiment includes a number measurement unit 11, a time measurement unit 12, a temperature measurement unit 13, a determination unit 14, and a writing unit 15. The frequency measurement unit 11, the determination unit 14, and the writing unit 15 may be an electronic circuit, or may be realized by a computer program and a processor that operates according to the computer program. The time measuring unit 12 is a device that includes a clock (time measuring means). The temperature measurement unit 13 is a device that includes a temperature sensor.

  The number measuring unit 11 calculates the number of times data has been written to the normal access block 21 (the number of times of writing), that is, the total number of times of writing to the sub-blocks 21-1 to 21-511. taking measurement. The count measuring unit 11 resets the count value, which is a measurement result, to an initial value (for example, 0) every time the number of writings reaches a predetermined count threshold determined by a system administrator or the like. For example, when the number-of-times threshold is set to the number of times of writing to the sub-blocks 21-1 to 21-511 10 times, the value is 5110 times. The number measurement unit 11 notifies the determination unit 14 of the measured count value.

  The time measuring unit 12 measures an elapsed time from the last writing to the normal access block 21 at a predetermined timing (for example, periodically). The time measurement unit 12 notifies the determination unit 14 of the measured elapsed time. The time measurement unit 12 resets the elapsed time as a measurement result to an initial value (for example, 0) every time the elapsed time reaches a predetermined time threshold determined by a system administrator or the like. The time threshold is preferably a data retention guarantee time depending on the nonvolatile performance of the FROM 20, for example.

  The temperature measurement unit 13 measures the temperature of the FROM 20 via a temperature sensor installed on the surface of the FROM 20 or the like. The temperature measurement unit 13 notifies the determination unit 14 of the measured temperature of the FROM 20.

  The determination unit 14 determines whether the count value (number of writings) notified from the number measurement unit 11 satisfies a predetermined number of times. This number condition is, for example, whether or not the count value has reached the number threshold. The determination unit 14 determines whether or not the elapsed time notified from the time measurement unit 12 has reached a time threshold value. The determination unit 14 notifies the writing unit 15 of these determination results.

  The determination unit 14 may gradually reduce the number threshold every time the count value reaches the number threshold. For example, it is assumed that the number threshold is initially set to the number of times (ie, 5110 times) when writing is performed 10 times for each of the sub-blocks 21-1 to 21-511. In this case, after the count value reaches 5110 times, the determination unit 14 sets the number threshold, for example, the number of times when writing is performed 9 times for each of the sub-blocks 21-1 to 21-511 (that is, 4599 times). ). Thereafter, after the count value reaches 4599 times, the determination unit 14 writes the threshold value for the number of times, for example, when the sub-blocks 21-1 to 21-511 are written eight times each (that is, 4088 times). Make it smaller. The determination unit 14 gradually decreases the number threshold by repeating the same process. Similarly, the determination unit 14 may gradually decrease the time threshold every time the count value reaches the number-of-times threshold.

  The determination unit 14 may change the content of the frequency condition according to the temperature of the FROM 20 notified from the temperature measurement unit 13. For example, the determination unit 14 decreases the number-of-times threshold as the temperature of the FROM 20 increases. The determination unit 14 may change the time threshold according to the temperature of the FROM 20 notified from the temperature measurement unit 13. For example, the determination unit 14 decreases the time threshold as the temperature of the FROM 20 increases.

  When the determination unit 14 determines that the number of times of writing satisfies the number of times, the writing unit 15 outputs the data received from the CPU 2 written in the sub-block 21-j in the normal access block 21 in an emergency state. Write to the access block 22. The writing unit 15 also stores the data written in the sub-block 21-j in an emergency when the determining unit 14 determines that the elapsed time measured by the time measuring unit 12 has reached the time threshold. Write to the access block 22.

  Next, the operation (processing) of the memory control circuit 10 according to the present embodiment will be described in detail with reference to the flowcharts of FIGS.

  FIG. 2 is a flowchart illustrating an operation in which the memory control circuit 10 according to the embodiment writes data received from the CPU 2 in the FROM 20.

  The writing unit 15 writes the updated data received from the CPU 2 in the sub-block 21-j (Step S101). The writing unit 15 erases the pre-update data stored in the sub-block 21-i (Step S102). The number measuring unit 11 adds 1 to the count value (step S103). The determination unit 14 compares the count value with the frequency threshold (step S104).

  If the count value is not the number-of-times threshold (No in step S105), the entire process ends. When the count value is a threshold value for the number of times (Yes in step S105), the number measuring unit resets the count value to 0 (step S106). The writing unit 15 writes the updated data received from the CPU 2 to the emergency access block 22 (step S107), and the entire process ends.

  FIG. 3 is a flowchart illustrating an operation in which the memory control circuit 10 according to the embodiment writes the data stored in the normal access block 21 to the emergency access block 22.

  The time measurement unit 12 measures the elapsed time since the last writing to the emergency access block 22 at a predetermined timing (step S201). The determination unit 14 compares the elapsed time with a time threshold value (step S202).

  If the elapsed time is not equal to or greater than the time threshold (No in step S203), the entire process returns to step S201. When the elapsed time is equal to or greater than the time threshold (Yes in step S203), the time measurement unit 12 resets the measured value of elapsed time to 0. The writing unit 15 writes the data stored in the normal access block 21 to the emergency access block 22 (step S205), and the entire process returns to step S201.

  The memory control circuit 10 according to the present embodiment can avoid the loss of the data while avoiding a decrease in the freshness of the data stored in the rewritable nonvolatile memory. The reason is that the number-of-times measuring unit 11 measures the number of times of writing when data is written to the normal access block 21 in the FROM 20, and the writing unit 15 reaches the number of times threshold. In this case, the data is written in the emergency access block 22 in the FROM 20.

  Hereinafter, effects realized by the memory control circuit 10 according to the present embodiment will be described in detail.

  In a system that stores data in flash memory, in order to prevent data from being lost, by providing a storage block that does not update data after shipment, to avoid deterioration of the nonvolatile performance of the storage block There is a problem that the latestness of the data stored in the storage block is lowered. On the other hand, in such a system, when the data is updated so that the data freshness does not deteriorate, there is a problem that the nonvolatile performance of the storage block is deteriorated. In an actual system, it is required to avoid both the loss of data and the decrease in data freshness, and it is a problem to realize this.

  On the other hand, in the memory control circuit 10 according to the present embodiment, when the data is written in the normal access block 21, the number measurement unit 11 does not apply to the normal access block 21 until then. The number of times of writing is measured. The determination unit 14 determines whether the number of writings measured by the number measurement unit 11 satisfies a predetermined number of times (has reached the number threshold). The writing unit 15 writes the data written in the normal access block 21 to the emergency access block 22 when the determination unit 14 determines that the write count satisfies the number of times. Thereby, the memory control circuit 30 according to the present embodiment can avoid the loss of the data while avoiding a decrease in the freshness of the data stored in the flash memory.

  FIG. 9 is a diagram conceptually illustrating the relationship between the time since the start of use of the FROM 20 according to the present embodiment and the data retention guaranteed time. FIG. 9 shows each sub-block of the normal-time access block 21 when data is rewritten 10N times in a cycle of T time for each sub-block of the normal-time access block 21 in the FROM 20. And, the transition of the data retention guarantee time is shown for the emergency access block 22. In an actual system, the data is not rewritten 10N times for each sub-block of the normal access block 21. However, in order to simplify the description, such an operation is performed. To be done. The FROM 20 has the characteristics shown in FIG. 6, and the temperature of the FROM 20 is 55 ° C.

  The thick line shown in FIG. 9 represents the length of the data retention guarantee time of the normal access block 21 and the emergency access block 22 in the time after the use of the FROM 20 is started. As shown in FIG. 9, 10N times of rewriting is performed on each sub-block of the normal-time access block 21 1T time after the use of the FROM 20 is started. The data retention guarantee time of the normal access block 21 at this time is 1T time as shown in FIG. In the present embodiment, as described above, each time the rewrite is performed 10 times for each sub-block of the normal access block 21, the emergency access block 22 is rewritten once. Therefore, the emergency access block 22 is rewritten 1N times 1T time after the use of the FROM 20 is started. The data retention guarantee time of the emergency access block 22 at this time is 10T as shown in FIG.

  As shown in FIG. 9, 20N times of rewriting is performed on each sub-block of the normal access block 21 after 2T hours from the start of use of the FROM 20. At this time, the data retention guarantee time of the normal access block 21 is reduced to 0.9 T time. Then, 2N times after the start of use of the FROM 20, the emergency access block 22 is rewritten 2N times. At this time, the data retention guarantee time of the emergency access block 22 is reduced to 9T time.

  As described above, the data retention guarantee time of the normal access block 21 and the emergency access block 22 decreases by 10% every time 1T time has elapsed since the start of use of the FROM 20. The number of data rewrites for the emergency access block 22 is one tenth of the number of data rewrites for each sub-block of the normal access block 21. Therefore, the data retention guarantee time of the emergency access block 22 at the same time can be maintained 10 times the data retention guarantee time of the normal access block 21. The data stored in the emergency access block 22 is updated as appropriate. Therefore, according to the memory control circuit 10 according to the present embodiment, even when the data stored in the normal access block 21 is lost, the data is stored in a state in which the latest data is maintained to some extent. It can be recovered.

  In the memory control circuit 10 according to the present embodiment, the time measurement unit 12 measures the elapsed time since the last writing to the emergency access block 22 at a predetermined timing. When the determination unit 14 determines that the elapsed time has reached the time threshold value, the writing unit 15 writes the data stored in the normal access block 21 to the emergency access block 22. As a result, the memory control circuit 10 according to the present embodiment makes the data emergency as a backup of the data when the time when the data stored in the normal access block 21 may be lost has elapsed. Since data is written in the time access block 22, it is possible to more reliably avoid the loss of data.

  As shown in FIGS. 6 and 9, the data retention guarantee time of the FROM 20 decreases as the number of rewrites to the FROM 20 increases. In the memory control circuit 10 according to the present embodiment, the determination unit 14 can decrease the number threshold or the time threshold every time the number of writes measured by the number measuring unit 11 reaches the number threshold. Therefore, the memory control circuit 10 according to the present embodiment writes the data backup to the emergency access block 22 more frequently as the nonvolatile performance of the FROM 20 deteriorates. Can be avoided more reliably.

  Furthermore, in the memory control circuit 10 according to the present embodiment, the temperature measurement unit 13 measures the temperature of the FROM 20. And the determination part 14 can change at least any one of a frequency | count threshold value and a time threshold value according to the temperature measured by the temperature measurement part 13. FIG. As shown in FIG. 6, the non-volatile performance of the FROM 20 decreases as the temperature increases. The determination unit 14 decreases at least one of the number threshold and the time threshold as the temperature of the FROM 20 increases. As a result, the memory control circuit 10 according to the present embodiment writes the data backup to the emergency access block 22 more frequently as the temperature of the FROM 20 becomes higher. Can be avoided more reliably.

<Second Embodiment>
FIG. 4 is a block diagram conceptually showing the configuration of the memory control circuit 30 according to the second embodiment.

  The memory control circuit 30 according to the present embodiment includes a number measurement unit 31, a determination unit 34, and a writing unit 35.

  The rewritable nonvolatile memory 40 to be controlled by the memory control circuit 30 includes a first storage block 41 and a second storage block 42 that individually have nonvolatile performance depending on the number of data writings up to now. Have.

  When the data is written in the first storage block 41, the number measurement unit 31 measures the number of times of writing to the first storage block 41 so far.

  The determination unit 34 determines whether or not the number of writes measured by the number measurement unit 31 satisfies a predetermined number of times.

  The writing unit 35 writes the data written in the first storage block 41 to the second storage block 42 when the determination unit 34 determines that the number of times of writing satisfies the number of times condition. .

  The memory control circuit 30 according to the present embodiment can avoid the loss of the data while avoiding a decrease in the freshness of the data stored in the rewritable nonvolatile memory. The reason is that the number-of-times measuring unit 31 measures the number of times of writing so far when data is written to the first storage block 41, and the writing unit 35 is when the number of times of writing reaches the number of times threshold. This is because the data is written into the second storage block 42.

<Hardware configuration example>
In each embodiment described above, each unit illustrated in FIGS. 1 and 4 can be realized by a dedicated HW (HardWare) (electronic circuit). 1 and 4, at least the following configuration can be regarded as a function (processing) unit (software module) of the software program.
・ Number of times measurement unit 11 and 31,
-Determination units 14 and 34,
Write units 15 and 35.

  However, the division of each part shown in these drawings is a configuration for convenience of explanation, and various configurations can be assumed for mounting. An example of the hardware environment in this case will be described with reference to FIG.

  FIG. 5 is a diagram for exemplifying the configuration of an information processing circuit 900 (computer) that can execute the memory control circuit according to each embodiment of the present invention. That is, FIG. 5 is a configuration of a computer (information processing circuit) capable of realizing the memory control circuit shown in FIGS. 1 and 4 and represents a hardware environment capable of realizing each function in the above-described embodiment.

The information processing circuit 900 shown in FIG. 5 includes the following as components.
CPU (Central_Processing_Unit) 901,
ROM (Read_Only_Memory) 902,
RAM (Random_Access_Memory) 903,
-Bus 904 (communication line).

  That is, the information processing circuit 900 including the above-described components is a general computer in which these configurations are connected via the bus 904.

  The present invention described by taking the above embodiment as an example supplies a computer program capable of realizing the following functions to the information processing circuit 900 shown in FIG. The function is the above-described configuration in the block configuration diagram (FIGS. 1 and 4) referred to in the description of the embodiment, or the function of the flowcharts (FIGS. 2 and 3). The present invention is then achieved by reading the computer program to the CPU 901 of the hardware, interpreting it and executing it. Further, the computer program supplied to the apparatus may be stored in a nonvolatile storage device such as a readable / writable volatile memory (RAM 903).

  The present invention has been described above using the above-described embodiment as an exemplary example. However, the present invention is not limited to the embodiment described above. That is, the present invention can apply various modes that can be understood by those skilled in the art within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Memory control system 10 Memory control circuit 11 Count measurement part 12 Time measurement part 13 Temperature measurement part 14 Judgment part 15 Writing part 20 FROM
21 Block for normal access 21-1 to 21-511 Sub-block 22 Block for emergency access 2 CPU
DESCRIPTION OF SYMBOLS 30 Memory control circuit 31 Count measurement part 34 Judgment part 35 Writing part 40 Nonvolatile memory 41 1st memory block 42 2nd memory block 50 FROM
50-1 to 50-512 Storage block 900 Information processing circuit 901 CPU
902 ROM
903 RAM
904 bus

Claims (9)

When data is written to the first storage block in the rewritable nonvolatile memory having first and second storage blocks each having nonvolatile performance depending on the number of times of data writing up to now Count measuring means for measuring the number of times of writing to the first storage block,
Time measuring means for measuring an elapsed time since the last writing to the second storage block;
It is determined whether or not the number of times of writing measured by the number of times measuring unit satisfies a predetermined number of times, and whether or not the elapsed time measured by the time measuring unit has reached a predetermined time threshold. Determination means for determining ;
When the determination means determines that the number of times of writing satisfies the number of times condition or the elapsed time has reached the time threshold, the data written to the first storage block is Writing means for writing to the storage block;
Comprising
Memory control circuit. The number-of-times measuring means resets the number of times of writing to an initial value when the number of times of writing reaches a predetermined number of times threshold,
The determination means determines whether the number of times of writing has reached the number of times threshold as the number of times condition,
The memory control circuit according to claim 1 . The determination unit reduces the number-of-times threshold as the number of times of writing reaches the number-of-times threshold.
The memory control circuit according to claim 2 . The determination unit decreases the time threshold as the number of times of writing reaches the number of times threshold.
The memory control circuit according to claim 2 or 3. Temperature measuring means for measuring the temperature of the nonvolatile memory,
The determination unit changes at least one of the contents of the number condition and the time threshold according to the temperature of the nonvolatile memory measured by the temperature measurement unit.
The memory control circuit according to any one of claims 1 to 4. In the case where the sub-block to which the data is written moves in a round robin manner in response to the data being written to the first storage block including a plurality of sub-blocks, Measuring the total number of times of writing to the plurality of sub-blocks;
The memory control circuit according to any one of claims 1 to 5. A memory control circuit according to any one of claims 1 to 6 ;
The nonvolatile memory;
A memory control system. Depending on the information processing device,
When data is written to the first storage block in the rewritable nonvolatile memory having first and second storage blocks each having nonvolatile performance depending on the number of times of data writing up to now , Measure the number of writes to the first storage block so far,
Measuring the elapsed time since the last write to the second storage block;
Measured the number of times of writing has, together with determining whether a predetermined number of times satisfying, the elapsed time is measured to determine whether it has reached a predetermined time threshold,
When it is determined that the number of times of writing satisfies the number of times condition or the elapsed time has reached the time threshold, the data written to the first storage block is transferred to the second storage block. Write
Memory control method. When data is written to the first storage block in the rewritable nonvolatile memory having first and second storage blocks each having nonvolatile performance depending on the number of times of data writing up to now , A number measurement process for measuring the number of times of writing to the first storage block,
A time measurement process for measuring an elapsed time since the last writing to the second storage block;
It is determined whether or not the number of times of writing measured by the number of times measurement process satisfies a predetermined number of times, and whether or not the elapsed time measured by the time measurement process has reached a predetermined time threshold value. A determination process for determining ;
When the determination process determines that the number of times of writing satisfies the number of times condition or the elapsed time has reached the time threshold, the data written to the first storage block is changed to the second storage block. Write processing to write to the storage block,
Memory control program for causing a computer to execute.

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