TW201813314A - Clock data recovery module - Google Patents

Abstract

The present disclosure is a clock data recovery circuit that includes a Clock and Data Recovery (CDR) loop and a Spread Spectrum Clock (SSC) tracking circuit. The CDR loop includes a CDR unit and a Phase Interpolator (PI) unit. The PI unit is coupled to the CDR unit. The CDR unit generates a phase signal according to a data signal, and the PI unit generates a data clock signal and an edge clock signal according to the phase signal and a reference clock signal. The SSC tracking circuit generates the reference clock signal according to the data signal, and transmits the reference clock signal to the PI unit. The CDR unit further generates the phase signal according to the data signal, the data clock signal and the edge clock signal. The SSC tracking circuit and the CDR loop are in decoupling arrangement.

Description

 Clock data recovery module  

The present invention relates to a signal processing circuit, and more particularly to a clock data recovery module.

With the rapid development of signal transmission technology, the requirements of the receiver for jitter jitter are becoming stricter. Therefore, in order to achieve more stringent signal jitter tolerance, a Clock and Data Recovery (CDR) circuit is usually set in the receiving end to restore the data signal affected by the signal jitter.

However, in addition to the signal jitter caused by the transmission of the data signal, the operation of the clock data recovery circuit itself will also cause signal jitter of the data signal. In order to reduce the signal jitter generated by the clock data recovery circuit, it is common practice to increase the phase interpolation resolution (PI resolution) of the phase interpolator (PI) in the phase tracking circuit, but the method and frequency are The phase interpolator in the tracking circuit requires less phase interpolation resolution when operating.

Therefore, how to design the clock data recovery module under the premise of balancing the operation of the clock data recovery circuit and the overall signal jitter is a big challenge.

One aspect of the present invention relates to a clock data recovery module including a clock data recovery loop and a spread spectrum clock tracking circuit. The clock data recovery loop includes a clock data recovery unit and a first phase interpolation unit, and the first phase interpolation unit is coupled to the clock data recovery unit. The clock data recovery unit is configured to generate a phase signal according to the data signal, and the first phase interpolation unit is configured to generate the data clock signal and the edge clock signal according to the phase signal and the reference clock signal. The spread spectrum clock tracking circuit is configured to generate a reference clock signal according to the data signal, and transmit the reference clock signal to the first phase interpolation unit. The clock data recovery unit generates a phase signal based on the data signal, the data clock signal, and the edge clock signal. In addition, the spread spectrum clock tracking circuit and the clock data recovery loop are decoupled configurations.

In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. With the above technical solution, considerable technological progress can be achieved, and the industrial use value is widely used. The present invention decouples the clock data recovery loop and the spread spectrum clock tracking circuit in the clock data recovery module. The clock data recovery loop and the spread spectrum clock tracking circuit respectively track the phase and frequency, and integrate the phase and frequency tracking results to restore the data signal. According to the technique of the present invention, the decoupled clock data recovery loop and the spread spectrum clock circuit can respectively implement different phase interpolation resolutions, so that they respectively reach the global optimum of the phase interpolation resolution. In order to improve the accuracy and efficiency of phase and frequency tracking, the data signal restored by the clock data recovery module conforms to the display threshold (such as DisplayPort 1.3) for signal jitter tolerance.

100, 100A, 100B‧‧‧ clock data recovery module

110‧‧‧ Clock data recovery loop

112‧‧‧clock data recovery unit

114‧‧‧First phase interpolation unit

116‧‧‧Sampling unit

118‧‧‧ digit conversion unit

120, 120A‧‧‧ Spread spectrum clock tracking circuit

120B‧‧‧clock data recovery circuit

122‧‧‧Frequency detection unit

124‧‧‧frequency generation unit

126‧‧‧Second phase interpolation unit

Sdata‧‧‧Information Signal

1 is a block diagram of a clock data recovery module according to an embodiment of the present disclosure; and FIG. 2 is a block diagram of a clock data recovery module according to an embodiment of the present disclosure; FIG. 3 is a block diagram of a clock data recovery module according to still another embodiment of the present disclosure.

The following is a detailed description of the embodiments in order to provide a better understanding of the aspects of the present invention, but the embodiments are not intended to limit the scope of the disclosure, and the description of structural operation is not used. Limiting the order in which they are performed, any device that is recombined by components, produces equal-efficiency devices, and is covered by the disclosure. In addition, according to industry standards and practices, the drawings are only for the purpose of assisting the description, and are not drawn according to the original size. In fact, the dimensions of the various features may be arbitrarily increased or decreased for convenience of explanation. In the following description, the same elements will be denoted by the same reference numerals for convenience of understanding.

The terms used in the entire specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, the content disclosed herein, and the particular content. Certain terms used to describe the present disclosure are discussed below or elsewhere in the specification to provide additional guidance to those skilled in the art in the description of the present disclosure.

In addition, the terms "including", "including", "having", "containing", and the like, which are used in the present invention, are all open terms, meaning "including but not limited to". Further, "and/or" as used in the present invention includes any one or a combination of one or more of the related listed items.

In the present invention, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate that two or more components operate or interact with each other. Further, although the terms "first", "second", and the like are used in the present invention to describe different elements, the terms are used to distinguish the elements or operations described in the same technical terms. The use of the term is not intended to be a limitation or a

FIG. 1 is a block diagram of a clock data recovery module according to an embodiment of the present disclosure. As shown in FIG. 1, the clock data recovery module 100 includes a clock data recovery loop 110 and a spread spectrum clock tracking circuit 120. The clock data recovery circuit 110 includes a clock data recovery unit 112, a first phase interpolation unit 114, and the clock data recovery unit 112 is coupled to the first phase interpolation unit 114. In addition, the clock data recovery loop 110 and the spread spectrum clock tracking circuit 120 are decoupled. For example, the spread spectrum clock tracking circuit 120 acts as a circuit that can operate independently, and is not a component or circuit in the clock data recovery loop 110.

The clock data recovery unit 112 is configured to receive the data signal Sdata, generate a phase signal according to the data signal Sdata, and transmit the phase signal to the first phase interpolation unit 114. The spread spectrum clock tracking circuit 120 is configured to receive the data signal Sdata, generate a reference clock signal according to the data signal Sdata, and transmit the reference clock signal to the first phase interpolation unit 114. The first phase interpolation unit is configured to generate the data clock signal and the edge clock signal according to the phase signal from the clock data recovery unit 112 and the reference clock signal of the spread spectrum clock tracking circuit 120.

Then, the clock data recovery unit 112 is further configured to generate a phase signal according to the data signal Sdata, the data clock signal, and the edge clock signal. For example, the data clock signal and the edge clock signal generated by the first phase interpolating unit 114 can be directly or again processed by the signal and then sent back to the clock data replying unit 112, and the clock data replying unit 112 performs the clock data replying unit 112. Regeneration of the phase signal.

In one embodiment, the clock data recovery loop 110 further includes a sampling unit 116, and the sampling unit 116 is coupled to the first phase interpolation unit 114. The sampling unit 116 is configured to receive the data clock signal and the edge clock signal generated by the first phase interpolation unit 114, and sample the data to generate the data sampling signal and the edge sampling signal.

In another embodiment, the clock data recovery loop 110 further includes a bit number conversion unit 118, and the bit number conversion unit 118 is coupled to the sampling unit 116. The bit number converting unit 118 is configured to receive the data sampling signal and the edge sampling signal generated by the sampling unit 116, and perform bit number conversion thereon. Then, the bit number converting unit 118 transmits the converted data sampling signal and the edge sampling signal to the clock data replying unit 112, and the clock data replying unit 112 performs the regenerating of the phase signal. Therefore, the clock data replying unit 112, the first phase interpolating unit 114, the sampling unit 116, and the bit number converting unit 118 form a first loop circuit, so that the clock data replying unit 112 can be based on the received data signal Sdata and The converted data sampling signal and the edge sampling signal are iteratively operated. For example, the bit number conversion unit 118 performs bit number conversion for the data sampling signal and the edge sampling signal according to the signal form supported by the clock data replying unit 112.

In another embodiment, the data sampling signal and the edge sampling signal generated by the sampling unit 116 are presented in the form of a binary signal stream, and the bit number converting unit 118 uses the data sampling signal and the edge sampling signal from the binary signal. The stream is converted to a four-bit signal stream. After the bit number conversion unit 118 converts the data sample signal and the edge sample signal into a four-bit signal stream, the converted data sample signal and the edge sample signal are transmitted to the clock data recovery unit 112, and the clock data is obtained. The reply unit 112 performs re-generation of the phase signal. It should be understood that the above specific implementation of the bit number conversion unit 118 is for illustrative purposes only and is not intended to limit the implementation of the present invention.

In an embodiment, the spread spectrum clock tracking circuit 120 is further configured to adjust the frequency of the reference clock signal, so that the frequency of the reference clock is approximated to the frequency corresponding to the data signal Sdata, thereby reducing jitter of the reference clock signal (jitter) ). In another embodiment, the spread spectrum clock tracking circuit 120 generates a plurality of reference clock signals according to the data signal Sdata, and each of the reference clock signals has the same frequency but different phases.

In one embodiment, the first phase interpolating unit 114 is configured to perform phase interpolation processing on the plurality of reference clock signals generated by the spread spectrum clock tracking circuit 120 according to the phase signal, thereby generating data clock signals and edges. Clock signal. For example, when the first phase interpolating unit 114 performs phase interpolation processing on the plurality of reference clock signals, it may first select two of the reference clock signals from the plurality of reference clock signals, and then select according to the selected Two clock signals, which generate data clock signals and edge clock signals. For example, the phase of the data clock signal and the edge clock signal is between the phases of the two reference clock signals selected by the first phase interpolation unit 114.

In addition, the operation of the first phase interpolating unit 114 is related to the phase interpolation resolution. For example, when the unit interval of the phase interpolation resolution is smaller, the error of the data clock signal and the edge clock signal generated by the first phase interpolation unit 114 compared with the clock signal corresponding to the data signal Sdata should be The operation time required for the data clock signal and the edge clock signal generated by the first phase interpolating unit 114 may be relatively extended. Conversely, the data clock signal generated by the first phase interpolating unit 114 and The error of the edge clock signal may be larger than that of the clock signal corresponding to the data signal Sdata, but the operation time of the data clock signal and the edge clock signal generated by the first phase interpolation unit 114 may be relatively shortened.

On the other hand, by increasing the unit interval of the phase interpolation resolution in the first phase interpolating unit 114, the dither jitter caused by the processing of the data signal Sdata by the clock data recovery unit 112 can be further reduced. Or tracking jitter. In an embodiment, the unit interval of the phase interpolation resolution may be between 1/32 and 1/128. It should be understood that the above specific implementation of the phase interpolation resolution is for illustrative purposes only and is not intended to limit the implementation of the present invention.

In an embodiment, the clock data replying unit 112 is a second order clock data replying unit, and the operating clock frequency is related to the data rate corresponding to the data signal Sdata. For example, the clock data recovery module 100 can be applied to a device supported by a display port (eg, DisplayPort 1.3). Since the data rate corresponding to the data signal Sdata in the DisplayPort 1.3 is 8.1 Gbps, the clock data recovery unit 112 The operating clock frequency can be a frequency corresponding to a value of one quarter of the transmission rate (approximately 2 GHz). It should be understood that the above specific implementation of the operating clock frequency of the clock data replying unit 112 is for exemplary purposes only and is not intended to limit the implementation of the present invention.

In one embodiment, the spread spectrum clock tracking circuit 120 is coupled to the first phase interpolation unit 114 and the bit number conversion unit 118 in the clock data recovery loop 110, respectively. The bit number conversion unit 118 is configured to transmit the converted data sample signal and the edge sample signal to the spread spectrum clock tracking circuit 120, and the spread spectrum clock tracking circuit 120 performs frequency signal regeneration. Therefore, the spread spectrum clock tracking circuit 120 and the first phase interpolation unit 114, the sampling unit 116, and the bit number conversion unit 118 in the clock data recovery loop 110 form a second loop circuit, thereby spreading the clock tracking circuit. 120 can operate according to the received data signal Sdata and the converted data sampling signal and the edge sampling signal.

FIG. 2 is a block diagram of a clock data recovery module according to an embodiment of the present disclosure. In an embodiment, the clock data recovery module 100 shown in FIG. 1 can be implemented by the clock data recovery module 100A of FIG. 2, but the invention is not limited thereto.

In contrast to FIG. 1, FIG. 2 illustrates in detail one of the embodiments of the spread spectrum clock tracking circuit 120 of FIG. 1, such as the spread spectrum clock tracking circuit 120A. The spread spectrum clock tracking circuit 120A includes a frequency detecting unit 122, a frequency generating unit 124, and a second phase interpolating unit 126. The frequency detecting unit 122 is coupled to the frequency generating unit 124, and the frequency generating unit 124 is further coupled to the second phase interpolating unit 126. In addition, the clock data recovery loop 110 and the spread spectrum clock tracking circuit 120A are decoupled. For example, the spread spectrum clock tracking circuit 120A functions as a circuit that can operate independently, not as a component or circuit in the clock data recovery loop 110. The functions and configurations of the clock data replying unit 112, the first phase interpolating unit 114, the sampling unit 116, and the bit number converting unit 118 in the clock data recovery loop 110 have been described in detail in the previous embodiments. This is not repeated.

The frequency detecting unit 122 is configured to detect the frequency of the data signal Sdata to generate a frequency detecting signal, and then transmit the frequency detecting signal to the frequency generating unit 124. The frequency generating unit 124 is configured to generate a frequency signal according to the frequency detecting signal from the frequency detecting unit 122, and then transmit the frequency signal to the second phase interpolating unit 126. The second phase interpolating unit 126 is configured to generate a reference clock signal according to the frequency signal from the frequency generating unit 124, and then transmit the reference clock signal to the first phase interpolating unit 114 in the clock data recovery loop 110.

In an embodiment, the second phase interpolating unit 126 is further configured to adjust the frequency of the reference clock signal, so that the frequency of the reference clock is approximated to the clock frequency corresponding to the data signal Sdata, thereby reducing the jitter of the reference clock signal. . In one embodiment, the second phase interpolating unit 126 generates a plurality of reference clock signals according to the frequency signals generated by the frequency generating unit 124, and each of the reference clock signals has the same frequency but different phases.

Additionally, the operation of the second phase interpolation unit 126 is related to phase interpolation resolution. However, compared to the first phase interpolation unit 114, a larger phase interpolation resolution is required to reduce the high frequency jitter or tracking jitter caused by the clock data recovery unit 112, which is applied to the second phase interpolation unit 126. The phase interpolation resolution is reversed. For example, since the operation of the second phase interpolation unit 126 in the spread spectrum clock tracking circuit 120A generally needs to support a faster phase rotation or a higher phase update rate, The second phase interpolation unit 126 needs to implement a smaller phase interpolation resolution to meet the above requirements. In an embodiment, the unit interval of the phase interpolation resolution applied to the second phase interpolation unit 126 may be between 1/32 and 1/128. It should be understood that the above specific implementation of the phase interpolation resolution is for illustrative purposes only and is not intended to limit the implementation of the present invention.

In one embodiment, the second phase interpolating unit 126 is coupled to the first phase interpolating unit 114 in the clock data recovery loop 110, and the frequency detecting unit 122 is coupled to the bit in the clock data recovery loop 110. The number conversion unit 118. The bit number conversion unit 118 is configured to transmit the converted data sample signal and the edge sample signal to the frequency detection unit 122, and the frequency detection unit 122 performs the regeneration of the frequency detection signal. Therefore, the frequency detecting unit 122, the frequency generating unit 124, and the second phase interpolating unit 126 in the spread spectrum clock tracking circuit 120A and the first phase interpolating unit 114 and the sampling unit 116 in the clock data recovery loop 110 and The bit number converting unit 118 forms a second loop circuit, so that the frequency detecting unit 122 can operate in tandem with the converted data sample signal and the edge sample signal according to the received data signal Sdata.

FIG. 3 is a block diagram of a clock data recovery module according to still another embodiment of the present disclosure. In an embodiment, the clock data recovery module 100 shown in FIG. 1 can be implemented by the clock data recovery module 100B of FIG. 3, but the invention is not limited thereto.

Compared with FIG. 1, FIG. 3 illustrates one of the embodiments of the spread spectrum clock tracking circuit 120 of FIG. 1, such as the clock data recovery circuit 120B. In an embodiment, the clock data recovery circuit 120B is configured to receive the data signal Sdata, generate a frequency signal according to the data signal Sdata, and further generate a reference clock signal according to the frequency signal, and transmit the reference clock signal to the reference clock signal. The clock data is returned to the first phase interpolation unit 114 in the loop 110. It should be understood that the above specific implementation of the clock data recovery circuit 120B is for illustrative purposes only and is not intended to limit the implementation of the present invention. In addition, the functions and configurations of the clock data replying unit 112, the first phase interpolating unit 114, the sampling unit 116, and the bit number converting unit 118 in the clock data recovery loop 110 have been described in detail in the previous embodiments. Therefore, the details are not repeated here.

In an embodiment, the clock data recovery unit 112 and the second clock data recovery unit are both second-order clock data recovery units, and the operating clock frequency is related to the transmission rate corresponding to the data signal Sdata. For example, the clock data recovery module 100A can be applied to a device supported by DisplayPort 1.3. Since the data rate corresponding to the data signal Sdata in DisplayPort 1.3 is 8.1 Gbps, the clock data recovery unit 112 and the second clock data are used. The operating clock frequency of the reply unit can be a frequency corresponding to a value of one quarter of the transmission rate (approximately 2 GHz). It should be understood that the specific implementation of the operating clock frequency of the clock data replying unit 112 and the second clock data replying unit is merely exemplary and is not intended to limit the implementation of the present invention.

In the above embodiment, the present invention decouples the clock data recovery loop and the spread spectrum clock tracking circuit in the clock data recovery module, and causes the clock data recovery loop and the spread spectrum clock tracking circuit to perform respectively. Phase and frequency tracking, and integration of phase and frequency tracking results for data signal restoration. According to the technology of the present invention, the decoupled clock data recovery loop and the spread spectrum clock circuit can respectively implement different phase interpolation resolutions, so that they respectively reach the global optimal solution of the phase interpolation resolution, thereby improving the phase and the phase. The accuracy and efficiency of the frequency tracking, so that the data signal restored by the clock data recovery module meets the requirements of the display 埠 (such as: DisplayPort 1.3) for signal jitter tolerance.

Those skilled in the art will readily appreciate that the disclosed embodiments achieve the advantages of one or more of the foregoing examples. After reading the foregoing description, those skilled in the art will be able to make various modifications, substitutions, equivalents, and various other embodiments. Therefore, the scope of protection of the present invention is defined by the scope of the patent application and its equal scope.

Claims (10)

 A clock data recovery module includes: a clock data recovery loop, comprising: a clock data recovery unit for generating a phase signal according to a data signal; and a first phase interpolation unit coupled to the time The data recovery unit is configured to generate a data clock signal and an edge clock signal according to the phase signal and a reference clock signal, wherein the clock data recovery unit is further configured to use the data signal and the data clock. The phase signal is generated by the signal and the edge clock signal; and a spread spectrum clock tracking circuit is configured to generate the reference clock signal according to the data signal, and transmit the reference clock signal to the first phase The plug-in unit, wherein the spread-spectrum clock tracking circuit and the clock data recovery loop are decoupled.    The clock data recovery module of claim 1, wherein the clock data recovery loop further comprises: a sampling unit coupled to the first phase interpolation unit for the data clock signal and the edge The clock signal is sampled to generate a data sample signal and an edge sample signal.    The clock data recovery module of claim 2, wherein the clock data recovery loop further comprises: a one-digit conversion unit coupled to the sampling unit for sampling the signal and the edge sampling signal Performing bit number conversion, and transmitting the converted sample signal and the edge sample to the clock data recovery unit.    The clock data recovery module of claim 3, wherein the data sampling signal and the edge sampling signal are both binary signal streams, and the bit number conversion unit is configured to convert the binary signal stream into four Bit signal stream.    The clock data recovery module of claim 4, wherein the spread spectrum clock tracking circuit comprises: a frequency detecting unit for detecting a frequency of the data signal to generate a frequency detecting signal; and a frequency The generating unit is coupled to the frequency detecting unit for generating a frequency signal according to the frequency detecting signal.    The clock data recovery module of claim 5, wherein the spread spectrum clock tracking circuit further comprises: a second phase interpolation unit coupled to the frequency generating unit for generating the frequency signal according to the frequency signal Referring to the clock signal, and transmitting the reference clock signal to the first phase interpolation unit.    The clock data recovery module of claim 6, wherein the frequency detecting unit is coupled to the bit number converting unit, and the bit number converting unit performs bit number on the data sampling signal and the edge sampling signal. Converting, and transmitting the converted data sampling signal and the edge sampling signal to the frequency detecting unit.    The clock data replying module of claim 7, wherein the data sampling signal and the edge sampling signal are both binary signal streams, and the bit number converting unit is configured to convert the binary signal stream into four Bit signal stream.    The clock data recovery module of claim 1, wherein the spread spectrum clock tracking circuit comprises a clock data recovery circuit for generating the reference clock signal according to the data signal.    The clock data recovery module of claim 9, wherein the clock data recovery circuit comprises: a second clock data recovery unit for generating a frequency signal according to the data signal; and a second phase The plug-in unit is coupled to the second clock data recovery unit for generating the reference clock signal according to the frequency signal, and transmitting the reference clock signal to the first phase interpolation unit.