JP2014146964A - Signal transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal transmission system which allows for reduction of even-ordered harmonics.SOLUTION: A transmitter 1 includes a signal generator 2 and a differential amplifier 5. The signal generator 2 includes an original signal generation unit 3 for generating the original signal S1 of data, and a delay signal generation unit 4 for generating a delay signal S2 by delaying the original signal S1 by 1 bit. The output ports 2A, 2B of the signal generator 2 output the original signal S1 and the delay signal S2. The output ports 2A, 2B of the signal generator 2 are connected, respectively, with two input terminals of the differential amplifier 5. The differential amplifier 5 calculates the difference between the original signal S1 and delay signal S2, and outputs a self-delay difference signal S3. The self-delay difference signal S3 is transmitted to a receiver 7 via a transmission line 6.

Description

  The present invention relates to a signal transmission method for transmitting a plurality of bits of data.

  As a signal transmission method, a balanced transmission method is known in which signals having phases inverted to each other are transmitted to two transmission lines (see, for example, Patent Document 1). In this balanced transmission system, when the transmission line is viewed from a distance, it looks as if the signal is 0 (zero). For this reason, noise radiation from the transmission line can be reduced.

JP-A-51-97314

  Incidentally, noise radiation actually exists even in the balanced transmission system. The causes are (a) the rise and fall timings of the two signals are shifted, (b) the rise and fall rates of the signals are different, and (c) the impedance and electrical length of the two transmission lines are shifted. For example, the phases and amplitudes of the two signals are shifted. The most probable cause is the deviation (skew) between the rising and falling timings of the signal. If even this skew exists, there is a problem that noise radiation is hardly reduced for even-order harmonics.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a signal transmission system that can reduce even-order harmonics.

  In order to solve the above-mentioned problem, the invention of claim 1 is a signal transmission system for transmitting a plurality of bits of data, wherein a difference between the original signal of the data and a delayed signal obtained by delaying the original signal by 1 bit is obtained. The taken self-delay differential signal is transmitted.

  In the invention of claim 2, the self-delay differential signal includes three values of a high value, a low value, and an intermediate value therebetween, and when the self-delay differential signal is an intermediate value, Demodulate the data.

  In the invention of claim 3, the self-delay differential signal is transmitted to one of the two transmission lines, and the opposite-phase signal that is in reverse phase to the self-delay differential signal is transmitted to the other.

  According to the first aspect of the present invention, the self-delayed difference signal obtained by taking the difference between the original signal and the delayed signal is transmitted. Here, since the delayed signal is only delayed by one bit with respect to the original signal, the spectrums of the original signal and the delayed signal are basically the same. In addition, with respect to the fundamental wave component corresponding to a half frequency of the data transmission rate, the original signal and the delayed signal are 180 ° out of phase with each other. At this time, since the self-delayed difference signal takes the difference between the original signal and the delayed signal, the fundamental wave components of the self-delayed difference signal are output in an intensified manner. On the other hand, with respect to the second harmonic component (second harmonic component) that is the frequency of the data transmission rate, the original signal and the delayed signal are mutually shifted in phase by 360 °. For this reason, the second harmonic component of the self-delayed difference signal is output after being weakened. Therefore, in the self-delayed differential signal, even-order harmonics are weakened, so that noise radiation due to even-order harmonics can be reduced.

  According to the second aspect of the present invention, since the original signal is a binary digital signal, the self-delayed difference signal obtained by taking the difference between the original signal and the delayed signal includes a high value, a low value, and an intermediate value. At this time, when the self-delay differential signal becomes a high value or a low value, the high value and the low value of the original signal are switched for each bit, for example, the value of the original signal is reflected. For this reason, data can be demodulated by making the value of the demodulated signal of data correspond to the high value and low value of the self-delayed difference signal. On the other hand, when the self-delay differential signal has an intermediate value, the high value or low value of the original signal is continuous for 2 bits or more, and the value one bit before the original signal is reflected. For this reason, the data can be demodulated by setting the value of the demodulated signal of the data to the same value as one bit before.

  According to the invention of claim 3, since the self-delay differential signal is transmitted to one of the two transmission lines, and the opposite phase signal that is in reverse phase to the self-delay differential signal is transmitted to the other, the self-delay Balanced transmission using the differential signal can be performed. For this reason, noise radiation from the transmission line can be further reduced.

It is a block diagram which shows the transmitter and receiver of the signal transmission system by the 1st Embodiment of this invention. It is explanatory drawing which shows the conversion logic in FIG. It is a characteristic diagram which shows the time change of an original signal, a delay signal, and a self-delay difference signal. It is a characteristic diagram which shows the spectrum of an original signal, a delay signal, and a self-delay difference signal. It is a characteristic diagram which shows the time change of the original signal by a modification, a delay signal, and a self-delay difference signal. It is a block diagram which shows the transmitter of the signal transmission system by the 2nd Embodiment of this invention. It is a block diagram which shows the transmitter of the signal transmission system by the 3rd Embodiment of this invention. It is explanatory drawing which shows the logic logic by the difference calculating part in FIG. It is a block diagram which shows the transmitter of the signal transmission system by the 4th Embodiment of this invention.

  Hereinafter, a signal transmission system according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a transmitter 1 and a receiver 7 used in the signal transmission system according to the first embodiment. In the following, the current bit is referred to as the current bit, and the bit one bit before is referred to as the previous bit.

  The transmitter 1 includes a signal generator 2 and a differential amplifier 5. The signal generator 2 is constituted by, for example, a microcomputer, and an original signal generator 3 that generates an original signal S1 of data, and a delayed signal generator 4 that generates a delayed signal S2 obtained by delaying the original signal S1 by 1 bit. With. At this time, the original signal S1 is composed of a digital signal and constitutes data consisting of a plurality of bits. The original signal S1 and the delayed signal S2 are voltage signals whose voltages are determined according to, for example, bit values “1” and “0”, and are output from the output ports 2A and 2B of the signal generator 2, respectively.

  The differential amplifier 5 calculates the difference between the original signal S1 and the delayed signal S2, and outputs a self-delayed differential signal S3. Specifically, the differential amplifier 5 subtracts the delay signal S2 from the original signal S1 to calculate a self-delay difference signal S3.

  The differential amplifier 5 is constituted by an operational amplifier having an amplification factor of 1, for example. For example, the differential amplifier 5 has a bandwidth (FT) of about 10 times the data rate of the original signal S1 and an input third-order intercept point (IIP3) sufficiently higher than the signal voltage. preferable. Further, the self-delayed difference signal S3 only needs to correspond to the difference between the original signal S1 and the delayed signal S2, and may be, for example, a signal obtained by subtracting the original signal S1 from the delayed signal S2.

  Here, the original signal S1 and the delayed signal S2 are both binary digital signals. That is, the original signal S1 and the delayed signal S2 have, for example, a high value H (High) corresponding to “1” and a low value L (Low) corresponding to “0”. On the other hand, since the self-delayed differential signal S3 corresponds to the difference between the original signal S1 and the delayed signal S2, in addition to the high value H and the low value L, three values of an intermediate value M (Middle) between them are obtained. Including. In order to clarify the three values of the self-delayed differential signal S3, for example, the high value H of the original signal S1 and the high value H of the delayed signal S2 are substantially the same voltage, and the low value L of the original signal S1 and the delayed signal S2 Preferably, the low value L is substantially the same voltage.

  The differential amplifier 5 has an input terminal connected to the output ports 2A and 2B of the signal generator 2, and an output terminal connected to one transmission line 6. For this reason, the self-delayed differential signal S 3 output from the differential amplifier 5 is transmitted toward the receiver 7 through the transmission line 6.

  Note that a header HD for identifying the head portion and packet length data PLD corresponding to the number of bits of data, for example, are added before the self-delay differential signal S3. Thereby, for example, it is possible to classify whether the value of the intermediate value M is data to be demodulated in the packet or data to be discarded.

  The receiver 7 includes an AD converter 8 and a demodulator 9. The AD converter 8 converts the self-delayed differential signal S3 composed of an analog signal input from the transmission line 6 into a digital signal.

  The demodulator 9 is connected to the AD converter 8 through the input port 9A and includes the conversion logic 10 shown in FIG. The conversion logic 10 detects the demodulated signal S4 corresponding to the original signal S1 from the self-delayed differential signal S3, and demodulates the data.

  Specifically, the conversion logic 10 determines the current bit of the demodulated signal S4 to the high value H when the current bit of the self-delayed difference signal S3 is the high value H. Also, the conversion logic 10 determines the current bit of the demodulated signal S4 to be a low value L when the current bit of the self-delayed difference signal S3 is a low value L. On the other hand, when the self-delay difference signal S3 is the intermediate value M, the conversion logic 10 determines that the current bit of the demodulated signal S4 is the same value as the previous bit that is one bit before. That is, when the self-delayed difference signal S3 is the intermediate value M, the conversion logic 10 determines the current bit of the demodulated signal S4 as the high value H when the previous bit of the demodulated signal S4 is determined as the high value H, and demodulates the demodulated signal S4. When the previous bit of the signal S4 is determined to be a low value L, the current bit of the demodulated signal S4 is determined to be a low value L.

  The signal transmission system according to the present embodiment is realized by the above-described configuration, and the operation thereof will be described with reference to FIGS.

  The transmitter 1 generates an original signal S1 and a delayed signal S2 of data by the signal generator 2 when transmitting various data such as images and sounds. Here, the delay signal S2 is obtained by delaying the original signal S1 by 1 bit. As shown in FIG. 3, for example, the original signal S1 is [1,0,1,0,1,0,1,1,0,0,1,0,1,0,1,1 from the beginning to the end. , 1,0,0,1], the delayed signal S2 is equivalent to the original signal S1 with a low value L or no signal added for one bit. Note that FIG. 3 shows a case where the original signal S1 and the delayed signal S2 become the ground potential at the low value L and become the predetermined voltage V0 determined in advance at the high value H.

  The original signal S1 and the delayed signal S2 are output from the output ports 2A and 2B of the signal generator 2, respectively, and the difference between them is calculated by the differential amplifier 5. That is, the differential amplifier 5 compares the original signal S1 and the delayed signal S2 for each bit, and outputs a self-delayed differential signal S3 corresponding to the difference between them. Therefore, when the current bit of the original signal S1 becomes “1” and the current bit of the delayed signal S2 corresponding to the previous bit of the original signal S1 becomes “0”, the current bit of the self-delayed difference signal S3 is positive. A high value H corresponding to the predetermined voltage (+ V0) is output. When the current bit of the original signal S1 becomes “0” and the current bit of the delay signal S2 becomes “1”, the current bit of the self-delay difference signal S3 is a low value corresponding to a negative predetermined voltage (−V0). L is output. Further, when the current bit of the original signal S1 and the current bit of the delayed signal S2 have the same value, the intermediate value M corresponding to the ground potential is output as the current bit of the self-delayed difference signal S3.

  As a result, the self-delayed difference signal S3 output from the differential amplifier 5 becomes a ternary signal while the original signal S1 and the delayed signal S2 are binary signals. As shown in FIG. 3, for example, the original signal S1 is [1,0,1,0,1,0,1,1,0,0,1,0,1,0,1,1,1,0,0 , 1], the self-delayed differential signal S3 is [1, -1,1, -1,1, -1,1,0, -1,0,1, -1,1,0,0,- 1,0,1, -1]. At this time, “1” of the self-delayed difference signal S3 corresponds to the high value H, “−1” corresponds to the low value L, and “0” corresponds to the intermediate value M. The self-delayed differential signal S3 is transmitted to the receiver 7 through one transmission line 6.

  When the receiver 7 receives the self-delay differential signal S3, the AD converter 8 converts the self-delay differential signal S3 into a digital signal and inputs the digital signal to the demodulator 9. As shown in FIG. 3, the demodulator 9 uses the conversion logic 10 to detect the demodulated signal S4 from the self-delayed difference signal S3. For example, the self-delayed differential signal S3 is [1, -1,1, -1,1, -1,1,0, -1,0,1, -1,1,0,0, -1,0,1, -1], the demodulated signal S4 is [1,0,1,0,1,0,1,1,0,0,1,0,1,1,1,0,0,1,0]. become.

  As shown in FIG. 3, the self-delayed differential signal S3 obtained by taking the difference between the original signal S1 and the delayed signal S2 includes three values: a high value H, a low value L, and an intermediate value M. At this time, when the self-delay differential signal S3 becomes a high value H or a low value L, the high value H and the low value L of the original signal S1 are switched every bit, and the value of the current bit of the original signal S1 is reflected. Has been. Therefore, the data can be demodulated by making the value of the current bit of the demodulated signal S4 correspond to the value of the current bit of the self-delayed differential signal S3. On the other hand, when the self-delay differential signal S3 becomes the intermediate value M, the high value H or low value L of the original signal S1 is continuous for 2 bits or more, and the value one bit before the original signal S1, that is, the original signal S1 The value of the previous bit is reflected. Therefore, the data can be demodulated by setting the value of the current bit of the demodulated signal S4 to the same value as the previous bit.

  Note that the number of bits of the demodulated signal S4 is one bit greater than that of the original signal S1, depending on the number of bits of the self-delayed differential signal S3. On the other hand, the header HD and the packet length data PLD are added in advance before the self-delay differential signal S3. For this reason, the demodulator 9 can identify the head portion of the self-delayed differential signal S3 using the header HD and can grasp the number of bits of the original signal S1 based on the packet length data PLD. For this reason, the transmitted data can be demodulated by deleting the last bit of the demodulated signal S4. As a result, the receiver 7 restores the data transmitted from the transmitter 1.

  Next, the effect of reducing even-order harmonics according to the present embodiment will be specifically described below.

  For example, in the case of an ideal signal in which the rise time and fall time of the signal are the same and a random data string continues indefinitely, the even-order harmonic does not originally exist in the spectrum of the signal. However, in actual data transmission, the signal rise time and the fall time are different, and the data string has a packet structure that exists only in a finite time interval. In such a case, even harmonics are generated.

  On the other hand, in the signal transmission system according to the present embodiment, the self-delayed differential signal S3 obtained by taking the difference between the original signal S1 and the delayed signal S2 is transmitted. Here, the delay signal S2 is merely delayed by one bit with respect to the original signal S1. Therefore, as shown in FIG. 4, the spectrums of the original signal S1 and the delayed signal S2 are basically the same. FIG. 4 shows, as an example, a case where the basic frequency f1 is 50 MHz and the data rate is 100 Mbps.

  Further, with respect to the fundamental wave component corresponding to the frequency f1 that is ½ of the data transmission rate, the original signal S1 and the delayed signal S2 are 180 ° out of phase with each other. Since the self-delayed difference signal S3 takes the difference between the original signal S1 and the delayed signal S2, the fundamental wave components of the self-delayed difference signal S3 are output in an intensified manner.

  On the other hand, regarding the second harmonic component (second harmonic component) that is the frequency f2 of the data transmission rate, the original signal S1 and the delayed signal S2 are out of phase with each other by 360 °. For this reason, the second harmonic component of the self-delayed differential signal S3 is output after being weakened. Therefore, in the self-delayed differential signal S3, even-order harmonics corresponding to even multiples of the frequency f1, such as the frequencies f2, f4, are weakened.

  Thus, in the signal transmission system according to the present embodiment, since the self-delayed differential signal S3 obtained by taking the difference between the original signal S1 and the delayed signal S2 is transmitted, even-order harmonics can be reduced, and even-order harmonics are used. Noise radiation can be reduced. As a result, signal transmission with less noise radiation due to even-order harmonics can be achieved compared to the balanced transmission method even when there is a skew due to the difference between the rising and falling timings of the signal.

  In the balanced transmission method, signals having opposite phases are transmitted using two transmission lines, whereas in the signal transmission method according to the present embodiment, a self-delayed differential signal is transmitted using one transmission line 6. S3 is transmitted. Therefore, the present invention can be applied to the case where there is only one transmission line 6.

  Furthermore, in the case of the balanced transmission method, it is difficult to completely align the physical line length, impedance, phase, voltage rise time and fall time of the two transmission lines between the two transmission lines. These values are likely to vary. In particular, in the second harmonic component (second harmonic component) that is the frequency of the data transmission speed, noise radiation tends to increase, and it is often necessary to take measures against noise.

  On the other hand, in the present embodiment, the self-delayed differential signal S3 including the original signal S1 and the delayed signal S2 is transmitted through the same transmission line 6, and therefore, between the two transmission lines as in the balanced transmission system. The problem of variation does not occur, and the characteristics as the theory is easily obtained.

  The balanced transmission method aims to create a signal that is in reverse phase at all frequencies by inverting the voltage between a positive (+) and negative (-) pair. The even harmonics generated by the difference between time and fall time are not out of phase. For this reason, even-order harmonics tend to radiate very easily.

  In the present embodiment, even-order harmonics are reduced by taking the difference between the original signal S1 and the delayed signal S2. For this reason, even when the rise time and the fall time are different, even-order harmonics can be removed.

  Further, for example, in the case of binary detection in which it is determined whether the detection signal is a high value H or a low value L, when the detection signal becomes an intermediate value between the high value H and the low value L, the value of the bit is determined. I can't do it and it's undefined. On the other hand, in the present embodiment, the self-delayed differential signal S3 has an intermediate value M located between these high value H and low value L, so that the self-delayed differential signal S3 becomes indefinite during demodulation. And the bit error rate can be reduced.

  Furthermore, in a general ternary logic, for example, it is necessary to distribute the determination result into three values depending on whether the value is close to a high value H, a low value L, or an intermediate value M. On the other hand, in the present embodiment, when the current bit of the self-delayed difference signal S3 becomes the intermediate value M, the current bit of the demodulated signal S4 is determined to be the same value as the previous bit of the demodulated signal S4. That is, when the current bit of the self-delayed differential signal S3 becomes the intermediate value M, whether the current bit of the demodulated signal S4 is a high value H or a low value L depends on whether the previous bit of the demodulated signal S4 is a high value H or a low value L. Judgment changes. Since the binary demodulated signal S4 is demodulated from the ternary self-delay differential signal S3 with hysteresis as described above, the self-delay differential signal S3 is higher than the intermediate value M when the preceding bit of the demodulated signal S4 has a high value H, for example. When the value is close to the high value H, the current bit of the demodulated signal S4 may be determined to be the high value H, redundancy occurs with respect to the data voltage, and the possibility of erroneous determination is reduced.

  A header HD and packet length data PLD are added before the self-delay differential signal S3. For this reason, the receiver 7 can distinguish between the self-delayed differential signal S3 and the no signal even when the self-delayed differential signal S3 includes the same value as the no signal as the intermediate value M or the low value L, for example. Thus, the head portion of the self-delayed differential signal S3 can be detected. In addition, the receiver 7 can grasp the number of bits of the original signal S1 from the packet length data PLD. For this reason, even if the self-delayed differential signal S3 is 1 bit more than the original signal S1, the data is reliably obtained by extracting a signal corresponding to the number of bits of the original signal S1 from the demodulated signal S4 based on the self-delayed differential signal S3. Can be demodulated.

  In the first embodiment, the self-delayed difference signal S3 has a ternary logical value of a high value H, a low value L, and an intermediate value M. However, the present invention is not limited to this, and may have five logic values, such as a self-delayed difference signal S3 according to the modification shown in FIG.

  In FIG. 5, “1” of the original signal S1 is set to a high value H to correspond to a positive predetermined voltage (+ V0), “0” of the original signal S1 is set to a low value L to correspond to a negative predetermined voltage (−V0), The case where the no-signal state is made to correspond to the ground potential is illustrated. In this case, the leading bit of the self-delayed differential signal S3 has the same voltage as the leading bit of the original signal S1, and the last bit of the self-delayed differential signal S3 has a voltage that is opposite in sign to the last bit of the original signal S1. In FIG. 5, since both the first bit and the last bit of the original signal S1 are “1”, the first bit of the self-delay difference signal S3 becomes a positive predetermined voltage (+ V0) corresponding to “1”. The last bit of the self-delay differential signal S3 becomes a negative predetermined voltage (+ V0) corresponding to “−1”. On the other hand, the remaining bits of the self-delayed difference signal S3 become a value twice the positive or negative predetermined voltage V0 (± 2V0) corresponding to “± 2” or a ground potential corresponding to “0”. .

  Thus, when the quinary self-delay differential signal S3 is used, only the first bit and the last bit of the self-delay differential signal S3 can be set to values different from the remaining bits. For this reason, it is possible to detect the beginning and the end (end) of the self-delayed differential signal S3 using this point.

  Next, a second embodiment of the present invention is shown in FIG. The feature of the second embodiment is that the original signal is delayed using a delay device. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The transmitter 11 according to the second embodiment includes a signal generator 12, a delay device 13, and a differential amplifier 5. The signal generator 12 is configured by, for example, a microcomputer and includes the original signal generation unit 3 and outputs the original signal S1 from the output port 12A. The non-inverting input terminal of the differential amplifier 5 is connected to the output port 12A. For this reason, the original signal S1 is inputted to the non-inverting input terminal of the differential amplifier 5 as it is. Further, the inverting input terminal of the differential amplifier 5 is connected to the output port 12 </ b> A via the delay device 13. At this time, the delay unit 13 delays the original signal S1 by 1 bit to generate a delayed signal S2. Therefore, the delay signal S2 is input to the inverting input terminal of the differential amplifier 5. As a result, the differential amplifier 5 calculates the difference between the original signal S1 and the delay signal S2, and outputs a self-delay difference signal S3.

  Thus, the second embodiment can provide the same effects as those of the first embodiment. In the second embodiment, there is no difference in rising and falling between the original signal S1 and the delayed signal S2 due to individual differences of the signal generator 12, and the accuracy of the self-delayed differential signal S3 is improved. To do. Note that the delay device 13 may cause a loss in the delay signal S2, and it is necessary to pay attention to the characteristic deterioration due to the loss.

  Next, a third embodiment of the present invention is shown in FIG. The feature of the third embodiment is that the signal generator calculates the difference between the original signal and the delayed signal. In the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The transmitter 21 according to the third embodiment includes a signal generator 22. The signal generator 22 includes, for example, a microcomputer, and includes a difference calculation unit 23 that calculates the difference between the original signal S1 and the delay signal S2 in addition to the original signal generation unit 3 and the delay signal generation unit 4. Yes. The difference calculation unit 23 calculates a difference between the original signal S1 made of a digital signal and the delay signal S2 based on, for example, the calculation logic 24 shown in FIG. 8, and outputs a self-delayed difference signal S3.

  Specifically, the difference calculation unit 23 uses the original signal S1 and the delayed signal S2 to calculate, for example, the difference between the value of the current bit of the original signal S1 and the value of the previous bit of the original signal S1. For example, when the current bit of the original signal S1 is “1” (high value H) and the previous bit is “0” (low value L), a high value H is output as the current bit of the self-delay differential signal S3. When the current bit of the original signal S1 becomes “0” (low value L) and the previous bit becomes “1” (high value H), the low value L is output as the current bit of the self-delay difference signal S3. Further, when the current bit and the previous bit of the original signal S1 have the same value, the intermediate value M is output as the current bit of the self-delayed difference signal S3.

  The difference calculation unit 23 is connected to the transmission line 6 through the output port 22 </ b> A of the signal generator 22. Thereby, the self-delayed difference signal S3 output from the difference calculation unit 23 is transmitted to the outside through the transmission line 6.

  Thus, the third embodiment can provide the same operational effects as those of the first embodiment.

  In the third embodiment, the signal generator 22 outputs a ternary self-delay difference signal S3. However, the present invention is not limited to this, and the signal generator 22 may be configured to output a five-valued self-delayed difference signal S3 as in the modification shown in FIG. Since the signal generator 22 generates the self-delayed difference signal S3 by calculating a digital signal, it can easily select either a ternary or quinary logical value according to the desired performance.

  In the third embodiment, the self-delay differential signal S3 is generated by the digital signal arithmetic processing. However, the present invention is not limited to this, and the self-delayed difference signal S3 may be generated by an analog signal calculation process by configuring the signal generator 22 with, for example, a dedicated IC capable of calculating an analog signal.

  Next, FIG. 9 shows a fourth embodiment of the present invention. The feature of the fourth embodiment is that one of the two transmission lines transmits a self-delay differential signal, and the other transmits a reverse-phase signal that is out of phase with the self-delay differential signal. . In the fourth embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The transmitter 31 according to the fourth embodiment includes a differential amplifier 32 that outputs a negative-phase signal (-S3) in addition to the signal generator 2 and the differential amplifier 5. At this time, in the differential amplifier 5, the original signal S1 is input to the non-inverting input terminal, and the delay signal S2 is input to the inverting input terminal. Thereby, the differential amplifier 5 outputs a self-delayed differential signal S3 (+ S3).

  On the other hand, in the differential amplifier 32, the original signal S1 is input to the inverting input terminal, and the delay signal S2 is input to the non-inverting input terminal. As a result, the differential amplifier 32 outputs a negative-phase signal (-S3) that is 180 degrees out of phase with the self-delayed differential signal S3 output from the differential amplifier 5.

  The output terminal of the differential amplifier 5 is connected to the transmission line 6, and the output terminal of the differential amplifier 32 is connected to a separate transmission line 33 paired with the transmission line 6. Thereby, on the receiving side, the self-delayed differential signal S3 can be received by the potential difference between the transmission lines 6 and 33.

  Thus, the fourth embodiment can provide the same operational effects as the first embodiment. In the fourth embodiment, since the self-delayed differential signal S3 is transmitted by balanced transmission using the two transmission lines 6 and 33, in addition to the noise suppression effect of even-order harmonics, all frequencies in balanced transmission are transmitted. Noise suppression effect can be obtained. For this reason, noise radiation from the transmission lines 6 and 33 can be further reduced.

  Although the fourth embodiment is applied to the first embodiment, it can also be applied to the second and third embodiments. When the fourth embodiment is applied to the third embodiment, a reverse phase signal may be calculated in the signal generator, and the self-delayed difference signal output from the signal generator is inverted. A negative phase signal may be generated. Also in the second and fourth embodiments, a quinary self-delay differential signal S3 can be used.

  In each of the above embodiments, the self-delayed difference signal S3 is a positive voltage at the high value H, a negative voltage at the low value L, and a ground potential at the intermediate value M. However, the present invention is not limited to this. For example, the self-delayed difference signal S3 becomes a positive voltage at a high value H, becomes a ground potential at a low value L, and becomes an intermediate positive voltage at an intermediate value M. May be.

1,11,21,31 Transmitter 2,12,22 Signal generator 3 Original signal generator 4 Delayed signal generator 5, 32 Differential amplifier 6, 33 Transmission line 7 Receiver 8 AD converter 9 Demodulator 10 Conversion logic 13 Delay Unit 23 Difference Calculation Unit

Claims (3)

A signal transmission method for transmitting multiple bits of data,
A signal transmission system for transmitting a self-delayed differential signal obtained by taking a difference between an original signal of the data and a delayed signal obtained by delaying the original signal by 1 bit. The self-delayed differential signal includes three values: a high value, a low value, and an intermediate value therebetween,
2. The signal transmission system according to claim 1, wherein when the self-delay differential signal is an intermediate value, the data is demodulated as the same value as the previous bit.   The signal according to claim 1 or 2, wherein one of two transmission lines transmits the self-delay differential signal, and the other transmits a reverse-phase signal that is in reverse phase to the self-delay differential signal. Transmission method.

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