TW201810572A - Fan-out semiconductor package - Google Patents

Abstract

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad, the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad through a via, and the via covers at least a portion of the passivation layer.

Description

Fan-out semiconductor package

[Cross Reference to Related Applications] This application claims the priority of Korean Patent Application No. 10-2016-0077593 filed on June 21, 2016 with the Korean Intellectual Property Office, and on September 2, 2016 Priority of Korean Patent Application No. 10-2016-0112983 filed in the Korean Intellectual Property Office, the entire disclosure of each Korean patent application mentioned herein is incorporated in this case for reference.

The present invention relates to a semiconductor package, and more particularly, to a fan-out type semiconductor package in which connection terminals can extend outside a region in which a semiconductor wafer is placed.

Recently, a significant recent trend in the development of semiconductor wafer-related technologies has been reducing the size of semiconductor wafers. Therefore, in the field of packaging technology, as the demand for small-sized semiconductor wafers and the like has rapidly increased, the demand for a semiconductor package having a compact size that includes a plurality of pins at the same time has increased.

One proposed packaging technology to meet the above technical requirements is fan-out packaging. This fan-out type package has a compact size by rewiring the connection terminals outside the area in which the semiconductor wafer is placed, and can achieve implementation of multiple pins.

Aspects of the present invention can provide a fan-out type semiconductor package in which corrosion of a connection pad, which may occur due to various reasons, can be prevented.

One of the several solutions proposed in the present invention is to prevent the possible exposure to temperature humidity bias (THB) conditions for various reasons by covering the entire exposed surface of the connection pad with a via window. And the corrosion of the connection pad occurred.

According to an aspect of the present invention, a fan-out type semiconductor package may include: a first interconnection member having a through hole; and a semiconductor wafer disposed in the through hole of the first interconnection member and having an active surface and an A passive surface opposite to the active surface, a connection pad is disposed on the active surface; an encapsulation body encapsulating at least some parts of the first interconnection member and at least some of the passive surface of the semiconductor wafer Portions; and a second interconnecting member disposed on the first interconnecting member and on the active surface of the semiconductor wafer. The first interconnection member and the second interconnection member respectively include a redistribution layer, the redistribution layer is electrically connected to the connection pad, the semiconductor wafer includes a protection layer, and the protection layer has an exposed layer. An opening of at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad via a via, and the via is located above at least a portion of the protective layer .

Hereinafter, exemplary embodiments in the present invention will be explained with reference to the drawings. In the drawings, the shape, size, etc. of each component may be exaggerated or shortened for clarity.

The term "exemplary embodiment" used herein does not refer to the same exemplary embodiment, but is provided to emphasize a particular feature or characteristic that is different from a particular feature or characteristic of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be able to be implemented by being combined with each other in whole or in part. For example, even if an element set forth in a particular exemplary embodiment is not set forth in another exemplary embodiment, the element can be understood as a contrary unless a contrary or contradictory description is provided herein. A description related to another exemplary embodiment.

The meaning of "connection" between a component and another component in the description includes an indirect connection via a third component and a direct connection between two components. In addition, “electrically connected” means a concept including physical connection and physical disconnection. It should be understood that when referring to a component by "first" and "second", the component is not limited thereby. The use of "first" and "second" may only be used for the purpose of distinguishing the elements from other elements, and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the patentable scope set forth herein. Similarly, the second element may also be referred to as the first element.

Herein, the upper part, the lower part, the upper side, the lower side, the upper surface, the lower surface, and the like are determined in the drawings. For example, the first interconnection member is disposed at a level higher than the redistribution layer. However, the scope of this application patent is not limited to this. In addition, the vertical direction refers to the above upward and downward directions, and the horizontal direction refers to the directions perpendicular to the above upward and downward directions. In this case, the vertical cross-section refers to a case of being taken along a plane in the vertical direction, and an example of the vertical cross-section may be a cross-sectional view shown in a drawing. In addition, the horizontal cross section refers to a case of being taken along a plane in the horizontal direction, and an example of the horizontal cross section may be a plan view shown in a drawing.

The terminology used herein is for the purpose of illustrating exemplary embodiments only and not limiting the present invention. In this case, the singular includes the plural unless otherwise explained in context. Electronic device

FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

Referring to FIG. 1, the electronic device 1000 can house a motherboard 1010. The motherboard 1010 may include a chip-related component 1020, a network-related component 1030, other components 1040, etc. that are physically connected or electrically connected to the motherboard 1010. These components can be connected to other components described below to form various signal lines 1090.

The chip-related component 1020 may include a memory chip, such as a volatile memory (for example, dynamic random access memory (DRAM)), a non-volatile memory (for example, read only memory memory (ROM)), flash memory, etc .; application processor chips, such as a central processing unit (eg, a central processing unit (CPU)), a graphics processor (eg, a graphic processing unit, GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc .; and logic chips such as analog-to-digital converters, application-specific integrated circuits (ASICs) ), Etc .; or similar chips. However, the wafer-related component 1020 is not limited thereto, and may include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network related component 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), worldwide interoperable microwave access (worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packet access + (high speed packet access + (HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), enhanced data GSM environment (enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (code division multiple access (CDMA), Time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G, and any other wireless designation specified after the above Agreements and cable agreements. However, the network related component 1030 is not limited to this, but may include a variety of other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC), electromagnetic interference (electromagnetic interference) , EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may include passive components and the like for various other purposes. In addition, other components 1040 may be combined with each other together with the chip-related component 1020 or the network-related component 1030 described above.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically connected to or electrically connected to the motherboard 1010 or may be physically connected or not electrically connected to the motherboard 1010. The other components may include, for example, a camera module 1050, an antenna 1060, a display device 1070, a battery 1080, an audio codec (not shown in the figure), a video codec (not shown in the figure), a power amplifier (the figure Not shown), compass (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (such as , Hard disk drive) (not shown), compact disk (CD) drive (not shown), digital versatile disk (DVD) drive (not shown) )Wait. However, the other components are not limited to this, but the type of the end-view electronic device 1000 and the like may include other components for various purposes.

The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PCs, netbook PCs, TVs, video game machines, smart watches, car components, etc. However, the electronic device 1000 is not limited thereto, and may be any other electronic device capable of processing data.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, a semiconductor package may be used in various electronic devices 1000 as described above for various purposes. For example, the motherboard 1110 may be housed in the main body 1101 of the smart phone 1100, and various electronic components 1120 may be physically connected to or electrically connected to the motherboard 1110. In addition, other components (eg, the camera module 1130) that can be physically connected or electrically connected to the motherboard 1110 or can be physically or non-electrically connected to the motherboard 1110 can be housed in the main body 1101. Some electronic components in the electronic component 1120 may be wafer-related components 1020, and the semiconductor package 100 may be, for example, an application processor in the wafer-related components 1020, but is not limited thereto. The electronic device need not be limited to the smart phone 1100, but may be other electronic devices as described above. Semiconductor package

Generally speaking, many fine circuits are integrated in a semiconductor wafer. However, the semiconductor wafer itself cannot be used as a completed semiconductor product, and may be damaged by external physical or chemical shock. Therefore, a semiconductor wafer cannot be used alone, but is packaged in an electronic device or the like and used in a packaged state in the electronic device or the like.

In terms of electrical connection, there is a difference in circuit width between the semiconductor chip and the motherboard of the electronic device, so a semiconductor package is required. In detail, the size of the connection pads of the semiconductor wafer and the interval between the connection pads of the semiconductor wafer are very fine, but the size of the component mounting pads of the motherboard and the component mounting pads of the motherboard used in electronic devices The interval between the connection pads is significantly larger than the size of the connection pads of the semiconductor wafer and the interval between the connection pads. Therefore, it may be difficult to directly mount the semiconductor wafer on the motherboard, and a packaging technology for buffering a difference in circuit width between the semiconductor wafer and the motherboard may be required.

End-view semiconductor packages have the structure and purpose. Semiconductor packages manufactured using packaging technology can be divided into fan-in semiconductor packages and fan-out semiconductor packages.

The fan-in type semiconductor package and the fan-out type semiconductor package will be explained in more detail below with reference to the drawings. Fan-in semiconductor package

3A and 3B are schematic cross-sectional views illustrating states of the fan-in semiconductor package before and after being packaged.

FIG. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in a bare state. The semiconductor wafer 2220 includes a main body 2221 including silicon (Si), germanium (Ge), and gallium arsenide ( GaAs), etc .; a connection pad 2222 formed on one surface of the main body 2221 and containing a conductive material such as aluminum (Al); and a protective layer 2223 such as an oxide film or a nitride film, formed on one surface of the main body 2221 and Covers at least some portions of the connection pad 2222. Here, since the connection pad 2222 is very small, it is difficult to mount an integrated circuit (IC) on an intermediate printed circuit board (PCB), a motherboard of an electronic device, and the like.

Therefore, depending on the size of the semiconductor wafer 2220, an interconnection member 2240 can be formed on the semiconductor wafer 2220 to rewire the connection pads 2222. The interconnection member 2240 can be formed by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as a photoimagable dielectric (PID) resin; and forming a dielectric window hole 2243h that opens the connection pad 2222 ; And then forming a wiring pattern 2242 and an interlayer window 2243. Next, a protective layer 2250 may be formed to protect the interconnection member 2240, an opening 2251 may be formed, and a metal layer 2260 under the bump may be formed. That is, a fan-in semiconductor package 2200 including, for example, a semiconductor wafer 2220, an interconnect member 2240, a protective layer 2250, and a sub-bump metal layer 2260 may be manufactured through a series of processes.

As described above, the fan-in type semiconductor package may have a package in which all connection pads (eg, input / output (I / O) terminals) of the semiconductor wafer are placed in the semiconductor wafer The form can have excellent electrical characteristics and can be produced at low cost. Therefore, many components mounted in a smart phone have been manufactured in the form of a fan-in semiconductor package. In detail, many components installed in a smart phone have been developed to enable fast signal transfer while having a compact size.

However, since all the input / output terminals need to be placed in a semiconductor wafer in a fan-in semiconductor package, the fan-in semiconductor package has significant space limitations. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input / output terminals or a semiconductor wafer having a compact size. In addition, due to the above disadvantages, a fan-in semiconductor package cannot be directly mounted and used on a motherboard of an electronic device. The reason is that even if the size of the input / output terminals of the semiconductor wafer and the interval between the input / output terminals of the semiconductor wafer are increased by the rewiring process, the size of the input / output terminals of the semiconductor wafer and the input / output terminals of the semiconductor wafer are increased. The interval between the output terminals is still insufficient to directly mount the fan-in semiconductor package on the motherboard of the electronic device.

5 is a schematic cross-sectional view illustrating a situation in which a fan-in semiconductor package is mounted on a board substrate and finally mounted on a main board of an electronic device.

FIG. 6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in a board substrate and finally mounted on a main board of an electronic device.

Referring to the drawings, in the fan-in type semiconductor package 2200, the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 may be re-wired again via the interposer substrate 2301, and the fan-in type semiconductor package 2200 may be The fan-in semiconductor package 2200 is finally mounted on the motherboard 2500 of the electronic device in a state of being mounted on the board substrate 2301. Here, the solder balls 2270 and the like can be fixed by underfill resin 2280 and the like, and the outer surface of the semiconductor wafer 2220 can be covered with a molding material 2290 and the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pad 2222 (ie, input / output terminals) of the semiconductor wafer 2220 may be embedded in the interposer. In the state of the substrate 2302, the rewiring is performed again by the interposer substrate 2302, and the fan-in semiconductor package 2200 can be finally mounted on the motherboard 2500 of the electronic device.

As described above, it may be difficult to directly mount and use a fan-in semiconductor package on a motherboard of an electronic device. Therefore, the fan-in type semiconductor package may be mounted on a separate board substrate and then may be mounted on a main board of an electronic device by a packaging process, or may be in a state where the fan-in type semiconductor package is embedded in the board substrate. Install and use on the motherboard of electronic devices. Fan-out semiconductor package

FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

Referring to the drawings, in the fan-out type semiconductor package 2100, for example, the outer surface of the semiconductor wafer 2120 may be protected by the encapsulation body 2130, and the connection pad 2122 of the semiconductor wafer 2120 may be formed by the interconnection member 2140. Rewiring is performed outside the semiconductor wafer 2120. In this case, a protective layer 2150 may be further formed on the interconnection member 2140, and an under bump metal layer 2160 may be further formed in the opening of the protective layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit (IC) including a main body 2121, a connection pad 2122, a protective layer (not shown in the figure), and the like. The interconnection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a via window 2143 that electrically connects the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have an input / output terminal in which a semiconductor wafer is rewired outside the semiconductor wafer by an interconnection member formed on the semiconductor wafer and disposed on the semiconductor wafer. Forms other than semiconductor wafers. As described above, in a fan-in type semiconductor package, all input / output terminals of a semiconductor wafer need to be placed in the semiconductor wafer. Therefore, when the size of a semiconductor wafer is reduced, it is necessary to reduce the size and pitch of the balls, thereby making it impossible to use a standardized ball layout in a fan-in semiconductor package. On the other hand, the fan-out type semiconductor package has an input / output terminal in which a semiconductor wafer is rewired outside the semiconductor wafer and placed outside the semiconductor wafer by an interconnection member formed on the semiconductor wafer as described above. form. Therefore, even in the case where the size of the semiconductor wafer is reduced, it is actually possible to use a standardized ball layout in a fan-out semiconductor package, thereby enabling the fan-out semiconductor package to be used without a separate interposer substrate. Installed on the motherboard of the electronic device under conditions, as explained below.

FIG. 8 is a schematic cross-sectional view illustrating a case where a fan-out type semiconductor package is mounted on a main board of an electronic device.

Referring to the drawings, the fan-out semiconductor package 2100 can be mounted on the main board 2500 of the electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes the interconnection member 2140 formed on the semiconductor wafer 2120 and capable of rewiring the connection pad 2122 to a fan-out area outside the size of the semiconductor wafer 2120, and further This makes it possible to actually use a standardized ball layout in the fan-out type semiconductor package 2100. Therefore, the fan-out type semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device without using a separate interposer substrate or the like.

As described above, since the fan-out type semiconductor package can be mounted on a motherboard of an electronic device without using a separate board substrate, the fan-out type semiconductor package can be more than a fan-in type using a board substrate The semiconductor package is implemented with a small thickness. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, which makes the fan-out semiconductor package particularly suitable for mobile products. Therefore, the fan-out type semiconductor package can be implemented in a more compact form than a general package-on-package (POP) type using a printed circuit board (PCB), and can solve the problem caused by warping (Warpage) phenomenon.

Meanwhile, the fan-out semiconductor package refers to a packaging technology for mounting a semiconductor wafer on a motherboard of an electronic device or the like as described above and protecting the semiconductor wafer from external impact, and the fan-out semiconductor package is conceptually It is different from a printed circuit board (PCB) (for example, a board substrate, etc.) having a scale, purpose, etc. different from that of a fan-out type semiconductor package, and a fan-in type is embedded in the printed circuit board Semiconductor packaging.

Hereinafter, a fan-out type semiconductor package in which corrosion of a connection pad, which may occur due to various reasons, can be prevented will be explained with reference to the drawings.

FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package.

FIG. 10 is a schematic plan view taken along a line II ′ of the fan-out type semiconductor package shown in FIG. 9.

Referring to the drawings, a fan-out type semiconductor package 100A according to an exemplary embodiment of the present invention may include: a first interconnection member 110 having a through hole 110H; and a semiconductor wafer 120 disposed on the first interconnection member 110. The through hole 110H has an active surface and a passive surface opposite to the active surface, and a connection pad 122 is disposed on the active surface; an encapsulation body 130 encapsulates at least some parts of the first interconnection member 110 and At least some parts of the passive surface of the semiconductor wafer 120; a second interconnecting member 140 disposed on the first interconnecting member 110 and an active surface of the semiconductor wafer 120; a protective layer 150 disposed on the second interconnecting member 140 ; The under bump metal layer 160 is disposed in the opening 151 of the protective layer 150; and the connection terminal 170 is formed on the under bump metal layer 160. The semiconductor wafer 120 may include a protective layer 123 having an opening exposing at least some portions of the connection pad 122. The connection pad 122 may be connected to the redistribution layer 142 via the via window 143 of the second interconnection member 140. In this case, the via window 143 may be located on at least some portions of the protective layer 123. Therefore, the interlayer window 143 can cover the entire surface exposed by the opening of the protected layer 123 of the connection pad 122. That is, the connection pad 122 may not contact the insulating layer 141.

Generally, a semiconductor package can be manufactured by a conventional packaging method in which a wafer in which a circuit is formed on a silicon wafer in a pre-processing process is mounted on a lead frame substrate in a post-processing process, and then the wafer is Molded. However, recently, the following fan-out type packaging technology has become increasingly prominent: firstly, a wafer is molded and a fine circuit is directly formed in an area including a molding area without using a lead frame substrate. The fan-out type packaging technology refers to a technology of first molding the wafer in a state where the connection pads of the wafer are exposed to extend the area in which the fine circuits and connection terminals are formed to the molding area, and The fan-out type packaging technology can utilize low-cost package molding to ensure the space corresponding to the number of inputs / outputs and spaces required for mounting. Therefore, the chip can be embedded in an ultra-miniaturized / high-integrated expensive silicon wafer to ensure the connection to the board, without using a lead frame substrate, thereby reducing costs and shortening the wiring distance, thus making it possible to Reduce inductance and power consumption.

Because the technology for refining silicon pretreatment in the semiconductor industry has reached physical limits, it has been due to the miniaturization of silicon wafers and investment in extreme ultra-violet (EUV) lithography technology as a new exposure method The burden has accelerated the development of inexpensive chip packaging technologies including fan-out wafer-level packaging. However, due to the thinness of the layers made of various materials, the reduction in the board mounting process and the decrease in the reliability of the acceleration caused by the concentration of the stress on the minute parts have not been used for a long time. produce. In order to improve the reliability of the board mounting process, an underfill method may be considered in which the space between the connection terminals connecting the package and the board to each other is filled with an adhesive resin after the package is mounted on the board.

However, in the underfill method, in order to ensure the process properties, it is necessary to use a material that can be reprocessed, and this material contains a relatively large concentration and a higher concentration of Cl ^- ions. Under temperature-humidity bias (THB) conditions, Cl ^- ions contained in the underfill may be dispersed into the polymer insulating layer 141 ′ to reach the connection pad 122 ′, as shown in FIG. 14. The Cl ⁻ ions that reach the connection pad 122 ′ as described above can cause corrosion to the connection pad of the semiconductor wafer in both the state where no voltage is applied and the state where the voltage is applied, as shown in FIGS. 15 and 16. To prevent corrosion of the connection pads due to Cl ^- ions, consider reducing Cl ^- ions in the underfill, inserting a Cl ^- ion trap layer, adding dummy electrodes, and the like. However, reducing the Cl ^- ions in the underfill deteriorates the reworking properties, and the Cl ^- ion trap layer requires an inorganic filler, and therefore it is difficult to insert the Cl ^- ion trap layer into the insulating layer on which a fine pattern should be implemented. . In addition, inserting the dummy electrode only reduces the corrosion rate to the connection pad. Therefore, inserting a dummy electrode is not a basic countermeasure to guarantee long-term execution of warm and humid conditions.

On the other hand, the via window 143 in which the second interconnection member 140 is formed over at least some portions of the protective layer 123 so that the connection pad 122 does not contact the insulating layer 141, that is, prevents the connection pad 122 from being exposed. In the case of a path through which ions pass, as in the fan-out type semiconductor package 100A according to the exemplary embodiment, introduction of ions into the connection pad 122 can be effectively blocked. As a result, corrosion of the connection pads 122 of the semiconductor wafer 120 as described above, which may occur due to various reasons under temperature-humidity bias (THB) conditions, can be prevented.

When the width of the surface of the contact layer 143 of the protective layer 123 surrounding the opening of the protective layer 123 at the same time is W, and the edge of the contact layer 123 of the protective layer 143 and the contact layer 143 of the protective layer 123 simultaneously surround the protective layer 123 When the center line C of the surface of the opening is separated by a distance d, d / W may be less than or equal to 0.3. Here, d may be a distance spaced in an inward direction (d ₁ ) or an outward direction (d ₂ ). In the case where the interposer window 143 is formed such that the edges of the interposer window 143 are positioned to be 20% or more apart from the inner and outer edges of the protective layer 123 as described above, the interposer window 143 is under stress Aspects can be stable. In a case where the edge of the interlayer window 143 is positioned adjacent to the edge of the protective layer 123, the stress applied to the protective layer 123 may increase, thus making T / C stability problems possible.

When the entire area of the surface of the protective layer 123 contacting the interlayer window 143 while surrounding the opening of the protective layer 123 is S ₁ and the area of the cover protective layer 123 of the interlayer window 143 is S ₂ , S ₂ / S ₁ may be approximately In the range of 0.2 to 0.8. Similarly, in the case where the interlayer window 143 is formed such that the edges of the interlayer window 143 are positioned to be spaced apart from the inner and outer edges of the protective layer 123 by 20% or more, the interlayer window 143 is under stress Aspects can be stable. Therefore, the area of the cover and protection layer 123 of the interlayer window 143 may be about 20% to 80% of the entire area, and within this range, the interlayer window 143 may be the most stable in terms of stress.

At the same time, the via window may be a filled via. In the case where the interposer window is a filled interposer window as described above, the metal ratio increases, thereby making the interposer window more stable in terms of stress and more effectively blocking the introduction of ions.

The respective components included in the fan-out type semiconductor package 100A according to an exemplary embodiment will be explained in more detail below.

The first interconnection member 110 may include a redistribution layer 112 a and a redistribution layer 112 b that re-routes the connection pad 122 to thereby reduce the number of layers of the second interconnection member 140. If necessary, the first interconnection member 110 can maintain the rigidity of the fan-out semiconductor package 100A depending on the material, and is used to ensure the thickness uniformity of the encapsulation body 130. In some cases, due to the first interconnection member 110, the fan-out type semiconductor package 100A according to an exemplary embodiment may be used as a part of a stacked package. The first interconnection member 110 may have a through hole 110H. A semiconductor wafer 120 may be disposed in the through hole 110H to be spaced a predetermined distance from the first interconnection member 110. A side surface of the semiconductor wafer 120 may be surrounded by the first interconnection member 110. However, this form is merely an example and can be modified into other forms in various ways, and the fan-out type semiconductor package 100A can perform another function depending on the form.

The first interconnection member 110 may include: an insulation layer 111 that contacts the second interconnection member 140; a first redistribution layer 112a that contacts the second interconnection member 140 and is embedded in the insulation layer 111; and a second redistribution layer 112b Is disposed on the other surface of the insulating layer 111 opposite to one surface of the insulating layer 111 in which the first redistribution layer 112a is embedded. The first interconnection member 110 may include a via window 113 that penetrates the insulating layer 111 and electrically connects the first redistribution layer 112 a and the second redistribution layer 112 b to each other. The first redistribution layer 112 a and the second redistribution layer 112 b may be electrically connected to the connection pad 122. When the first redistribution layer 112a is embedded in the insulating layer 111, a step due to the thickness of the first redistribution layer 112a can be significantly reduced, and the insulation distance of the second interconnection member 140 can therefore be made constant. That is, the difference between the distance from the redistribution layer 142 of the second interconnection member 140 to the lower surface of the insulating layer 111 and the distance from the redistribution layer 142 of the second interconnection member 140 to the connection pad 122 may be smaller than the first distance. The thickness of the wiring layer 112a. Therefore, the high-density wiring design of the second interconnection member 140 may be easy.

The material of the insulating layer 111 is not particularly limited. For example, an insulating material may be used as a material of the insulating layer 111. In this case, the following materials may be used as the insulating material: a thermosetting resin such as epoxy resin; a thermoplastic resin such as polyimide resin; wherein the thermosetting resin or thermoplastic resin and an inorganic filler are impregnated, for example, glass cloth ( Or glass fiber) resins in core materials, such as prepreg, Ajinomoto Build up Film (ABF), FR-4, bismaleimide triazine (BT )Wait. Alternatively, a photosensitive imaging dielectric (PID) resin may be used as the insulating material.

The redistribution layer 112a and the redistribution layer 112b may be used for redistribution of the connection pads 122 of the semiconductor wafer 120, and the following materials may be used as materials for each of the redistribution layer 112a and the redistribution layer 112b: for example, copper (Cu ), Aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof and other conductive materials. The redistribution layer 112a and the redistribution layer 112b may perform various functions depending on the design of their corresponding layers. For example, the redistribution layer 112a and the redistribution layer 112b may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, and the like, such as a data signal. In addition, the redistribution layer 112a and the redistribution layer 112b may include a via window pad, a connection terminal pad, and the like. As a non-limiting example, both the redistribution layer 112a and the redistribution layer 112b may include a ground pattern. In this case, the number of ground patterns formed on the redistribution layer 142 of the second interconnection member 140 can be significantly reduced, so that the degree of freedom in wiring design can be improved.

If necessary, a surface treatment layer (not shown) may be further formed on some patterns of the redistribution layer 112b and the redistribution layer 112b exposed through the opening 131. The surface treatment layer (not shown in the figure) is not particularly limited as long as the surface treatment layer (not shown in the figure) is conventionally known in the related art, and the surface treatment layer (see FIG. (Not shown) may use, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin, electroless silver, electroless nickel / replacement gold, direct immersion gold , DIG) plating, hot air solder leveling (HASL), etc.

The interlayer window 113 may electrically connect the redistribution layer 112 a and the redistribution layer 112 b formed on different layers, thereby generating an electrical path in the first interconnection member 110. A conductive material may also be used as a material of each of the via windows 113. Each of the via windows 113 may be completely filled with a conductive material as shown in FIG. 10, or the conductive material may also be formed along the wall of each of the via windows. In addition, each of the via windows 113 may have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like.

The semiconductor wafer 120 may be an integrated circuit (IC) configured to integrate a number of hundreds to millions of elements or more in a single wafer. For example, the integrated circuit may be an application processor chip, such as a central processing unit (for example, a central processing unit), a graphics processor (for example, a graphics processing unit), a digital signal processor, a cryptographic processor, a microcomputer Processors, microcontrollers, etc., but not limited to them. The semiconductor wafer 120 may be formed based on an active wafer. In this case, the base material of the main body 121 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the main body 121. The connection pad 122 may electrically connect the semiconductor wafer 120 to other components, and a conductive material such as aluminum (Al) may be used as a material of each of the connection pads 122. A protective layer 123 having an opening exposing the connection pad 122 may be formed on the main body 121, and the protective layer 123 may be formed of, for example, an oxide film made of SiO or the like, a nitride film made of SiN or the like, or an oxide film The film is formed as a double layer with a nitride film. With the protective layer 123, the lower surface of the connection pad 122 may have a step relative to the lower surface of the encapsulation body 130. As a result, a phenomenon in which the encapsulation body 130 penetrates into the lower surface of the connection pad 122 can be prevented to some extent. An insulation layer (not shown in the figure) and the like may be further disposed at other required positions.

The passive surface of the semiconductor wafer 120 may be disposed at a level lower than an upper surface of the second redistribution layer 112 b of the first interconnection member 110. For example, the passive surface of the semiconductor wafer 120 may be disposed at a level lower than the upper surface of the insulating layer 111 of the first interconnection member 110. A height difference between a passive surface of the semiconductor wafer 120 and an upper surface of the second redistribution layer 112 b of the first interconnection member 110 may be 2 micrometers (μm) or more, for example, 5 micrometers or more. In this case, it is possible to effectively prevent cracks from occurring in the corners of the passive surface of the semiconductor wafer 120. In addition, the deviation of the insulation distance on the passive surface of the semiconductor wafer 120 in the case where the encapsulation body 130 is used can be significantly reduced.

The encapsulation body 130 may protect the first interconnection member 110 or the semiconductor wafer 120. The encapsulation form of the encapsulation body 130 is not particularly limited, but may be a form in which the encapsulation body 130 surrounds at least some parts of the first interconnection member 110 or at least some parts of the semiconductor wafer 120. For example, the encapsulation body 130 may cover the passive surfaces of the first interconnection member 110 and the semiconductor wafer 120 and fill a space between the wall of the through hole 110H and the side surface of the semiconductor wafer 120. In addition, the encapsulation body 130 may also fill at least a part of the space between the protective layer 123 of the semiconductor wafer 120 and the second interconnection member 140. At the same time, the encapsulation body 130 may fill the through-hole 110H so as to act as an adhesive and reduce buckling of the semiconductor wafer 120.

The material of the encapsulation body 130 is not particularly limited. For example, an insulating material may be used as a material of the encapsulation body 130. In this case, the following materials can be used as the insulating material: a thermosetting resin, such as an epoxy resin; a thermoplastic resin, such as a polyimide resin; and a reinforcing material such as an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin. Resins, such as Ajinomoto constituting film, FR-4, bismaleimide triazine, photosensitive imaging dielectric resin, and the like. In addition, a conventional molding material such as an epoxy molding compound (EMC) can also be used. Alternatively, a resin in which a thermosetting resin or a thermoplastic resin and an inorganic filler are impregnated in a core material such as glass cloth (or glass fiber) may be used as the insulating material.

The encapsulation body 130 may include a plurality of layers formed of a plurality of materials. For example, the space within the through hole 110H may be filled with a first encapsulation body, and the first interconnection member 110 and the semiconductor wafer 120 may be covered with a second encapsulation body. Alternatively, the first encapsulation body can cover the first interconnecting member 110 and the semiconductor wafer 120 with a predetermined thickness while filling the space in the through hole 110H, and the second encapsulation body can cover the first encapsulation again with a predetermined thickness. body. In addition to the above, various forms can be used.

If desired, the encapsulation body 130 may include conductive particles to block electromagnetic waves. For example, the conductive particles can be any material that can block electromagnetic waves, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), solder, etc. However, this is only an example, and the conductive particles are not limited thereto.

The second interconnection member 140 may be configured to rewire the connection pads 122 of the semiconductor wafer 120. Dozens to hundreds of connection pads 122 having various functions can be rewired by the second interconnection member 140, and can be physically connected or electrically connected to the outside via the connection terminal 170 depending on the functions. source. The second interconnection member 140 may include: an insulating layer 141; a redistribution layer 142 disposed on the insulating layer 141; and a via window 143 passing through the insulating layer 141 and connecting the redistribution layers 142 to each other. The second interconnection member 140 may be formed of a single layer, or may be formed of a plurality of layers differently from the drawing.

An insulating material may be used as a material of each of the insulating layers 141. In this case, in addition to the above-mentioned insulating material, a photosensitive insulating material such as a photosensitive imaging dielectric resin may be used as the insulating material. In this case, the insulating layer 141 may be formed to have a smaller thickness, and the fine pitch of the via window 143 may be more easily achieved. When the insulating layer 141 is a plurality of layers, the materials of the respective insulating layers 141 may be the same as each other, and may also be different from each other. When the insulating layer 141 is a plurality of layers, the insulating layers 141 may be integrated with each other, so that a boundary between the insulating layers 141 may not be easily apparent.

The redistribution layer 142 may be substantially used for redistribution of the connection pads 122, and the following materials may be used as a material of each of the redistribution layers 142: for example, copper (Cu), aluminum (Al), silver (Ag) , Tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof and other conductive materials. The redistribution layer 142 may perform various functions depending on the design of its corresponding layer. For example, the redistribution layer 142 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, and the like, such as a data signal. In addition, the redistribution layer 142 may include a via window pad, a connection terminal pad, and the like.

If necessary, a surface treatment layer (not shown in the figure) may be further formed on some patterns exposed by the weight wiring layer 142. The surface treatment layer (not shown in the figure) is not particularly limited as long as the surface treatment layer is known in the related art, and the surface treatment layer may be formed by, for example, electrolytic gold plating, It is formed by electroplating gold, organic solderability protection, or electroless tin, electroless silver, electroless nickel / replacement gold plating, direct immersion gold plating, hot air solder coating, etc.

The interlayer window 143 can electrically connect the redistribution layer 142, the connection pad 122, and the like formed on different layers, thereby generating an electrical path in the fan-out semiconductor package 100A. The following materials can be used as the material of each of the interlayer windows 143: for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead ( Pb), titanium (Ti), or an alloy thereof and other conductive materials. The via window 143 may be located on at least some portions of the protective layer 123 and cover the entire exposed surface of the connection pad 122. The via window 143 may be a filled via window, but is not limited thereto. The via window 143 may have a tapered shape whose diameter decreases toward the connection pad 122, but is not limited thereto.

The via window 143 may include a seed layer 143a and a conductive layer 143b. The seed layer 143 a may be formed on the exposed surface of the connection pad 122, the wall of the protective layer 123, the surface of the protective layer 123, and the wall of the via hole passing through the insulating layer 141. The conductive layer 143b may be formed on the seed layer 143a and fill the via hole. The seed layer 143a may include a first seed layer and a second seed layer. The first seed layer includes a material selected from the group consisting of titanium (Ti), titanium-tungsten (Ti-W), molybdenum (Mo), and chromium (Cr ), Nickel (Ni), and nickel-chromium (Ni-Cr), the second seed layer is disposed on the first seed layer and includes a conductive layer 143b The same material, such as copper (Cu). The first seed layer may serve as an adhesive, and the second seed layer may serve as a basic plating layer. The conductive layer 143b may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or an alloy thereof, and generally May contain copper (Cu).

When the width of the surface of the contact layer 143 of the protective layer 123 surrounding the opening of the protective layer 123 at the same time is W, and the edge of the contact layer 123 of the protective layer 143 and the contact layer 143 of the protective layer 123 simultaneously surround the protective layer 123 When the center line C of the surface of the opening is separated by a distance d, d / W may be less than or equal to 0.3. Here, d may be a distance spaced in an inward direction (d ₁ ) or an outward direction (d ₂ ). In the case where the interposer window 143 is formed such that the edges of the interposer window 143 are positioned to be 20% or more apart from the inner and outer edges of the protective layer 123 as described above, the interposer window 143 is under stress Aspects can be stable. When the edge of the interposer window 143 is positioned adjacent to the edge of the protective layer 123, the stress applied to the protective layer 123 increases, thus making T / C reliability issues possible.

When the entire area of the surface of the protective layer 123 that contacts the interlayer window 143 while surrounding the opening of the protective layer 123 is S ₁ and the area of the cover protective layer 123 of the interlayer window 143 is S ₂ , S ₂ / S ₁ may be approximately In the range of 0.2 to 0.8. Similarly, in the case where the interlayer window 143 is formed such that the edges of the interlayer window 143 are positioned to be spaced apart from the inner and outer edges of the protective layer 123 by 20% or more, the interlayer window 143 is under stress Aspects can be stable. Therefore, the area of the cover and protection layer 123 of the interlayer window 143 may be about 20% to 80% of the entire area, and within this range, the interlayer window 143 may be the most stable in terms of stress.

The thicknesses of the redistribution layer 112 a and the redistribution layer 112 b of the first interconnection member 110 may be greater than the thickness of the redistribution layer 142 of the second interconnection member 140. Since the first interconnection member 110 may have a thickness equal to or larger than the thickness of the semiconductor wafer 120, depending on the scale of the first interconnection member 110, the weight of the first interconnection member 110 formed in the first interconnection member 110 is large. The wiring layer 112a and the redistribution layer 112b may be formed to be relatively large. On the other hand, the redistribution layer 142 of the second interconnecting member 140 may be formed with a relatively smaller size than the size of the redistribution layer 112a and the redistribution layer 112b of the first interconnecting member 110 to achieve the second interconnecting member 140. Thinness.

The protective layer 150 may be configured to protect the second interconnection member 140 from external physical damage or chemical damage. The protective layer 150 may have an opening 151 that exposes at least some portions of one of the redistribution layers 142 of the second interconnection member 140. The opening 151 may expose the entire surface of the redistribution layer 142 or only a portion of the surface of the redistribution layer 142. In some cases, each of the openings 151 may expose a side surface of the redistribution layer 142.

The material of the protective layer 150 is not particularly limited, and may be, for example, a photosensitive insulating material. Alternatively, a solder resist may be used as a material of the protective layer 150. Alternatively, as the material of the protective layer 150, an insulating resin (for example, an Ajinomoto-containing film including an inorganic filler and an epoxy resin) that does not include a core material but includes a filler may be used. The surface roughness of the protective layer 150 may be lower than that in a general case. When the surface roughness is low as described above, several side effects (such as stains on the surface, difficulty in implementing fine circuits, etc.) that may occur during the circuit formation process can be improved.

The under-bump metal layer 160 may be additionally configured to improve connection reliability of the connection terminal 170 to improve board-level reliability. The under bump metal layer 160 may fill at least some portions of the opening 151. The under bump metal layer 160 may be formed by a conventional metallization method. The under bump metal layer 160 may include a conventional metal. The under bump metal layer 160 may be formed by forming a seed layer using electroplated copper and forming a plating layer on the seed layer using electroless copper.

The connection terminal 170 may be additionally configured to connect the fan-out semiconductor package 100A physically or electrically externally. For example, the fan-out semiconductor package 100A can be mounted on a motherboard of an electronic device via a connection terminal 170. Each of the connection terminals 170 may be formed of a conductive material such as solder. However, this is only an example, and the material of each of the connection terminals 170 is not limited thereto. Each of the connection terminals 170 may be a land, a ball, a pin, or the like. The connection terminal 170 may be formed of a plurality of layers or a single layer. When the connection terminal 170 is formed of a plurality of layers, the connection terminal 170 may include a copper pillar and solder. When the connection terminal 17 is formed of a single layer, the connection terminal 170 may include tin-silver solder or copper. However, this is only an example, and the connection terminal 170 is not limited to this. The number, interval, and arrangement of the connection terminals 170 are not particularly limited, but can be sufficiently modified by those skilled in the art depending on the design details. For example, according to the number of connection pads 122 of the semiconductor wafer 120, the connection terminals 170 may be set to a number of tens to thousands, but it is not limited thereto, and may be set to tens to thousands or more The number, or the number from tens to thousands or less.

At least one of the connection terminals 170 may be disposed in the fan-out area. The fan-out region is a region other than a region in which the semiconductor wafer 120 is disposed. That is, the fan-out type semiconductor package 100A according to an exemplary embodiment may be a fan-out type package. Compared with the fan-in package, the fan-out package can have excellent reliability, the fan-out package can implement multiple input / output (I / O) terminals, and can benefit 3D interconnection. In addition, unlike a ball grid array (BGA) package and a land grid array (LGA) package, the fan-out package can be mounted on an electronic device without the need for a separate board. . Therefore, the fan-out type package can be thinned and can be price competitive.

Although not shown in the drawings, if necessary, a metal layer may be further disposed on an inner sidewall of the through hole 110H of the first interconnection member 110. That is, the side surface of the semiconductor wafer 120 may also be surrounded by the metal layer. With the metal layer, heat generated by the semiconductor wafer 120 can be efficiently radiated in an upward direction or a downward direction of the fan-out type semiconductor package 100A, and through the metal layer, electromagnetic waves can be effectively blocked. In addition, if necessary, a plurality of semiconductor wafers may be placed in the through-holes 110H of the first interconnecting member 110, and the number of the through-holes 110H of the first interconnecting member 110 may be plural and the semiconductor wafers may be separately placed in all of them. Said through-hole. In addition, a separate passive component may be encapsulated in the through hole 110H together with the semiconductor wafer. In addition, a surface mount technology (SMT) component may be mounted on the protective layer 150.

FIG. 11 is a graph schematically illustrating a change in stress depending on a position where a via layer of a second interconnection member of the fan-out type semiconductor package shown in FIG. 9 covers a protective layer of a semiconductor wafer.

Referring to the drawing, # 1 refers to the case where the edge of the interposer window 143 is substantially close to the inner edge of the surface of the protective layer 123 contacting the interposer window 143, that is, the cover protection of the interposer window 143 The T / C reliability test result in a case where the area S _{2 of the} layer 123 is smaller than 20% (less than 20%) of the entire area S ₁ of the surface of the contact layer 143 of the protective layer 123, # 2 to # 5 refer to in the case where the edge of the window 143 which is adjacent the interposer protective layer 123 in contact with the center line C vias located surface 143, i.e. the area in which the protective window covering interposer layer 123 corresponding to the 143 S ₂ of the protective layer T / C reliability test results in the case where the entire area S ₁ of the surface of the contact via 143 is 20% to 80% (the spaced distance is within 30%), and # 6 refers to the middle In the case where the edge of the layer window 143 is substantially close to the outer edge of the surface of the protective layer 123 contacting the interposer window 143, that is, in which the area S _{2 of the} interlayer window 143 covering the protective layer 123 exceeds the contact layer of the protective layer 123 T / C reliability test result in the case (less than 20%) of the entire area S ₁ of the surface of the layer window 143.

Therefore, it can be understood that when the width of the surface of the contact layer 143 of the protective layer 123 surrounding the opening of the protective layer 123 at the same time is W and the edge of the contact layer 143 of the contact layer 143 and the contact layer 143 of the protective layer 123 When the center line C surrounding the opening surface of the protective layer 123 is spaced apart by a distance d, the interlayer window 143 may be stable in terms of stress in a case where d / W is within 0.3. In addition, it can be understood that when the entire area of the surface of the protective layer 123 that contacts the interlayer window 143 while surrounding the opening of the protective layer 123 is S ₁ and the area of the protective layer 123 that covers the interlayer window 143 is S ₂ , the interlayer window 143 may be stable in terms of stress in a case where S ₂ / S _{1 is} in a range of about 0.2 to 0.8.

FIG. 12 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 100B according to another exemplary embodiment of the present invention, the first interconnection member 110 may include: a first insulating layer 111 a that contacts the second interconnection member 140; The first redistribution layer 112a contacts the second interconnecting member 140 and is embedded in the first surface of the first insulating layer 111a; the second redistribution layer 112b is disposed on the first insulating layer 111a and the first insulating layer 111a On the second surface opposite to the first surface; a second insulating layer 111b is disposed on the first insulating layer 111a and covers the second redistribution layer 112b; and a third redistribution layer 112c is disposed on the second insulating layer 111b on. The first redistribution layer 112a, the second redistribution layer 112b, and the third redistribution layer 112c may be electrically connected to the connection pad 122. At the same time, the first redistribution layer 112a and the second redistribution layer 112b, the second redistribution layer 112b, and the third redistribution layer 112c may pass through the first interlayer of the first insulating layer 111a and the second insulating layer 111b, respectively. The window and the second interlayer window (not shown in the figure) are electrically connected to each other.

Since the first redistribution layer 112a is embedded in the first insulation layer 111a, as described above, the insulation distance of the insulation layer 141 of the second interconnection member 140 may be substantially constant. Since the first interconnection member 110 may include a large number of redistribution layers 112a, redistribution layers 112b, and redistribution layers 112c, the second interconnection member 140 may be further simplified. Therefore, a decrease in the yield due to a defect occurring in a process of forming the second interconnection member 140 can be improved. The first redistribution layer 112a may be recessed in the first insulation layer 111a, so that the lower surface of the first insulation layer 111a may have a step relative to the lower surface of the first redistribution layer 112a. As a result, when the encapsulation body 130 is formed, a phenomenon in which the material of the encapsulation body 130 penetrates and contaminates the first redistribution layer 112a can be prevented.

The lower surface of the first redistribution layer 112 a of the first interconnection member 110 may be disposed at a level higher than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, a distance between the redistribution layer 142 of the second interconnection member 140 and the first redistribution layer 112 a of the first interconnection member 110 may be greater than a connection between the redistribution layer 142 of the second interconnection member 140 and the semiconductor wafer 120. The distance between the pads 122. The reason is that the first redistribution layer 112a may be recessed in the first insulating layer 111a. The second redistribution layer 112b of the first interconnection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120. The first interconnection member 110 may be formed at a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the second redistribution layer 112 b formed in the first interconnection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120.

The thicknesses of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the first interconnection member 110 may be larger than the thickness of the redistribution layer 142 of the second interconnection member 140. Since the first interconnection member 110 may have a thickness equal to or larger than the thickness of the semiconductor wafer 120, depending on the scale of the first interconnection member 110, the redistribution layer 112a, the redistribution layer 112b, and The redistribution layer 112c may be formed to be relatively large. On the other hand, the redistribution layer 142 of the second interconnection member 140 may be formed to be relatively small to achieve a thinness.

The configuration overlapping with the previously described configuration will not be repeated.

FIG. 13 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out type semiconductor package 100C according to another exemplary embodiment of the present invention, the first interconnection member 110 may include: a first insulating layer 111a; a first redistribution layer 112a; The double wiring layer 112b is disposed on both surfaces of the first insulating layer 111a; the second insulating layer 111b is disposed on the first insulating layer 111a and covers the first red wiring layer 112a; the third red wiring layer 112c, It is disposed on the second insulating layer 111b; a third insulating layer 111c is disposed on the first insulating layer 111a and covers the second redistribution layer 112b; and a fourth redistribution layer 112d is disposed on the third insulating layer 111c. The first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may be electrically connected to the connection pad 122. Since the first interconnection member 110 may include a larger number of redistribution layers 112a, redistribution layers 112b, redistribution layers 112c, and redistribution layers 112d, the second interconnection member 140 may be further simplified, and Yield reduction due to defects in the two interconnecting members 140. Meanwhile, the first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may pass through the first insulating layer 111a, the second insulating layer 111b, and the third through The first to third interlayer windows of the insulating layer 111c are electrically connected to each other.

The first insulating layer 111a may have a thickness larger than that of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be substantially thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of redistribution layers 112c and 112d. The first insulating layer 111a may include an insulating material different from that of the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be a flavor including the inorganic filler and the insulating resin Element constituting a film or a photosensitive insulating film. However, the materials of the first insulating layer 111a and the materials of the second insulating layer 111b and the third insulating layer 111c are not limited thereto.

The lower surface of the third redistribution layer 112c of the first interconnection member 110 may be disposed at a level lower than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second interconnection member 140 and the third redistribution layer 112c of the first interconnection member 110 may be smaller than the connection between the redistribution layer 142 of the second interconnection member 140 and the semiconductor wafer 120. The distance between the pads 122. The reason is that the third redistribution layer 112c may be disposed on the second insulating layer 111b in a protruding form so as to contact the second interconnection member 140. The first redistribution layer 112a and the second redistribution layer 112b of the first interconnection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120. The first interconnection member 110 may be formed at a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the first redistribution layer 112 a and the second redistribution layer 112 b formed in the first interconnection member 110 may be disposed at a level between the active surface and the passive surface of the semiconductor wafer 120.

The thicknesses of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d of the first interconnection member 110 may be greater than the thickness of the redistribution layer 142 of the second interconnection member 140. Since the first interconnection member 110 may have a thickness equal to or larger than the thickness of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d may also be formed. Is formed to be relatively large. On the other hand, the redistribution layer 142 of the second interconnection member 140 may be formed to be relatively small to achieve a thinness.

The configuration overlapping with the previously described configuration will not be repeated.

FIG. 14 is a schematic diagram illustrating a case where corrosion occurs on the connection pad.

FIG. 15 is a schematic diagram illustrating corrosion of a connection pad in a state where no voltage is applied.

FIG. 16 is a schematic diagram illustrating corrosion of a connection pad in a state where a voltage is applied.

Referring to the drawings, a semiconductor package may be mounted on a board 500 'via a connection terminal 170'. The connection terminal 170 'can be electrically connected to the electrode 502' exposed from the insulating layer 501 'of the board 500'. The connection terminal 170 'can be electrically connected to the connection pad 122' via a redistribution layer 142 'formed in the polymer insulating layer 141'. Meanwhile, the connection terminal 170 'may be fixed by the underfill 200'. In this case, under temperature-humidity bias (THB) conditions, for example, Cl ^- plasma of the underfill 200 'can penetrate the polymer insulating layer 141' to etch the connection pad 122 'of the semiconductor wafer. In detail, the surface of the protective layer 123 ′ exposed from the connection pad 122 ′ and formed on the body 121 ′ of the semiconductor wafer may be corroded by, for example, Cl ⁻ plasma under the temperature and humidity bias conditions. That is, in a case where the interlayer window 143 is not formed to cover the protective layer 123, unlike the fan-out type semiconductor package 100A to 100C according to the present invention, the connection pads of the semiconductor wafer are not applied with a voltage. It can be corroded in the state of being applied or the state of applying voltage.

As proposed above, according to the exemplary embodiments of the present invention, it is possible to provide a fan-out type semiconductor package in which corrosion of a connection pad, which may occur due to various reasons, can be prevented.

Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined by the scope of the accompanying patent application. transform.

100‧‧‧Semiconductor Package
100A, 100B, 100C‧‧‧fan-out semiconductor package
110‧‧‧first interconnecting member
110H‧‧‧through hole
111, 141, 501 ', 2141, 2241‧‧‧ insulating layer
111a‧‧‧First insulation layer
111b‧‧‧Second insulation layer
111c‧‧‧Third insulation layer
112a‧‧‧Rewiring layer / First rewiring layer
112b‧‧‧ Redistribution Layer / Second Redistribution Layer
112c‧‧‧ Redistribution Layer / Third Redistribution Layer
112d‧‧‧ redistribution layer / fourth redistribution layer
113, 143, 2143, 2243
120, 2120, 2220‧‧‧ semiconductor wafer
121, 121'‧‧‧ Subject
122, 122 ', 2122, 2222‧‧‧ connecting pads
123, 123 ', 150, 2150, 2223, 2250‧‧‧
130, 2130 ‧ ‧ capsules
131, 151, 2251‧‧‧ opening
140‧‧‧Second interconnecting component
141'‧‧‧ polymer insulation
142, 142 ', 2142‧‧‧ redistribution layer
143a‧‧‧Seed layer
143b‧‧‧conductor layer
160, 2160, 2260‧‧‧ metal layer under bump
170, 170'‧‧‧ connecting terminal
200'‧‧‧ underfill
500'‧‧‧board
502'‧‧‧ electrode
1000‧‧‧ electronic device
1010, 1110, 2500‧‧‧ Motherboard
1020‧‧‧Chip-related components
1030‧‧‧Network related components
1040‧‧‧Other components
1050, 1130‧‧‧ Camera Module
1060‧‧‧antenna
1070‧‧‧Display device
1080‧‧‧ battery
1090‧‧‧Signal line
1100‧‧‧Smartphone
1101, 2121, 2221‧‧‧ main body
1120‧‧‧Electronic components
2100‧‧‧fan-out semiconductor package
2140, 2240‧‧‧ interconnecting components
2170, 2270‧‧‧solder ball
2200‧‧‧fan-in semiconductor package
2242‧‧‧Wiring pattern
2243h‧‧‧Interlayer window
2280‧‧‧ underfill resin
2290‧‧‧Molding material
2301, 2302‧‧‧board
C‧‧‧ Centerline
d‧‧‧ spaced apart
I-I'‧‧‧ line
S ₁ , S ₂ ‧‧‧ area
W‧‧‧Width

The above and other aspects, features, and advantages of the present invention will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a schematic block diagram illustrating an example of an electronic device system. FIG. 2 is a schematic perspective view illustrating an example of an electronic device. 3A and 3B are schematic cross-sectional views illustrating states of the fan-in semiconductor package before and after being packaged. FIG. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package. 5 is a schematic cross-sectional view illustrating a situation in which a fan-in semiconductor package is mounted on a board substrate and finally mounted on a main board of an electronic device. FIG. 6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in a board substrate and finally mounted on a main board of an electronic device. FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package. FIG. 8 is a schematic cross-sectional view illustrating a case where a fan-out type semiconductor package is mounted on a main board of an electronic device. FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package. FIG. 10 is a schematic plan view taken along a line II ′ of the fan-out type semiconductor package shown in FIG. 9. FIG. 11 is a graph schematically illustrating the change in stress depending on the position where the interlayer window of the second interconnection member of the fan-out semiconductor package shown in FIG. 9 covers the protective layer of the semiconductor wafer; FIG. 12 is a diagram illustrating fan-out A schematic cross-sectional view of another example of a semiconductor package of the semiconductor type. FIG. 13 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. FIG. 14 is a schematic diagram illustrating a case where corrosion occurs on the connection pad. FIG. 15 is a schematic diagram illustrating corrosion of a connection pad in a state where no voltage is applied. FIG. 16 is a schematic diagram illustrating corrosion of a connection pad in a state where a voltage is applied.

2100‧‧‧fan-out semiconductor package

2120‧‧‧Semiconductor wafer

2122‧‧‧Connecting pad

2130‧‧‧ Capsule

2140‧‧‧interconnect

2141‧‧‧Insulation

2142‧‧‧ Redistribution Layer

2143‧‧‧Interlayer window

2150‧‧‧protective layer

2160‧‧‧Under bump metal layer

2170‧‧‧solder ball

Claims (17)

A fan-out type semiconductor package includes: a first interconnection member having a through hole; a semiconductor wafer disposed in the through hole of the first interconnection member, and the semiconductor wafer having an active surface and the semiconductor wafer An active surface opposite to a passive surface with a connection pad disposed on the active surface; an encapsulation body encapsulating at least some portions of the first interconnecting member and at least some portions of the passive surface of the semiconductor wafer And a second interconnecting member disposed on the first interconnecting member and on the active surface of the semiconductor wafer, wherein the first interconnecting member and the second interconnecting member each include rewiring Layer, the redistribution layer is electrically connected to the connection pad; the semiconductor wafer includes a protection layer having an opening exposing at least a portion of the connection pad, and a portion of the second interconnection member The redistribution layer is connected to the connection pad via a via, and the via is located on at least a portion of the protective layer. The fan-out type semiconductor package according to item 1 of the scope of patent application, wherein S ₂ / S _{1 is} in the range of 0.2 to 0.8, wherein S ₁ is the contact of the protective layer and the interlayer window while surrounding the protective layer. The entire area of the surface of the opening, and S ₂ is an area of the interlayer window covering the protective layer. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein d / W is less than 0.3 or equal to 0.3, wherein W is a surface of the contact layer of the protective layer while surrounding the opening of the protective layer And d is the edge of the interlayer window contacting the protective layer and the contact of the protective layer with the interlayer window surrounding the centerline of the surface of the opening of the protective layer distance. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the via window covers the entire exposed surface of the connection pad. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the via window is a filled via window. The fan-out type semiconductor package according to item 1 of the patent application scope, wherein the first interconnection member includes a first insulation layer, a first redistribution layer, and a second redistribution layer, and the first redistribution layer and The second interconnection member is in contact with and embedded in the first surface of the first insulation layer, and the second redistribution layer is disposed on the first insulation layer and the first insulation layer. On a second surface opposite to one surface, the first redistribution layer and the second redistribution layer are electrically connected to the connection pad. The fan-out type semiconductor package according to item 6 of the patent application scope, wherein the first interconnection member further includes a second insulation layer and a third redistribution layer, and the second insulation layer is disposed on the first insulation layer. Layer, and covers the second redistribution layer, the third redistribution layer is disposed on the second insulating layer, and the third redistribution layer is electrically connected to the connection pad. The fan-out type semiconductor package according to item 6 of the patent application scope, wherein a distance between the redistribution layer and the first redistribution layer of the second interconnection member is greater than the second interconnection member The distance between the redistribution layer and the connection pad. The fan-out type semiconductor package according to item 6 of the patent application scope, wherein the first redistribution layer has a thickness larger than a thickness of the redistribution layer of the second interconnection member. The fan-out type semiconductor package according to item 6 of the scope of patent application, wherein a lower surface of the first redistribution layer is disposed at a level higher than a lower surface of the connection pad. The fan-out type semiconductor package according to item 7 of the scope of patent application, wherein the second redistribution layer is disposed on a horizontal level between the active surface and the passive surface of the semiconductor wafer. The fan-out type semiconductor package according to item 1 of the scope of patent application, wherein the first interconnection member includes a first insulating layer, and first redistribution layers disposed on both surfaces of the first insulating layer, respectively. And a second redistribution layer, a second insulation layer disposed on the first insulation layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulation layer, and The first redistribution layer to the third redistribution layer are electrically connected to the connection pad. The fan-out type semiconductor package according to item 12 of the scope of patent application, wherein the first interconnecting member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer, and A fourth redistribution layer disposed on the third insulating layer, and the fourth redistribution layer is electrically connected to the connection pad. According to the fan-out type semiconductor package according to item 12 of the application scope, wherein the first insulating layer has a thickness larger than that of the second insulating layer. The fan-out type semiconductor package according to item 12 of the scope of patent application, wherein the third redistribution layer has a thickness larger than a thickness of the redistribution layer of the second interconnection member. The fan-out type semiconductor package according to item 12 of the application, wherein the first redistribution layer is disposed on a horizontal level between the active surface and the passive surface of the semiconductor wafer. According to the fan-out type semiconductor package according to item 12 of the application scope, wherein a lower surface of the third redistribution layer is disposed at a level lower than a lower surface of the connection pad.