TW201810388A - Low temperature epitaxy method and equipment - Google Patents

Abstract

The present invention provides a low temperature epitaxy method and equipment. The method comprises the steps of: S1: providing a substrate with a semiconductor fin; S2: growing an epitaxy layer on the sidewalls and top surface of the semiconductor fin; S3: etching the epitaxy layer by ultraviolet light source for cracking a source gas to trim the thickness of the epitaxy layer. The low temperature epitaxy method of the present invention uses etching to trim the thickness of the epitaxy layer in the deposition process can improve the epitaxy layer surface profile on the semiconductor fin in order to eliminate the chance of neighbor epitaxy layers touching each other and reduce the gap between epitaxy layers. It achieved by using UV irradiation to activate etchant gas can increase etching rate of the epitaxy layer as well as lower the etching temperature, that can increase the working window and lower the complexity of the manufacturing process.

Description

Low-temperature epitaxial method and device

The present invention relates to semiconductor manufacturing technology, and in particular, to a low-temperature epitaxial method and device.

As the size of integrated circuits is getting smaller and smaller, and the requirements for integrated circuits are gradually increasing, transistors need to have higher driving currents as the size becomes smaller, so fin-type field effect transistors have been developed ( Fin field-effect transistors; FinFETs).

Similar to a planar transistor, a source and drain silicide can be formed on the source and drain regions of a fin-type field effect transistor. However, since the fins of a fin-type field effect transistor are usually narrow, a current crowding phenomenon occurs. In addition, it is difficult to place contact plugs on the source / drain of the fin, so an epitaxial semiconductor layer is formed on the fin using an epitaxial process to increase the volume of the fin.

However, the epitaxial process has some disadvantages. FIG. 1 shows a cross-sectional view of a semiconductor structure including a source / drain region (which is part of the original fin 2), and an epitaxial layer 4 epitaxially grown on the source / drain region. Compared with conventional planar elements, the volume of source / drain region 2 is not limited by shallow trench isolation (STI) 6 because the growth rate of epitaxial layer 4 on the (111) crystal plane is less than Other crystalline surfaces, so the outer surface of the epitaxial layer 4 will have a rectangular (or approximately rectangular) contour, which is similar to the contour of the original fin 2. In addition, the epitaxial layer 4 extends laterally, A plurality of faces 8 are formed, which will cause the distance between the epitaxial layers grown on the adjacent fins to be excessively reduced, and therefore, the merging window thereof will be reduced. Within the scope of the fusion window, epitaxial layers grown on adjacent fins will not fuse. Furthermore, even if the adjacent epitaxial layer 4 belongs to the same source / drain region of a multi-fin FinFET, the epitaxial layer 4 grown on the adjacent fin 2 Blending also causes undesired voids 10, as shown in Figure 2.

US patent US2011 / 0210404A1 discloses that the above-mentioned problem is solved by a deposition-etching process. First, an epitaxial layer is epitaxially grown on the upper surface and sidewalls of a semiconductor fin, and then an epitaxial layer is removed by an etching step to improve the epitaxial layer Layer surface contour. As shown in FIG. 3, a cross-sectional view of the semiconductor structure shown in the patent after the deposition-etching-redeposition step is shown. The substrate 20 is provided with two shallow trench isolation regions 22, and the fins 24 are horizontally interposed. The epitaxial layer 36 on the surface of the fin 24 is between the two shallow trench isolation areas 22 and is located above the two shallow trench isolation areas 22. The epitaxial layer 36_1 formed by the first deposition and etching process and the redeposition The epitaxial layer 36_2 is superimposed. The dotted line in the figure is the interface of the two epitaxial layers 36_1 and 36_2. The thickness T of the increased portion of the epitaxial layer after redeposition is also shown in FIG. In this patent, if the epitaxial layer is fused after at least one deposition-etching loop, the voids generated by the fusion of the epitaxial layer will be reduced and may be eliminated. However, in this method, it is difficult to optimize the control of the process conditions during the deposition-etch process, because the epitaxial deposition, etching, and redeposition processes are sequentially performed in the same cavity in-situ, each stage Process temperature, process pressure and carrier gas flow are all the same. And in this method, the process temperature required to etch the epitaxial layer is relatively high (above 750 ° C). For some materials that require low-temperature epitaxy (such as germanium-silicon materials that are epitaxial at about 650 ° C), this process temperature will affect the epitaxy. Layers adversely affect device performance.

Therefore, how to provide a low-temperature epitaxial method and device to achieve the etching of the epitaxial layer on the surface of the semiconductor fin at a lower process temperature, improve the surface profile of the epitaxial layer, avoid the fusion of the epitaxial layer, or reduce The gap generated after the fusion has become an important technical problem to be solved urgently by those skilled in the art.

In view of the shortcomings of the prior art described above, an object of the present invention is to provide a low-temperature epitaxial method and device for solving the problem that the epitaxial layer on the surface of adjacent semiconductor fins is easy to fuse and there is a large fusion gap in the prior art. .

In order to achieve the above and other related objectives, the present invention provides a low-temperature epitaxial method. The low-temperature epitaxial method includes the following steps: S1: Provide a substrate, the substrate including a substrate and at least one semiconductor protruding from a surface of the substrate. Fins; S2: epitaxial layers are grown on the sidewalls and upper surfaces of the semiconductor fins; S3: the epitaxial layer is etched with an etching gas that is cracked by ultraviolet light irradiation to thin the epitaxial layers The thickness of the crystal layer.

Optionally, the steps S2-S3 are repeated at least once.

Optionally, a source or a drain of the fin-type field effect transistor is fabricated based on the sidewall and the epitaxial layer on the upper surface of the semiconductor fin.

Optionally, the epitaxial layer growth is continued on the surface of the epitaxial layer after the thinning.

Optionally, a source or a drain of the fin-type field effect transistor is fabricated based on the sidewall and the epitaxial layer on the upper surface of the semiconductor fin.

Optionally, steps S2 and S3 are completed in the same reaction chamber.

Optionally, in the step S3, the etching gas includes at least one of Cl ₂ , HCl, and HF in a non-cracked state.

Optionally, in the step S3, the selected temperature range is 650-750 ° C.

Optionally, in the step S3, the etching gas is mixed with a carrier gas, and the carrier gas includes at least one of H ₂ , N ₂ , He, and Ar.

Optionally, the epitaxial layer is made of Si or SiGe.

Optionally, a material of the semiconductor fin is monocrystalline silicon or silicon germanium.

Optionally, in the step S3, the thinned epitaxial layer has an arc-shaped surface profile.

The invention also provides a low-temperature epitaxial device. The low-temperature epitaxial device includes a reaction chamber, an etching gas input end connected to the reaction chamber, and an ultraviolet light source provided outside the reaction chamber. The gas is irradiated to crack it, so that the epitaxial layer on the sidewall and the upper surface of the semiconductor fin is thinned.

Optionally, the ultraviolet light source includes an ultraviolet light cracking unit disposed between the etching gas supply pipe and the etching gas input end, and is used to input the etching gas into the reaction chamber through the etching gas input end. The etching gas is cracked.

Optionally, the ultraviolet light cracking unit includes a cracking chamber and a UV light unit provided outside the cracking chamber; the etching gas supplied by the etching gas supply pipeline passes through the cracking chamber and is then input through the etching gas. End input into the reaction chamber.

Optionally, the cracking cavity is made of a material that can transmit ultraviolet light.

Optionally, the low-temperature epitaxial device uses an infrared light unit as a heating device.

Optionally, an ultraviolet light unit and an infrared light unit are simultaneously provided above the reaction chamber. An infrared light unit is arranged below the reaction chamber.

Optionally, the reaction chamber is made of a material that can transmit ultraviolet light and infrared light.

Optionally, the low-temperature epitaxial device further includes a process gas input end connected to the reaction chamber for inputting an epitaxial reaction source gas, a doping gas, or a carrier gas.

Optionally, a support substrate is provided in the reaction chamber for supporting a substrate to be epitaxially formed; the substrate includes a substrate and at least one semiconductor fin protruding from a surface of the substrate.

Optionally, the epitaxial layer is made of Si or SiGe.

Optionally, the etching gas includes at least one of Cl ₂ , HCl, and HF in a non-cracked state.

Optionally, a temperature range selected by the low-temperature epitaxial device when the epitaxial layer is thinned by an etching gas is 650-750 ° C.

As described above, the low-temperature epitaxial method and device of the present invention have the following beneficial effects:

First, the invention uses ultraviolet light to crack the etching gas, which can increase the etching rate of the epitaxial layer by the etching gas, and reduce the process temperature when etching the epitaxial layer;

Second, the present invention can expand the process window and reduce the difficulty of the process; the etching gas can be any of Cl ₂ , HCl and HF, or any combination thereof;

Third, the invention reduces the thickness of the epitaxial layer by etching during the epitaxial growth process, which can improve the surface profile of the epitaxial layer on the surface of the semiconductor fins, avoid fusion between the epitaxial layers on the surfaces of adjacent semiconductor fins, or reduce Voids produced by the fusion of the small epitaxial layer;

Fourth, the curved surface profile epitaxial layer formed on the semiconductor fin according to the present invention may In order to expand the volume of fins, meet the production needs of source and drain of advanced logic components;

Fifth, the process and device of the present invention are simple and have broad application prospects in the field of semiconductor manufacturing.

2, 24‧‧‧ fins

4, 36, 36_1, 36_2‧‧‧ epitaxial layer

6, 22‧‧‧ shallow trench isolation area

8‧‧‧ noodles

10‧‧‧Gap

20‧‧‧ substrate

T‧‧‧thickness of epitaxial layer

101‧‧‧ substrate

102‧‧‧Shallow trench isolation structure

103‧‧‧Semiconductor Fins

104, 105‧‧‧Epitaxial layer

106‧‧‧ reaction chamber

107‧‧‧Etching gas input

108‧‧‧Etching gas supply line

109‧‧‧lysis chamber

110, 112‧‧‧ UV light unit

111‧‧‧ infrared light unit

113‧‧‧process gas input

114‧‧‧Support substrate

115‧‧‧ substrate

116‧‧‧ tail gas output

FIG. 1 is a cross-sectional view of a semiconductor structure in the prior art.

FIG. 2 is a schematic diagram showing the generation of undesired voids caused by the fusion of epitaxial layers grown on adjacent fins in the prior art.

FIG. 3 is a cross-sectional view of a semiconductor structure presented through a deposition-etch-redeposition step in the prior art.

FIG. 4 is a process flow chart of the low-temperature epitaxial method of the present invention.

5 to 10 are cross-sectional views showing the structure of each step of the low-temperature epitaxial method of the present invention.

FIG. 11 is a schematic structural view of a low-temperature epitaxial device according to the present invention.

The following describes the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementations, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 4 to 11. It should be noted that the illustrations provided in this embodiment only illustrate the basic idea of the present invention in a schematic manner, and the drawings only show the same as in the present invention. Relevant components are not drawn according to the number, shape, and size of the components during actual implementation. The type, quantity, and proportion of each component during actual implementation may be changed at will, and the component layout may be more complicated.

Example one

The present invention provides a low-temperature epitaxial method. Please refer to FIG. 4, which shows a process flow chart of the method, including the following steps: S1: Provide a substrate, the substrate including a substrate and at least one semiconductor protruding from a surface of the substrate Fins; S2: epitaxial layers are grown on the sidewalls and upper surfaces of the semiconductor fins; S3: the epitaxial layer is etched with an etching gas that is cracked by ultraviolet light irradiation to thin the epitaxial layers The thickness of the crystal layer.

First, referring to FIG. 5, step S1 is performed: a substrate is provided. The substrate includes a substrate 101 and at least one semiconductor fin 103 protruding from a surface of the substrate 101.

Specifically, the substrate 101 includes, but is not limited to, conventional semiconductor substrates such as silicon, germanium, and silicon germanium. The substrate 101 may be P-type doped or N-type doped.

In this embodiment, a shallow trench isolation structure 102 is also formed in the substrate 101. The shallow trench isolation structure 102 can be obtained by forming a plurality of spaced-apart trenches in the substrate 101 and filling an insulating dielectric layer in the trenches. The insulating dielectric layer includes, but is not limited to, a silicon dioxide material.

The semiconductor fin 103 is interposed between two shallow trench isolation structures 102 in a horizontal direction, and is located above the shallow trench isolation structures 102.

In one embodiment, the semiconductor fin 103 may be made of the same material as the substrate 101. For example, the semiconductor fin 103 and the substrate 101 are made of single crystal silicon or silicon germanium. In this case, the semiconductor fin 103 may be obtained by removing a top portion of the shallow trench isolation structure 102. Of course, the semiconductor fin 103 can also be obtained by epitaxy.

In another embodiment, the material of the semiconductor fin 103 and the substrate 101 may be different materials. For example, the substrate 101 is selected from one of a silicon substrate and a germanium substrate, and the semiconductor fin 103 is made of a silicon germanium material; or the substrate 101 is selected from one of a silicon germanium substrate and a germanium substrate, and the semiconductor The fin 103 is made of a single crystal silicon material.

Referring to FIG. 6, step S2 is performed: an epitaxial layer 104 is epitaxially grown on a sidewall and an upper surface of the semiconductor fin 103.

Specifically, the material of the epitaxial layer 104 may be the same as or different from the semiconductor fin 103. As an example, the material of the epitaxial layer 104 is Si or SiGe. The composition of Ge in SiGe can be adjusted according to actual needs.

The epitaxial layer 104 can be obtained by a vapor phase epitaxy process. Specifically, the substrate is placed in a reaction chamber, the substrate is heated to a preset temperature, and an epitaxial reaction source gas is passed into the reaction chamber to epitaxially epitaxially be exposed on the semiconductor fin 103. The epitaxial layer 104 is grown.

As an example, the temperature range selected for epitaxial growth of Si epitaxial layer is 750 ° C-850 ° C, and the temperature range selected for epitaxial growth of SiGe epitaxial layer is 650 ° C-800 ° C. In this embodiment, the SiGe epitaxial layer is preferably epitaxially grown at a temperature of 690 ° C.

As an example, the silicon source in the reaction source gas is selected from the group consisting of silicon dichlorohydrogen (SiH ₂ Cl ₂ ), silicon trichlorohydrogen (SiHCl ₃ ), silicon tetrachloride (SiCl ₄ ), and silane (SiH ₄ ). One or more kinds; the germanium source in the reaction source is germane (GeH ₄ ). In forming the SiGe epitaxial layer, a SiGe epitaxial layer with a specific Ge composition can be realized by adjusting the flow rate of the germanium source.

During epitaxial growth, a carrier gas can be introduced at the same time. As an example, the carrier gas includes one or a combination of two or more of H ₂ , N ₂ , He, and Ar. In this embodiment, the carrier gas is selected as H ₂ .

During epitaxial growth, doping is often required to ensure controlled resistivity. The dopant used in the N-type epitaxial layer is generally phosphine (PH ₃ ) \ phosphorus trichloride (PCl ₃ ) or arsenic (AsH ₃ ); the dopant used in the P-type epitaxial layer is generally diboron Alkane (B ₂ H ₆ ) or boron trichloride (BCl ₃ ) and the like. Therefore, during the epitaxial growth process, a dopant gas may be simultaneously introduced to achieve more epitaxial functions. The dopant gas may include one or more of an N-type dopant gas and a P-type dopant gas.

In addition, during the epitaxial process, a selective gas, such as HCl gas, may be introduced at the same time, so that the epitaxial layer 104 selectively grows on the surface of the semiconductor fin 103, but does not grow on the shallow trench isolation structure 102.

As shown in FIG. 6, since the epitaxial layer has different growth rates on different surface crystal directions, multiple faces may be formed. As the epitaxial growth progresses, sharp angles will gradually be formed between the multiple surfaces of the epitaxial layer, so that the lateral width of the epitaxial layer increases, and the volume of the epitaxial layer is not sufficient.

Referring to FIG. 7 again, step S3 is performed: the epitaxial layer 104 is etched with an etching gas that is decomposed by ultraviolet light irradiation to reduce the thickness of the epitaxial layer 104.

As an example, the etching gas includes at least one of Cl ₂ , HCl, and HF in a non-cracked state. Among them, the maximum light absorption wavelength (Optical Absorption Wave Length) of Cl ₂ is 332nm (at this wavelength, the absorbance value reaches the maximum), the maximum light absorption wavelength of HCl is 154nm, the maximum light absorption wavelength of HF is 332nm, both in the ultraviolet Spectrum (10 ~ 380nm).

In this step, the etching gas is irradiated with ultraviolet light, and the etching gas can be cracked (or decomposed) to fully activate the etching gas, which has stronger etching ability and can achieve low-temperature etching. For example, under the action of ultraviolet light, chlorine gas molecules absorb energy to break the covalent bond and dissociate into two activated chlorine atoms. The radius of activated chlorine atoms is small, and the ability to capture or attract electrons is strong. It is very lively and at a lower temperature. The epitaxial layer can be etched.

As an example, the temperature range selected for etching in this step is 650-750 ° C, such as 660 ° C, 670 ° C, 680 ° C, 690 ° C, 695 ° C, 700 ° C, 710 ° C, 720 ° C, 730 ° C, 740 ° C, and the like.

This step and the step S2 may be completed in the same reaction chamber, and the etching gas may be mixed with a carrier gas. As an example, the carrier gas includes at least one of H ₂ , N ₂ , He, and Ar.

As shown in FIG. 7, the outline of the epitaxial layer 104 before thinning is shown by a dashed line. After the etching in this step, the thinned epitaxial layer 104 has an arc-shaped surface profile, which reduces adjacent semiconductors. The fusion probability of the epitaxial layer on the fin 103.

The epitaxial layer 105 and the epitaxial layer 104 may be made of the same material or different materials. The boundary between the epitaxial layer 105 and the epitaxial layer 104 in FIG. 10 is indicated by a dotted line, which means that this interface may not be visible.

In another embodiment, the steps S2-S3 can be repeated at least once to increase the volume of the epitaxial layer. FIG. 8 shows that the method of step S2 is further used in the epitaxy. A schematic diagram of the epitaxial layer 105 growing on the surface of the layer 104 is shown in FIG. 9. FIG. 9 is a schematic diagram of further thinning the epitaxial layer 105 by using the method of step S3.

In another embodiment, the epitaxial layer can be grown on the surface of the thinned epitaxial layer without further thinning, because the previous etching step reduces the probability of further epitaxial fusion. Alternatively, after repeating the steps S2-S3 at least once, the epitaxial layer growth is continued on the surface of the epitaxial layer after the thinning, without further thinning.

The low-temperature epitaxial method of the present invention reduces the epitaxial layer by etching during the epitaxial growth process, which can improve the surface profile of the epitaxial layer on the surface of the semiconductor fin and avoid fusion between the epitaxial layers on the surface of the adjacent semiconductor fin. Or reduce the void generated after the epitaxial layer is fused. The method of irradiating the etching gas with ultraviolet light can increase the etching rate of the epitaxial layer by the etching gas, and reduce the process temperature when etching the epitaxial layer, thereby expanding the process window and reducing the difficulty of the process. As the epitaxial layer with an arc-shaped surface profile formed on the semiconductor fin expands the volume of the fin, it can meet the manufacturing requirements of the source or drain of an advanced logic element (such as a fin-type field effect transistor).

Example two

The invention also provides a low-temperature epitaxial device. Please refer to FIG. 11, which is a schematic structural diagram of the device, including a reaction chamber 106, an etching gas input end 107 connected to the reaction chamber 106, and a reaction chamber 106. An external ultraviolet light source; the ultraviolet light source is irradiated by an etching gas to cause cracking, so that the epitaxial layer on the side wall and the upper surface of the semiconductor fin is thinned.

As an example, the ultraviolet light source includes an ultraviolet light cracking unit disposed between the etching gas supply pipe 108 and the etching gas input terminal 107, and is configured to input the etching gas into the reaction through the etching gas input terminal 107. The chamber 106 is previously cracked by the etching gas.

As an example, the ultraviolet light cracking unit includes a cracking chamber 109 and an ultraviolet light unit 110 provided outside the cracking chamber 109; the etching gas supplied by the etching gas supply pipe 108 passes through the cracking chamber 109 and then passes through the cracking chamber 109. The etching gas input terminal 107 is input into the reaction chamber 106.

As an example, the ultraviolet light unit 110 is an ultraviolet light, and the cracking cavity 109 is a material that can transmit ultraviolet light, such as quartz glass.

As an example, an ultraviolet light unit 112 may be further disposed above the reaction chamber 106, which is used for further cracking a part of the etching gas that has not been cracked to further improve the utilization rate of the etching gas.

As an example, the etching gas includes at least one of Cl ₂ , HCl, and HF in a non-cracked state. Under the irradiation of ultraviolet light, the etching gas is cracked (or decomposed) into atoms, so that the etching gas is fully activated, which has stronger etching ability and can achieve low-temperature etching. For example, under the action of ultraviolet light, chlorine gas molecules absorb energy to break the covalent bond and dissociate into two activated chlorine atoms. The radius of activated chlorine atoms is small, and the ability to capture or attract electrons is strong. It is very lively and at a lower temperature. The epitaxial layer can be etched. As an example, a temperature range selected by the low-temperature epitaxial device when the epitaxial layer is thinned by an etching gas is 650-750 ° C.

As shown in FIG. 11, the low-temperature epitaxial device uses an infrared light unit 111 as a heating device. The infrared light unit 111 may specifically be an infrared light. As an example, the infrared light units 111 are disposed above and below the reaction chamber 106, and the infrared light units 111 and the ultraviolet light units 112 are alternately arranged above the reaction chamber 106. In addition, the infrared light 111 is evenly distributed above and below the reaction chamber 106, and the ultraviolet light unit 112 is evenly distributed above the reaction chamber 106. Such a uniform arrangement can improve the uniformity of the heating temperature and the epitaxy. crystal Body quality and uniformity of epitaxial layer etching. As an example, the material of the epitaxial layer is Si or SiGe.

Since the ultraviolet light unit 112 and the infrared light unit 111 are both disposed outside the reaction chamber, the reaction chamber is preferably made of a material that can transmit ultraviolet light and infrared light.

Of course, the setting positions of the ultraviolet light unit and the infrared light unit can be changed according to requirements, and are not limited to the examples listed here.

As shown in FIG. 11, the low-temperature epitaxial device further includes a process gas input terminal 113 connected to the reaction chamber 106 for inputting an epitaxial reaction source gas, a doping gas, or a carrier gas, etc. to realize an epitaxial layer. Epitaxial growth.

It should be noted that for the convenience of illustration, only one process gas input terminal 113 is shown in FIG. 11. However, in actual use, the number of the process gas input terminals 113 can be adjusted according to needs, for example, 2 Root, 3 roots or more, and the protection scope of the present invention should not be excessively limited here.

A support substrate 114 is also provided in the reaction chamber 106 for supporting a substrate 115 that needs to be epitaxially formed. The substrate 115 includes a substrate and at least one semiconductor fin protruding from a surface of the substrate. As an example, the supporting substrate 114 is a graphite substrate covered by SiC.

The low-temperature epitaxial device of the present invention can realize the growth of the epitaxial layer and the low-temperature etching of the epitaxial layer, improve the surface profile of the epitaxial layer on the surface of the semiconductor fin, and meet the manufacturing requirements of the source and drain of the advanced logic element.

In summary, the low-temperature epitaxial method and device of the present invention have the following beneficial effects: First, the present invention uses an ultraviolet light irradiation method to crack the etching gas, which can increase the etching rate of the epitaxial layer by the etching gas, and Reduce the process temperature when etching the epitaxial layer; Second, the present invention can expand the process window and reduce the difficulty of the process; the etching gas can be any one of Cl ₂ , HCl and HF, or any combination thereof; third, this By etching the epitaxial layer, the invention can improve the surface profile of the epitaxial layer on the surface of the semiconductor fin, avoid fusion between the epitaxial layers on the surface of adjacent semiconductor fins, or reduce the gap generated after the epitaxial layer is fused; The arc-shaped surface epitaxial layer formed on the semiconductor fin according to the present invention can expand the volume of the fin and meet the manufacturing requirements of the source and drain of the advanced logic element. Fifth, the process and device of the present invention are simple and widely used in the field of semiconductor manufacturing. Application prospects.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-mentioned embodiments merely illustrate the principle of the present invention and its effects, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field to which they belong without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Steps S1 ~ S3‧‧‧‧

Claims (24)

A low-temperature epitaxial method, characterized in that the low-temperature epitaxial method includes the following steps: S1: providing a substrate, the substrate including a substrate and at least one semiconductor fin protruding from the surface of the substrate; S2: in the The epitaxial layer is epitaxially grown on the side wall and the upper surface of the semiconductor fin; S3: the epitaxial layer is etched with an etching gas that is cracked by ultraviolet light irradiation to reduce the thickness of the epitaxial layer. The low-temperature epitaxial method according to claim 1, wherein the steps S2-S3 are repeated at least once. The low-temperature epitaxial method according to claim 1 or 2, wherein a source or a drain of a fin-type field effect transistor is made based on an epitaxial layer on a sidewall and an upper surface of the semiconductor fin. The low-temperature epitaxial method according to claim 1 or 2, wherein the epitaxial layer is continuously grown on the surface of the epitaxial layer after the thinning. The low-temperature epitaxial method according to claim 4, wherein a source or a drain of a fin-type field effect transistor is fabricated based on an epitaxial layer on a sidewall and an upper surface of the semiconductor fin. The low-temperature epitaxial method according to claim 1, wherein the steps S2 and S3 are completed in a same reaction chamber. The low-temperature epitaxial method according to claim 1, wherein in the step S3, the etching gas includes at least one of Cl ₂ , HCl, and HF in an uncracked state. The low-temperature epitaxial method according to claim 1, wherein in the step S3, a selected temperature range is 650-750 ° C. Low Wen Leijing method of claim 1, wherein in said step S3, the etching gas mixed with carrier gas, the carrier gas comprises H _2, N _2, at least one of Ar and He. The low-temperature epitaxial method according to claim 1, wherein a material of the epitaxial layer is Si or SiGe. The low-temperature epitaxial method according to claim 1, wherein a material of the semiconductor fin is monocrystalline silicon or silicon germanium. The low-temperature epitaxial method according to claim 1, wherein in the step S3, the thinned epitaxial layer has an arc-shaped surface profile. A low-temperature epitaxial device, characterized in that the low-temperature epitaxial device includes a reaction chamber, an etching gas input end connected to the reaction chamber, and an ultraviolet light source provided outside the reaction chamber; The gas is irradiated to crack it, so that the epitaxial layer on the sidewall and the upper surface of the semiconductor fin is thinned. The low-temperature epitaxial device according to claim 13, wherein the ultraviolet light source comprises an ultraviolet light cracking unit provided between an etching gas supply pipe and the etching gas input end, and is configured to pass an etching gas through the etching gas. Before the input end is input into the reaction chamber, the etching gas is cracked. The low-temperature epitaxial device according to claim 14, wherein the ultraviolet light cracking unit pack It includes a cracking chamber and an ultraviolet light unit provided outside the cracking chamber; the etching gas supplied by the etching gas supply pipeline passes through the cracking chamber and is then input into the reaction chamber through the etching gas input end. The low-temperature epitaxial device according to claim 15, wherein the cracking cavity is made of a material that can transmit ultraviolet light. The low-temperature epitaxial device according to claim 13, wherein the low-temperature epitaxial device uses an infrared light unit as a heating device. The low-temperature epitaxial device according to claim 13, wherein an ultraviolet light unit and an infrared light unit are simultaneously provided above the reaction chamber; and an infrared light unit is provided below the reaction chamber. The low-temperature epitaxial device according to claim 13, wherein the reaction chamber is made of a material that can transmit ultraviolet light and infrared light. The low-temperature epitaxial device according to claim 13, wherein the low-temperature epitaxial device further comprises a process gas input terminal connected to the reaction chamber for inputting an epitaxial reaction source gas, a doping gas, or a carrier gas. The low-temperature epitaxial device according to claim 13, wherein a support substrate is provided in the reaction chamber for supporting a substrate to be epitaxially formed; the substrate comprises a substrate and at least one semiconductor protruding from a surface of the substrate Fins. The low-temperature epitaxial device according to claim 13, wherein a material of the epitaxial layer is Si or SiGe. The low-temperature epitaxial device according to claim 13, wherein the etching gas includes at least one of Cl ₂ , HCl, and HF in a state where it is not cracked. The low-temperature epitaxial device according to claim 13, wherein a temperature range selected by the low-temperature epitaxial device when the epitaxial layer is thinned by an etching gas is 650-750 ° C.