CN103151294A

CN103151294A - Device isolation structure and manufacturing method thereof

Info

Publication number: CN103151294A
Application number: CN2011104028021A
Authority: CN
Inventors: 高杏; 刘继全; 罗啸
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-12-07
Filing date: 2011-12-07
Publication date: 2013-06-12

Abstract

The invention discloses a device isolation structure and a manufacturing method of the device isolation structure. The device isolation structure comprises a silicon substrate, first isolation layers and active areas, wherein the first isolation layers and the active areas are located on the silicon substrate, the active areas are formed by mono-crystal silicon growing on an injected second isolation layer, the first isolation layers and the active area are arranged at intervals, the first isolation layers are formed by a dielectric layer deposited on the silicon substrate, and active area windows can be formed, and the second isolation layer is formed by injection of active area inversion impurities into the active area windows. The manufacturing method includes: (1) completing deposition of the first isolation layers on the silicon substrate; (2) carrying out etching on the first isolation layers to form active area windows; (3) injecting inversion ions of a metal oxide semiconductor (MOS) Well area into the active area windows, carrying out annealing and repairing and forming the second isolation layer; and (4) using selective epitaxy for generating the mono-crystal silicon in the active area windows. The device isolation structure and the manufacturing method of the device isolation structure can achieve the full-isolation structure similar to silicon on insulator (SOI) with lower cost.

Description

Device isolation structure and manufacture method thereof

Technical field

The present invention relates to isolation structure and manufacture method thereof in a kind of semiconductor integrated circuit, particularly relate to a kind of novel device isolation structure and manufacture method thereof.

Background technology

In the modem semi-conductor devices manufacturing process, along with the continuous lifting that device performance is required, in order to realize more low-power, MOS (the Metal-Oxide-Semiconductor of higher switching rate, Metal-oxide-semicondutor) structure, SOI (Silicon-on-insulator, the silicon on dielectric substrate) has inevitably captured high-end small size CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) manufacturing market.

The SOI technology is to have introduced one deck between at the bottom of top layer silicon and backing to bury oxide layer.By forming semiconductive thin film on insulator, the SOI material had advantages of body silicon incomparable: can realize the medium isolation of components and parts in integrated circuit, thoroughly eliminate the parasitic latch-up in the Bulk CMOS circuit; Adopt integrated circuit that this material is made to have also that parasitic capacitance is little, integration density is high, speed is fast, technique is simple, short-channel effect is little and be specially adapted to the advantages such as low voltage and low power circuits.Wherein, the detailed process of SOI technology processing procedure is as follows:

The SOI substrate sheet is made needs two silicon single crystal substrate A, B, as Fig. 1 (1.); And the certain thickness SiO that grows on the A substrate ₂, as Fig. 1 (2.); Pass through H ⁺Implantation forms the damage layer at the A substrate, as Fig. 1 (3.); By cleaning bonding technology, A, B substrate are bonded together again, as Fig. 1 (4.); Substrate after adopting subsequently Smart Cut technology with bonding split into two A～, B～, as Fig. 1 (5.); A～, B～substrate again by annealing and the CMP PROCESS FOR TREATMENT, B～substrate namely forms the SOI sheet, as Fig. 1 (6.); And A～form new silicon single crystal substrate by again processing, as Fig. 1 (7.)

The shortcomings such as therefore, SOI technology processing procedure exists preparation complicated, and is with high costs.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of new device isolation structure and manufacture method thereof.This structure realizes isolation effect by selective epitaxial, can reduce technology difficulty and cost.

For solving the problems of the technologies described above, new device isolation structure of the present invention comprises: silicon substrate, be positioned at the first separator and active area on silicon substrate, wherein, active area is formed by the monocrystalline silicon of growing on the second separator that injects, and the first separator and active area are spaced.

Described the first separator is formed by dielectric layer deposit on silicon substrate, and its thickness can be between 0.1um-10um, and can leave silicon window (being the active area window) by techniques such as chemical wet etchings; The second separator is injected with source region transoid impurity and forms in the silicon window by injection technology.Form in the silicon window by selective epitaxial process and meet the device related request, as the silicon epitaxy of thickness, resistivity, width of transition zone, so far form both sides and isolated by dielectric layer, the full isolation structure that the bottom is formed by the transoid depletion layer.

Described the first separator is dielectric layer SiO ₂Film, thickness are 0.1～10 μ m.

Described the second separator, the ion of its injection are and the ion of MOS Well district (P Well or N Well) transoid that its implantation dosage is 1 * 10 ¹³～5 * 10 ¹⁷/ cm ²Wherein, the ion that P well injects in the district comprises: As, P, Sb; The ion that N well district is injected comprises: B, In, BF ₂

The thickness of described monocrystalline silicon is 0.1～10 μ m.

In addition, the invention also discloses a kind of manufacture method of new device isolation structure, comprise step:

(1) complete on the silicon substrate deposit of the first separator;

(2) carry out etching on the first separator, silicon substrate is appeared, be formed with the source region window;

(3) inject ion with MOS Well district transoid at the active area window, and annealing repairs, form the second separator of injection;

(2) utilize selective epitaxial growth, generate monocrystalline silicon in the active area window.

In described step (2), after the first separator etching, the shape of sidewall comprises: right angle, anacline, reverse caster.

In described step (3), Implantation Energy is 10～2Mev, can adopt different-energy, dosage repeatedly to inject; Annealing temperature is 600～1200 ℃, and the time is 10～200min.

The present invention is combined with injection technique by the selective epitaxial technology, utilizes existing technique, at certain interval SiO ₂In thickness range, by photoetching development and etching, form required active area silicon window, inject in window, form the depletion layer with MOS WELL district transoid, and obtain the active area high-quality monocrystalline silicon layer of appointed thickness by selective epitaxial precipitation, with more low-cost, realize the similarly full isolation structure with SOI.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is the traditional SOI structural representation;

Fig. 2 is structural representation of the present invention;

Fig. 3 is the SiO during the present invention makes ₂Schematic diagram after deposit;

Fig. 4 be during the present invention makes SiO ₂Schematic diagram after etching;

Fig. 5 is schematic diagram after injection during the present invention makes;

Fig. 6 is transmission electron microscope in kind (TEM) figure of the full isolation structure that forms of the present invention.

In figure, description of reference numerals is as follows:

11 is that silicon substrate 21 is the first separator SiO ₂Film

22 is that the second separator 23 is monocrystalline silicon

Embodiment

New device isolation structure of the present invention as shown in Figure 2, comprising:

Silicon substrate 11;

Be positioned at the first separator SiO on silicon substrate 11 ₂ Film 21, its thickness are 0.1～10 μ m;

Be positioned at the active area on silicon substrate 11, monocrystalline silicon 23 by growth on the second separator 22 that injects is formed, wherein, and in the second separator 22, the ion of its injection is and the ion of MOS Well district (P Well or N Well) transoid that its implantation dosage is 1 * 10 ¹³～5 * 10 ¹⁷/ cm ²The thickness of monocrystalline silicon 23 is 0.1～10 μ m;

Wherein, the first separator SiO ₂Film 21 and active area are spaced; The first separator SiO ₂Film 21 is by SiO ₂The deposit on silicon substrate 11 of film medium layer forms, and can leave silicon window (being the active area window) by techniques such as chemical wet etchings; The second 22 of separators are injected with source region transoid impurity and form in the silicon window by injection technology; Form in the silicon window by selective epitaxial process and meet the device related request, as the silicon epitaxy of thickness, resistivity, width of transition zone, so far form both sides and isolated by dielectric layer, the full isolation structure that the bottom is formed by the transoid depletion layer.

For above-mentioned be the new device isolation structure, the manufacture method that it is concrete comprises step:

(1) utilize the dielectric layer depositing technics, as boiler tube, LPCVD, PECVD etc., growth the first separator SiO on silicon substrate 11 ₂ Film 21 is completed SiO ₂The deposit of film 21 (as shown in Figure 3), its deposition thickness are 0.1～10 μ m;

(2) utilize photoetching process, silicon chip surface is carried out gluing, exposure etc. form the required process window of device, utilize dry etch process at the first separator SiO ₂ Film 21 surface etch, and be parked in silicon substrate 11 surfaces, form or vertical-channel sidewall and epitaxial growth window parallel with the crystal orientation; Adopt the boiler tube thermal oxidation technology, consume surface silicon damage layer, and eliminate by wet etching the first separator SiO that boiler tube is grown in the process window surface ₂Film 21 appears silicon substrate 11, is formed with source region window (as shown in Figure 4);

Wherein, SiO ₂After etching, sidewall can be right angle, anacline, reverse caster etc.;

(3) the active area window inject with the ion of MOS Well district transoid (as, P Well carries out As, P, the injection of Sb plasma; N Well carries out B, In, BF ₂Plasma injects), its implantation dosage is 1 * 10 ¹³～5 * 10 ¹⁷/ cm ², Implantation Energy is 10～2Mev, can adopt different-energy, dosage repeatedly to inject, and anneals at 600～1200 ℃ and repair 10～200min, forms the second separator 22 (as shown in Figure 5) that injects;

(4) carry out selective epitaxial growth at silicon chip surface, detailed process is: utilize the reaction system contain Si deposit source and to contain halogen family element source of corrosion, carry out selective epitaxial precipitation, wherein, contain Si deposit source, comprise SiCl ₄, SiHCl ₃, SiH ₂Cl ₂, SiH ₄Deng; Contain halogen family element source of corrosion, comprising: the HCL etchant gas, wherein, this gas flow is 0.01～5slm; The temperature of deposit is 450～1250 ℃; Epitaxially grown pressure is that 20～760Torr, epitaxial growth thickness are 0.1～10 μ m; Epitaxial growth can be N-type or P type, and its doping content can be regulated according to requirement on devices; Thereby, generating monocrystalline silicon 23 in the active area window, thickness is 0.1～10 μ m, so far forms the active device region of full isolation; Wherein, the surface of monocrystalline silicon 23 and SiO ₂The film flush; In this step, but except the forming core growing epitaxial monocrystalline silicon layer of Si surface, SiO ₂The film surface is without polycrystalline deposition, as shown in Figure 6.

According to the method described above, by with SiO ₂Film utilizes selective epitaxial to form SiO as area of isolation ₂With active area and the isolated area that Si replaces, can realize the similar full isolation structure with SOI, and the present invention realizes isolation effect by selective epitaxial, not only can reduce technology difficulty, and more reduce costs.

Claims

1. a device isolation structure, is characterized in that, comprising: silicon substrate, be positioned at the first separator and active area on silicon substrate, and wherein, active area is formed by the monocrystalline silicon of growing on the second separator that injects, and the first separator and active area are spaced;

Described the first separator is formed by dielectric layer deposit on silicon substrate, and can be with the source region window; Described the second separator is injected with source region transoid impurity and forms in the active area window by injection technology.

2. structure as claimed in claim 1, it is characterized in that: described the first separator is dielectric layer SiO ₂Film, thickness are 0.1～10 μ m.

3. structure as claimed in claim 1 is characterized in that: described the second separator, the ion of its injection are and the ion of MOS Well district transoid that its implantation dosage is 1 * 10 ¹³～5 * 10 ¹⁷/ cm ²

4. structure as claimed in claim 3 is characterized in that: described MOS Well district is P well district or N well district;

Wherein, the ion that P well injects in the district comprises: As, P, Sb;

The ion that N well district is injected comprises: B, In, BF ₂

5. structure as claimed in claim 1, it is characterized in that: the thickness of described monocrystalline silicon is 0.1～10 μ m.

6. the manufacture method of device isolation structure as claimed in claim 1, is characterized in that, comprises step:

(1) complete on the silicon substrate deposit of the first separator;

(4) utilize selective epitaxial growth, generate monocrystalline silicon in the active area window.

7. method as claimed in claim 6, it is characterized in that: in described step (2), after the first separator etching, the shape of sidewall comprises: right angle, anacline, reverse caster.

8. method as claimed in claim 6, it is characterized in that: in described step (3), Implantation Energy is 10～2Mev.

9. method as claimed in claim 6, it is characterized in that: in described step (3), annealing temperature is 600～1200 ℃, and the time is 10～200min.