CN107516636A - A kind of low-temperature epitaxy method and device - Google Patents
A kind of low-temperature epitaxy method and device Download PDFInfo
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- CN107516636A CN107516636A CN201610435872.XA CN201610435872A CN107516636A CN 107516636 A CN107516636 A CN 107516636A CN 201610435872 A CN201610435872 A CN 201610435872A CN 107516636 A CN107516636 A CN 107516636A
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- 238000000407 epitaxy Methods 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 89
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 53
- 230000008569 process Effects 0.000 claims abstract description 19
- 238000006243 chemical reaction Methods 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 26
- 238000005336 cracking Methods 0.000 claims description 17
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 10
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 4
- 230000003628 erosive effect Effects 0.000 claims description 2
- 230000004927 fusion Effects 0.000 abstract description 16
- 238000005516 engineering process Methods 0.000 abstract description 7
- 239000007789 gas Substances 0.000 description 75
- 238000002955 isolation Methods 0.000 description 9
- 239000000460 chlorine Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052801 chlorine Inorganic materials 0.000 description 4
- 125000001309 chloro group Chemical group Cl* 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010494 dissociation reaction Methods 0.000 description 2
- 230000005593 dissociations Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- FAIAAWCVCHQXDN-UHFFFAOYSA-N phosphorus trichloride Chemical compound ClP(Cl)Cl FAIAAWCVCHQXDN-UHFFFAOYSA-N 0.000 description 2
- 239000005049 silicon tetrachloride Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 125000003963 dichloro group Chemical group Cl* 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of low-temperature epitaxy method and device, and methods described comprises the following steps：S1：A substrate is provided, the substrate includes substrate and protrudes from least one semiconductor fin of the substrate surface；S2：In the side wall and upper surface epitaxial growth epitaxial layer of the semiconductor fin；S3：The epitaxial layer is performed etching using the etching gas cracked by ultraviolet light, so that the thickness of the epitaxial layer is thinned.Epitaxial layer is thinned by etching during epitaxial growth in the low-temperature epitaxy method of the present invention, the surface profile of semiconductor fin surface epitaxial layer can be improved, the fusion between adjacent semiconductor fin surface epitaxial layer is avoided, or reduces caused space after epitaxial layer fusion.Wherein, the mode of ultraviolet light etching gas can improve etch rate of the etching gas to epitaxial layer, and reduce technological temperature when etching epitaxial layer, so as to expand process window, reduce technology difficulty.
Description
Technical field
The invention belongs to field of semiconductor manufacture, is related to a kind of low-temperature epitaxy method and device.
Background technology
It is less and less with the size of integrated circuit, and requirement for integrated circuit gradually increases, transistor needs
There is higher driving current with less and less size, therefore develop fin formula field effect transistor (Fin field-
effect transistors；FinFETs).
It is similar to the transistor of plane, source electrode and drain electrode silicon can be formed on the source electrode of fin field-effect transistor and drain region
Compound.However, because the fin of fin field-effect transistor is generally very narrow, therefore current collection (current can occur
Crowding) phenomenon.In addition, it is highly difficult to be placed into contact with connector on the source/drain of fin, therefore existed using epitaxy technique
Epitaxial semiconductor layer is formed on fin, to increase the volume of fin.
However, epitaxy technique has some shortcomings.Fig. 1 shows the profile of semiconductor structure, and it includes source/drain regions
(it is a part for original fin 2), and epitaxial layer 4 of the epitaxial growth on source/drain regions.With traditional plane component
Compare, the volume of source/drain regions 2 does not completely cut off (the shallow trench isolation of area 6 by shallow trench；STI) office
Limit, because growth rate of the epitaxial layer 4 on (111) crystal plane is less than other crystal planes, therefore the outer surface meeting of epitaxial layer 4
The profile of rectangle (or approximate rectangular) is produced, it is such as the profile of original fin 2.In addition, epitaxial layer 4 can extend transversely with, and
Multiple faces 8 (facet) are formed, this can cause the distance between the epitaxial layer grown on adjacent fin excessive reduction, because
This, it, which merges form (merging window), to reduce.In the scope of fusion form, what is grown on adjacent fin is outer
Prolonging layer will not merge.Furthermore even if adjacent epitaxial layer 4 belongs to same more fin fin field-effect transistor (multi-fin
FinFET source/drain regions), the fusion of the epitaxial layer 4 grown on adjacent fin 2 will also result in undesirable space 10
Produce, as shown in Figure 2.
Patent US2011/0210404A1 is disclosed by deposition-etch technique to solve the above problems, i.e., first half
The upper surface of conductor fin and side wall Epitaxial growth epitaxial layer, then remove a part of epitaxial layer to improve by etching step
Epi-layer surface profile.As shown in figure 3, it is shown as the semiconductor presented in the patent by deposition-etch-redeposited step
The profile of structure, wherein, two shallow trench are provided with substrate 20 and completely cut off areas 22, fin 24 flatly between two shallow trench every
Between exhausted area 22, and completely cut off positioned at two shallow trench on area 22, the epitaxial layer 36 on the surface of fin 24 by depositing and losing for the first time
The epitaxial layer 36_1 that carving technology is formed is formed by stacking with redeposited epitaxial layer 36_2, in figure dotted line be two layers of epitaxial layer 36_1,
36_2 interface, also show in Fig. 3 epitaxial layer after redeposition increased part thickness T.In that patent, by extremely
After few primary depositing-etch cycle, if epitaxial layer merges, it can reduce via space caused by the fusion of epitaxial layer, and
It may be eliminated.But in this method, the optimal control to process conditions during deposition-etch is relatively difficult, because outside
Prolong deposition, etching, redeposited process in same cavity, in situ (in-situ) carry out successively, each stage process temperature,
Process atmospheric pressures and carrier gas flow are consistent.And in this method, it is higher (750 DEG C to etch technological temperature needed for epitaxial layer
More than), the material (such as germanium silicon material of 650 DEG C or so extensions) of low-temperature epitaxy, this technological temperature meeting are needed for some
Harmful effect is produced to epitaxial layer, so as to deteriorate device performance.
Therefore, how a kind of low-temperature epitaxy method and device is provided, is partly led with being realized under the conditions of relatively low technological temperature
The etching of body fin surface epitaxial layer, improve the surface profile of epitaxial layer, avoid the fusion of epitaxial layer, or produced after reducing fusion
Raw space, turn into those skilled in the art's important technological problems urgently to be resolved hurrily.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of low-temperature epitaxy method and dress
Put, easily merged for solving the epitaxial layer on adjacent semiconductor fin surface in the prior art, and larger fusion gap be present
Problem.
In order to achieve the above objects and other related objects, the present invention provides a kind of low-temperature epitaxy method, the low-temperature epitaxy
Method comprises the following steps：
S1：A substrate is provided, the substrate includes substrate and protrudes from least one semiconductor fin of the substrate surface
Piece；
S2：In the side wall and upper surface epitaxial growth epitaxial layer of the semiconductor fin；
S3：The epitaxial layer is performed etching using the etching gas cracked by ultraviolet light, it is described to be thinned
The thickness of epitaxial layer.
Alternatively, repeating said steps S2-S3 is at least once.
Alternatively, the epitaxial layer of side wall and upper surface based on the semiconductor fin makes fin formula field effect transistor
Source electrode or drain electrode.
Alternatively, the growth that the epi-layer surface after being thinned carries out epitaxial layer is continued.
Alternatively, the epitaxial layer of side wall and upper surface based on the semiconductor fin makes fin formula field effect transistor
Source electrode or drain electrode.
Alternatively, the step S2 and step S3 are completed in same reaction cavity.
Alternatively, in the step S3, the etching gas include Cl in the state of not being cleaved2, in HCl and HF
At least one.
Alternatively, in the step S3, the temperature range of selection is 650-750 DEG C.
Alternatively, in the step S3, the etching gas are mixed with delivery gas, and the delivery gas includes H2、
N2, at least one of He and Ar.
Alternatively, the material of the epitaxial layer is Si or SiGe.
Alternatively, the material selection monocrystalline silicon or germanium silicon of the semiconductor fin.
Alternatively, in the step S3, there is the surface profile of arc by thinned epitaxial layer.
The present invention also provides a kind of low-temperature epitaxy device, the low-temperature epitaxy device include reaction chamber, be connected to it is described anti-
The ultraviolet source answered the etching gas input of chamber and be arranged at outside the reaction chamber；The ultraviolet source passes through to etching
Gas, which is irradiated, makes its cracking, realizes that the epitaxial layer on semiconductor fin side wall and upper surface is thinned.
Alternatively, the ultraviolet source includes being arranged between etching gas supply line and the etching gas input
Ultraviolet photodestruciton unit, for before etching gas are inputted into the reaction chamber by the etching gas input to carve
Erosion gas is cracked.
Alternatively, the ultraviolet photodestruciton unit includes cracking chamber and the ultraviolet light list being arranged at outside the cracking chamber
Member；The etching gas of the etching gas supply line supply are inputted by the etching gas again after the cracking chamber
End is inputted into the reaction chamber.
Alternatively, the cracking chamber is using the material that can pass through ultraviolet light.
Alternatively, the low-temperature epitaxy device uses infrared light unit as heater.
Alternatively, ultraviolet light unit and infrared light unit are provided with simultaneously above the reaction chamber；Below the reaction chamber
It is provided with infrared light unit.
Alternatively, the reaction chamber is using the material that can pass through ultraviolet light and infrared light.
Alternatively, the low-temperature epitaxy device also includes the process gas input for being connected to the reaction chamber, for defeated
Enter extension reaction source gas, impurity gas or delivery gas.
Alternatively, support substrate is provided with the reaction chamber, for supporting the substrate for needing to carry out extension；The substrate bag
Include substrate and protrude from least one semiconductor fin of the substrate surface.
Alternatively, the material of the epitaxial layer is Si or SiGe.
Alternatively, the etching gas include Cl in the state of not being cleaved2, at least one of HCl and HF.
Alternatively, the temperature range that the low-temperature epitaxy device is selected when epitaxial layer is thinned by etching gas is 650-
750℃。
As described above, the low-temperature epitaxy method and device of the present invention, has the advantages that：
First, the present invention is cracked by the way of ultraviolet light to etching gas, can improve etching gas pair
The etch rate of epitaxial layer, and reduce technological temperature when etching epitaxial layer；
Second, the present invention can expand process window, reduce technology difficulty；Etching gas can use Cl2, in HCl and HF
Any one, or using any of which combine；
3rd, epitaxial layer is thinned by etching during epitaxial growth in the present invention, can improve semiconductor fin table
The surface profile of face epitaxial layer, the fusion between adjacent semiconductor fin surface epitaxial layer is avoided, or reduce epitaxial layer fusion
Caused space afterwards；
4th, the curved surfaces profile epitaxial layer that the present invention is formed in semiconductor fin can expand fin volume, full
The making demand of the source-drain electrode of the advanced logical device of foot；
5th, present invention process and device are simple, are with a wide range of applications in field of semiconductor manufacture.
Brief description of the drawings
Fig. 1 is shown as the profile of semiconductor structure of the prior art.
The fusion for the epitaxial layer that Fig. 2 is shown as being grown on fin adjacent in the prior art causes undesirable space to produce
Raw schematic diagram.
Fig. 3 is shown as the section of the semiconductor structure presented in the prior art by deposition-etch-redeposited step
Figure.
Fig. 4 is shown as the process chart of the low-temperature epitaxy method of the present invention.
Fig. 5-Figure 10 is shown as the section of structure that each step of low-temperature epitaxy method of the present invention is presented.
Figure 11 is shown as the structural representation of the low-temperature epitaxy equipment of the present invention.
Component label instructions
2nd, 24 fin
4th, 36,36_1,36_2 epitaxial layer
6th, 22 shallow trench isolation area
8 faces
10 spaces
20 substrates
T epitaxial layers increased part thickness
101 substrates
102 fleet plough groove isolation structures
103 semiconductor fins
104th, 105 epitaxial layer
106 reaction chambers
107 etching gas inputs
108 etching gas supply lines
109 cracking chambers
110,112 ultraviolet light units
111 infrared light units
113 process gas inputs
114 support substrates
115 substrates
116 tail gas output ends
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 4 is referred to Figure 11.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, the component relevant with the present invention is only shown in schema then rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
The present invention provides a kind of low-temperature epitaxy method, referring to Fig. 4, the process chart of this method is shown as, including such as
Lower step：
S1：A substrate is provided, the substrate includes substrate and protrudes from least one semiconductor fin of the substrate surface
Piece；
S2：In the side wall and upper surface epitaxial growth epitaxial layer of the semiconductor fin；
S3：The epitaxial layer is performed etching using the etching gas cracked by ultraviolet light, it is described to be thinned
The thickness of epitaxial layer.
Referring initially to Fig. 5, step S1 is performed：A substrate is provided, the substrate includes substrate 101 and protrudes from the base
At least one semiconductor fin 103 on the surface of bottom 101.
Specifically, the substrate 101 includes but is not limited to the conventional semiconductor substrates such as silicon, germanium, germanium silicon.The substrate 101
It can be that p-type is adulterated, or n-type doping.
In the present embodiment, fleet plough groove isolation structure 102 is also formed with the substrate 101.The fleet plough groove isolation structure
102 can be by forming multiple spaced grooves in the substrate 101, and fills dielectric in the groove and obtain
Arrive.The dielectric includes but is not limited to earth silicon material.
The semiconductor fin 103 is in the horizontal direction between two fleet plough groove isolation structures 102, and positioned at described
On fleet plough groove isolation structure 102.
In one embodiment, the material of the semiconductor fin 103 can use identical material with the substrate 101
Material.Such as the material of the semiconductor fin 103 and the substrate 101 is monocrystalline silicon, or it is germanium silicon.In such case
Under, the semiconductor fin 103 can be obtained by removing the tip portion of the fleet plough groove isolation structure 102.Certainly, described half
Conductor fin 103 can also be obtained by extension.
In another embodiment, the material of the semiconductor fin 103 can also use different from the substrate 101
Material.For example, the substrate 101 selects one of silicon substrate and germanium substrate, the semiconductor fin 103 uses germanium silicon material
Material；Or the substrate 101 selects one of germanium silicon substrate and germanium substrate, the semiconductor fin 103 uses monocrystalline silicon material
Material.
Referring next to Fig. 6, step S2 is performed：Outside the side wall of the semiconductor fin 103 and upper surface epitaxial growth
Prolong layer 104.
Specifically, the material of the epitaxial layer 104 can be identical with the semiconductor fin 103, can also be different.As
Example, the material of the epitaxial layer 104 is Si or SiGe.Ge component can be adjusted according to being actually needed in wherein SiGe
It is whole.
The epitaxial layer 104 can be obtained by process for vapor phase epitaxy.Specifically, the substrate is placed in reaction chamber, will
The substrate is heated to preset temperature, and extension reaction source gas is passed through in reaction chamber, is exposed in the semiconductor fin 103
Epitaxial layer 104 described in part Epitaxial growth out.
As an example, the temperature range selected by epitaxial growth Si epitaxial layers is 750 DEG C -850 DEG C, outside epitaxial growth SiGe
It is 650 DEG C -800 DEG C to prolong the temperature range selected by layer.In the present embodiment, the epitaxial growth SiGe preferably at a temperature of 690 DEG C
Epitaxial layer.
As an example, the silicon source in the reaction source gas is selected from dichloro hydrogen silicon (SiH2Cl2), trichlorosilane (SiHCl3)、
Silicon tetrachloride (SiCl4) and silane (SiH4) in one or more；Ge source in the reaction source selects germane (GeH4).
SiGe epitaxial layers are formed, the SiGe epitaxial layers of specific Ge components can be realized by adjusting the flow of ge source.
During epitaxial growth, delivery gas can be passed through simultaneously.As an example, the delivery gas includes H2、N2、He
And one or both of Ar combination of the above, in the present embodiment, it is H that the delivery gas, which is selected,2。
During epitaxial growth, often need to control doping, to ensure to control resistivity.Dopant used in N-type epitaxy layer is general
For phosphine (PH3) phosphorus trichloride (PCl3) or arsine (AsH3) etc.；Dopant used in p-type epitaxial layer is generally diborane
(B2H6) or boron chloride (BCl3) etc..Therefore, during epitaxial growth, impurity gas can be passed through simultaneously, it is more to realize
Extension function, the impurity gas can include the one or more in n-type doping gas and p-type impurity gas.
In addition, during extension, selection gas, such as HCl gases can be passed through simultaneously so that epitaxial layer 104 selects
Property in the superficial growth of semiconductor fin 103, but will not be grown on fleet plough groove isolation structure 102.
As shown in fig. 6, because epitaxial layer has different growth rates in different surface orientations, it is thus possible to can be formed
Multiple faces.With the progress of epitaxial growth, wedge angle can be gradually formed between multiple faces of epitaxial layer so that epitaxial layer it is laterally wide
Degree increase, and epitaxial layer volume is also insufficient to.
Again referring to Fig. 7, performing step S3：Using the etching gas cracked by ultraviolet light to the epitaxial layer
104 perform etching, so that the thickness of the epitaxial layer 104 is thinned.
As an example, the etching gas include Cl in the state of not being cleaved2, at least one of HCl and HF.Its
In, Cl2Maximum light absorption wavelength (Optical Absorption wave length) be 332nm (at this wavelength, extinctions
Angle value reaches maximum), HCl maximum light absorption wavelength is 154nm, and HF maximum light absorption wavelength is 332nm, in ultraviolet light
Compose in the range of (10~380nm).
Ultraviolet light etching gas are used in this step, (or to decompose) etching gas can be cracked, make etching gas
Body fully activates (activate), has stronger etching power, and can realize Cryo-etching.Such as chlorine molecule is ultraviolet
Under light action, energy is absorbed, breaking of covalent bonds dissociation is turned into two activation chlorine atoms, and it is smaller to activate chlorine atom radius, takes by force
Take or attract the ability of electronics stronger, very vivaciously, can be achieved externally to prolong the etching of layer at a lower temperature.
As an example, the temperature range that selection is etched in this step is 650-750 DEG C, for example, 660 DEG C, 670 DEG C, 680 DEG C,
690 DEG C, 695 DEG C, 700 DEG C, 710 DEG C, 720 DEG C, 730 DEG C, 740 DEG C etc..
This step can be completed with the step S2 in same reaction cavity, and the etching gas can be mixed with delivery gas
Body.As an example, the delivery gas includes H2、N2, at least one of He and Ar.
Front profile is thinned as shown in fig. 7, adopting and illustrate with dashed lines the epitaxial layer 104, and the etching Jing Guo this step, subtract
Epitaxial layer 104 after thin has the surface profile of arc, reduces the fusion probability of the upper epitaxial layer of adjacent semiconductor fin 103.
The epitaxial layer 105 can use identical material with epitaxial layer 104, can also use different materials.Figure 10
Described in the boundary of epitaxial layer 105 and epitaxial layer 104 adopt and be represented by dashed line, it is meant that this interface is probably sightless.
In another embodiment, repeating said steps S2-S3 may be selected at least once, to increase the volume of epitaxial layer.Fig. 8
The method of the step S2 is shown with further in the schematic diagram of the superficial growth epitaxial layer 105 of epitaxial layer 104, Fig. 9
The schematic diagram of the epitaxial layer 105 is further thinned in the method for being shown with the step S3.
In another embodiment, the epi-layer surface after being thinned can also continued carrying out the growth of epitaxial layer, and nothing
Need to further it be thinned, because etch step above reduces the probability that further extension produces fusion.Or repeating
The step S2-S3 at least once after, continue be thinned after epi-layer surface carry out epitaxial layer growth, without entering one
Step is thinned.
Epitaxial layer is thinned by etching during epitaxial growth in the low-temperature epitaxy method of the present invention, can improve and partly lead
The surface profile of body fin surface epitaxial layer, the fusion between adjacent semiconductor fin surface epitaxial layer is avoided, or reduced outer
Prolong caused space after layer merges.Wherein, the mode of ultraviolet light etching gas can improve etching gas to epitaxial layer
Etch rate, and technological temperature when reducing etching epitaxial layer so as to expand process window, reduces technology difficulty.Due to half
The epitaxial layer of the curved surfaces profile formed on conductor fin expands fin volume, can meet advanced logical device (such as
Fin formula field effect transistor) source electrode or drain electrode making demand.
Embodiment two
The present invention also provides a kind of low-temperature epitaxy device, refers to Figure 11, is shown as the structural representation of the device, including
Reaction chamber 106, the etching gas input 107 for being connected to the reaction chamber 106 and it is arranged at outside the reaction chamber 106
Ultraviolet source；The ultraviolet source makes its cracking by being irradiated to etching gas, realizes semiconductor fin side wall and upper table
Epitaxial layer on face is thinned.
As an example, the ultraviolet source includes being arranged at etching gas supply line 108 and etching gas input
Ultraviolet photodestruciton unit between end 107, for being inputted in etching gas by the etching gas input 107 into described anti-
Answer and etching gas are cracked before chamber 106.
As an example, the ultraviolet photodestruciton unit includes cracking chamber 109 and is arranged at outside the cracking chamber 109
Ultraviolet light unit 110；The etching gas that the etching gas supply line 108 is supplied lead to again after the cracking chamber 109
The etching gas input 107 is crossed to input into the reaction chamber 106.
As an example, the ultraviolet light unit 110 uses ultraviolet lamp, the cracking chamber 109 is using permeable ultraviolet light
Material, such as quartz glass etc..
As an example, ultraviolet light unit 112 has may further be provided in the top of reaction chamber 106, for being gone back to part
The etching gas not being cleaved further are cracked, and further improve the utilization rate of etching gas.
As an example, the etching gas include Cl in the state of not being cleaved2, at least one of HCl and HF.
Under ultraviolet light, etching gas cracking (or being to decompose) is atom, etching gas is fully activated (activate), has
Stronger etching power, and Cryo-etching can be realized.Such as chlorine molecule absorbs energy under action of ultraviolet light, makes covalently
Key fracture dissociation turns into two activation chlorine atoms, and activates that chlorine atom radius is smaller, captures or attract the ability of electronics stronger, non-
It is often active, it can be achieved externally to prolong the etching of layer at a lower temperature.As an example, the low-temperature epitaxy device is passing through etching
It is 650-750 DEG C that the temperature range selected during epitaxial layer, which is thinned, in gas.
As shown in figure 11, the low-temperature epitaxy device is used as heater using infrared light unit 111.The infrared light list
Infrared lamp specifically can be selected in member 111.As an example, the infrared light list is provided with above and below the reaction chamber 106
Member 111, wherein, the infrared light unit 111 for being arranged at the top of reaction chamber 106 is alternately arranged with the ultraviolet light unit 112.
In addition, the infrared light 111 is uniformly distributed in above and below the reaction chamber 106, the ultraviolet light unit 112 is uniformly distributed
Above the reaction chamber 106, the so uniform quality that the temperature homogeneity that can improve heating is set, improves epitaxial crystal
And the uniformity of epitaxial layer etching.As an example, the material of the epitaxial layer is Si or SiGe.
Because the ultraviolet light unit 112 and infrared light unit 111 may be contained within outside the reaction chamber, thus it is described anti-
Answer chamber preferably using the material that can pass through ultraviolet light and infrared light.
Certainly, the set location of the ultraviolet light unit and infrared light unit can be changed according to demand, and unlimited
In example recited herein.
As shown in figure 11, the low-temperature epitaxy device further comprises that the process gas for being connected to the reaction chamber 106 is defeated
Enter end 113, for inputting extension reaction source gas, impurity gas or delivery gas etc., realize the epitaxial growth of epitaxial layer.
It is pointed out that a process gas input 113 is illustrate only for ease of illustration, in Figure 11, but
Reality use in, the quantity of the process gas input 113 can be adjusted as needed, for example, 2,3 even
More, should not too limit the scope of the invention herein.
Support substrate 114 is additionally provided with the reaction chamber 106, for supporting the substrate 115 for needing to carry out extension；The base
Piece 115 includes substrate and protrudes from least one semiconductor fin of the substrate surface.As an example, the support substrate
114 graphite substrates covered from SiC.
The low-temperature epitaxy device of the present invention can realize the growth of epitaxial layer and the Cryo-etching of epitaxial layer, improve semiconductor
The surface profile of fin surface epitaxial layer, meet the making demand of the source-drain electrode of advanced logical device.
In summary, low-temperature epitaxy method and device of the invention, has the advantages that：
First, the present invention is cracked by the way of ultraviolet light to etching gas, can improve etching gas pair
The etch rate of epitaxial layer, and reduce technological temperature when etching epitaxial layer；
Second, the present invention can expand process window, reduce technology difficulty；Etching gas can use Cl2, in HCl and HF
Any one, or using any of which combine；
3rd, the present invention can improve the surface profile of semiconductor fin surface epitaxial layer, avoid by etching epitaxial layer
Fusion between adjacent semiconductor fin surface epitaxial layer, or reduce caused space after epitaxial layer fusion；
4th, the curved surfaces profile epitaxial layer that the present invention is formed in semiconductor fin can expand fin volume, full
The making demand of the source-drain electrode of the advanced logical device of foot；
5th, present invention process and device are simple, are with a wide range of applications in field of semiconductor manufacture.
So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (24)
- A kind of 1. low-temperature epitaxy method, it is characterised in that the low-temperature epitaxy method comprises the following steps：S1：A substrate is provided, the substrate includes substrate and protrudes from least one semiconductor fin of the substrate surface；S2：In the side wall and upper surface epitaxial growth epitaxial layer of the semiconductor fin；S3：The epitaxial layer is performed etching using the etching gas cracked by ultraviolet light, so that the extension is thinned The thickness of layer.
- 2. low-temperature epitaxy method according to claim 1, it is characterised in that：Repeating said steps S2-S3 is at least once.
- 3. low-temperature epitaxy method according to claim 1 or 2, it is characterised in that：Side wall based on the semiconductor fin And the epitaxial layer of upper surface makes source electrode or the drain electrode of fin formula field effect transistor.
- 4. low-temperature epitaxy method according to claim 1 or 2, it is characterised in that：Continue the epi-layer surface after being thinned Carry out the growth of epitaxial layer.
- 5. low-temperature epitaxy method according to claim 4, it is characterised in that：Side wall based on the semiconductor fin and on The epitaxial layer on surface makes source electrode or the drain electrode of fin formula field effect transistor.
- 6. low-temperature epitaxy method according to claim 1, it is characterised in that：The step S2 and step S3 are in same reaction Completed in cavity.
- 7. low-temperature epitaxy method according to claim 1, it is characterised in that：In the step S3, the etching gas Include Cl in the state of not being cleaved2, at least one of HCl and HF.
- 8. low-temperature epitaxy method according to claim 1, it is characterised in that：In the step S3, the temperature model of selection Enclose is 650-750 DEG C.
- 9. low-temperature epitaxy method according to claim 1, it is characterised in that：In the step S3, the etching gas Delivery gas is mixed with, the delivery gas includes H2、N2, at least one of He and Ar.
- 10. low-temperature epitaxy method according to claim 1, it is characterised in that：The material of the epitaxial layer is Si or SiGe.
- 11. low-temperature epitaxy method according to claim 1, it is characterised in that：The material selection list of the semiconductor fin Crystal silicon or germanium silicon.
- 12. low-temperature epitaxy method according to claim 1, it is characterised in that：It is outer by what is be thinned in the step S3 Prolonging layer has the surface profile of arc.
- 13. a kind of low-temperature epitaxy device, it is characterised in that the low-temperature epitaxy device includes reaction chamber, is connected to the reaction The etching gas input of chamber and the ultraviolet source being arranged at outside the reaction chamber；The ultraviolet source passes through to etching gas Body, which is irradiated, makes its cracking, realizes that the epitaxial layer on semiconductor fin side wall and upper surface is thinned.
- 14. low-temperature epitaxy device according to claim 13, it is characterised in that：The ultraviolet source includes being arranged at etching Ultraviolet photodestruciton unit between gas supply pipeline and the etching gas input, for passing through the quarter in etching gas Erosion gas input cracks before inputting into the reaction chamber to etching gas.
- 15. low-temperature epitaxy device according to claim 14, it is characterised in that：The ultraviolet photodestruciton unit includes cracking Chamber and the ultraviolet light unit being arranged at outside the cracking chamber；The etching gas of the etching gas supply line supply pass through Inputted again by the etching gas input into the reaction chamber after the cracking chamber.
- 16. low-temperature epitaxy device according to claim 15, it is characterised in that：The cracking chamber is using permeable ultraviolet light Material.
- 17. low-temperature epitaxy device according to claim 13, it is characterised in that：The low-temperature epitaxy device uses infrared light Unit is as heater.
- 18. low-temperature epitaxy device according to claim 13, it is characterised in that：Purple is provided with above the reaction chamber simultaneously Outer light unit and infrared light unit；Infrared light unit is provided with below the reaction chamber.
- 19. low-temperature epitaxy device according to claim 13, it is characterised in that：The reaction chamber is using permeable ultraviolet light And the material of infrared light.
- 20. low-temperature epitaxy device according to claim 13, it is characterised in that：The low-temperature epitaxy device also includes connection In the process gas input of the reaction chamber, for inputting extension reaction source gas, impurity gas or delivery gas.
- 21. low-temperature epitaxy device according to claim 13, it is characterised in that：Support substrate is provided with the reaction chamber, For supporting the substrate for needing to carry out extension；The substrate includes substrate and protrudes from least one half of the substrate surface and lead Body fin.
- 22. low-temperature epitaxy device according to claim 13, it is characterised in that：The material of the epitaxial layer be Si or SiGe。
- 23. low-temperature epitaxy device according to claim 13, it is characterised in that：The etching gas are in the shape not being cleaved Include Cl under state2, at least one of HCl and HF.
- 24. low-temperature epitaxy device according to claim 13, it is characterised in that：The low-temperature epitaxy device is passing through etching It is 650-750 DEG C that the temperature range selected during epitaxial layer, which is thinned, in gas.
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| CN201610435872.XA CN107516636A (en) | 2016-06-17 | 2016-06-17 | A kind of low-temperature epitaxy method and device |
| TW105137530A TWI591699B (en) | 2016-06-17 | 2016-11-16 | Low temperature epitaxy method and equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110592665A (en) * | 2019-08-09 | 2019-12-20 | 上海新昇半导体科技有限公司 | Method for improving flatness of semiconductor film |
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|---|---|---|---|---|
| JPS622622A (en) * | 1985-06-28 | 1987-01-08 | Nec Corp | Surface treatment method |
| JPH06244106A (en) * | 1993-02-19 | 1994-09-02 | Nippondenso Co Ltd | Manufacture of semiconductor substrate |
| CN101802985A (en) * | 2007-09-14 | 2010-08-11 | 高通Mems科技公司 | Etching processes used in mems production |
| CN102169853A (en) * | 2010-02-26 | 2011-08-31 | 台湾积体电路制造股份有限公司 | Method of forming an integrated circuit structure |
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- 2016-06-17 CN CN201610435872.XA patent/CN107516636A/en active Pending
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| JPS622622A (en) * | 1985-06-28 | 1987-01-08 | Nec Corp | Surface treatment method |
| JPH06244106A (en) * | 1993-02-19 | 1994-09-02 | Nippondenso Co Ltd | Manufacture of semiconductor substrate |
| CN101802985A (en) * | 2007-09-14 | 2010-08-11 | 高通Mems科技公司 | Etching processes used in mems production |
| CN102169853A (en) * | 2010-02-26 | 2011-08-31 | 台湾积体电路制造股份有限公司 | Method of forming an integrated circuit structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110592665A (en) * | 2019-08-09 | 2019-12-20 | 上海新昇半导体科技有限公司 | Method for improving flatness of semiconductor film |
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| TW201810388A (en) | 2018-03-16 |
| TWI591699B (en) | 2017-07-11 |
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Application publication date: 20171226 |