TW201802790A - 畫素驅動電路及具有畫素驅動電路的顯示裝置 - Google Patents
畫素驅動電路及具有畫素驅動電路的顯示裝置 Download PDFInfo
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- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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Abstract
一種畫素驅動電路與三條掃描線和一條資料線連接,包括第一電晶體、第二電晶體、第三電晶體、第四電晶體、有機發光二極體以及存儲電容。第一電晶體的柵極與第一掃描線連接,汲極與資料線連接,源極與第二電晶體的柵極連接。第二電晶體的汲極與第三電晶體的源極連接,源極與有機發光二極體的陽極連接。第三電晶體的柵極與第三掃描線連接,汲極與電源線連接。第四電晶體的柵極與第二掃線連接,汲極與第二結點連接,源極與初始電壓連接。有機發光二極體的陽極與第二電晶體的源極連接,陰極與接地端連接。存儲電容連接於第二電晶體的柵極和源極之間。本發明還提供一種具有該畫素驅動電路的顯示裝置。
Description
本發明涉及一種畫素驅動電路及具有畫素驅動電路的顯示裝置。
隨著電子技術的不斷發展,手機、可擕式電腦、個人數位助理(PDA)、平板電腦、媒體播放機等消費性電子產品大多都採用顯示器作為輸入裝置,以使產品具有更友好的人機對話模式。顯示器包括液晶顯示器、發光二極體(Light Emitting Diode,OLED)顯示器以及有機發光二極體(Organic Light Emitting Diode,OLED)顯示器等多種類型。顯示器包括顯示模組以及驅動顯示模組的畫素驅動電路。顯示模組包括多個畫素單元,每個畫素單元對應有一個畫素驅動電路。畫素驅動電路通常設置於顯示器的非顯示區域。隨著窄邊框設計需求的增加,非顯示區域的面積縮小,因此,畫素驅動電路的電路結構需要進行簡化。
有鑑於此,有必要提供一種具有簡化電路結構的畫素驅動電路。
還有必要提供一種具有該畫素驅動電路的顯示裝置。
一種畫素驅動電路,其與三多條掃描線和一條資料線電性連接。畫素驅動電路包括第一電晶體、第二電晶體、第三電晶體、第四電晶體、有機發光二極體以及存儲電容。第一電晶體的柵極與第一掃描線電性連接,汲極與資料線電性連接,源極藉由第一結點與第二電晶體的柵極電性連接。第二電晶體的汲極與所述第三電晶體的源極電性連接,源極藉由第二結點與所述有機發光二極體的陽極電性連接。第三電晶體的柵極與所述第三掃描線電性連接,汲極與電源線電性連接。第四電晶體的柵極與所述第二掃線電性連接,汲極與所述第二結點電性連接,源極與初始電壓電性連接。有機發光二極體的陽極與所述第二電晶體的源極電性連接,陰極與接地端電性連接。存儲電容電性連接於所述第二電晶體的柵極和源極之間。
一種顯示裝置,包括多條相互平行設置的掃描線以及多條相互平行且與所述掃描線正交設置的資料線。多條掃描線與所述多條資料線垂直絕緣相交,定義出多個畫素單元。每個畫素單元均對應有一個畫素驅動電路。畫素驅動電路為申請專利範圍第1-7項中任意一項所述的畫素驅動電路。
採用上述畫素驅動電路的顯示裝置,畫素驅動電路採用三條掃描線、四個電晶體與時序電路的配合,使得在寫入階段結束時進入發光階段前鎖定並保持發光二極體陽極的電壓,同時採用四個電晶體相對於採用五個及以上電晶體的畫素驅動電路,減少畫素驅動電路元件,提高了非顯示區域的空間利用率,並保證了顯示裝置的顯示效果。
圖1為一種較佳實施方式之顯示裝置之平面示意圖。
圖2為圖1所示之畫素單元的畫素驅動電路的等效電路示意圖。
圖3為圖2所示之畫素驅動電路的時序示意圖。
圖4為圖2所示之畫素驅動電路在重置階段的等效電路示意圖。
圖5為圖2所示之畫素驅動電路在補償階段的等效電路示意圖。
圖6為圖2所示之畫素驅動電路在第一寫入階段的等效電路示意圖。
圖7為圖2所示之畫素驅動電路在第二寫入階段的等效電路示意圖。
圖8為圖2所示之畫素驅動電路在發光階段的等效電路示意圖。
請參閱圖1,圖1是本發明一實施例的顯示裝置100的平面示意圖。該顯示裝置100包括多條相互平行設置的掃描線S1-Sn以及多條相互平行且與所述掃描線S1-Sn正交設置的數據線D1-Dn。所述多條掃描線S1-Sn分別與所述第一驅動電路110電性連接,所述多條資料線D1-Dn分別與所述第二驅動電路120電性連接。所述多條掃描線S1-Sn與所述多條資料線D1-Dn垂直絕緣相交,定義出多個畫素單元20。所述顯示裝置100定義有一個顯示區域101以及圍繞所述顯示區域101設置的非顯示區域103。所述掃描線S1-Sn、所述資料線D1-Dn以及所述畫素單元20設置於所述顯示區域101內,所述第一驅動電路110和所述第二驅動電路120設置於所述非顯示區域103內。本實施例中,所述第一驅動電路110設置於所述顯示區域101的上側,所述第二驅動電路120設置於所述顯示區域101的左側。所述畫素單元20與對應的資料線D1-Dn電性連接,所述每個畫素單元20具有一個對應的驅動電路200(如圖2所示)。在本實施方式中,顯示裝置100可以為自發光式顯示器,如有機電致發光時顯示器,或一非自發光式顯示器,如液晶顯示器。在本實施方式中,第一驅動電路110可包括多工電路和柵極驅動電路。第二驅動電路120為資料驅動電路。
請參閱圖2,其為畫素單元20中畫素驅動電路200的等效電路圖。所述畫素驅動電路200包括電源線VDD、初始端Vini、第一電晶體T1、第二電晶體T2、第三電晶體T3、第四電晶體T4、第一結點A、第二結點B、有機發光二極體OLED、存儲電容Cs、寄生電容COLED以及接地端Vss。在本實施方式中,所述第一電晶體T1、第二電晶體T2、第三電晶體T3以及第四電晶體T4可以為多晶矽薄膜電晶體、非晶矽薄膜電晶體或有機薄膜電晶體中的任意一種。在本實施方式中,初始端Vini始終處於低電平狀態。
所述第一電晶體T1的柵極與第一掃描線S1電性連接,汲極與所述資料線D1電性連接,源極藉由所述第一結點A與所述第二電晶體的柵極T2電性連接。所述第二電晶體T2的汲極與所述第三電晶體T3的源極電性連接,所述第二電晶體T2的源極藉由第二結點B與所述有機發光二極體OLED的陽極電性連接。所述第三電晶體T3的柵極與所述第三掃描線S3電性連接,所述第三電晶體T3的汲極與所述電源線VDD電性連接。所述第四電晶體T4的柵極與所述第二掃描線S2電性連接,所述第四電晶體T4的汲極與所述第二結點B電性連接,即,所述第四電晶體T4的汲極電性連接於所述第二電晶體T2的源極和所述有機發光二極體OLED的陽極之間,所述第四電晶體T4的源極與所述初始電壓Vini電性連接。所述有機發光二極體OLED的陽極與所述第二電晶體的源極電性連接,陰極與所述接地端Vss電性連接。所述存儲電容Cs電性連接於所述第二電晶體T2的柵極和源極之間。所述寄生電容COLED電性連接於所述有機發光二極體OLED陰極和陽極之間。在本實施方式中,掃描線S1-Sn的電壓可在低電平和高電平之間進行切換,且資料線D1-Dn的電壓可在偏置電壓Vofs和寫入電壓Vsig之間切換。其中,偏置電壓Vofs為低電平,寫入電壓Vsig為高電平。
請參閱圖3,其為所述畫素驅動電路200的時序示意圖。所述畫素驅動電路200在一幀時間內依次經過重置階段Tset、電壓補償階段Tcom、寫入階段Tw以及發光階段Ti進行操作。其中,所述寫入階段Tw包括第一寫入階段Tw1和第二寫入階段Tw2(也可稱之為移動補償階段)。
請一併參閱圖4,所述畫素驅動電路200在處於所述重置階段Tset時,所述第一掃描線S1、所述第二掃描線S2以及所述第三掃描線S3均處於高電平,所述資料線D1的電壓處於偏置電壓Vofs,所述第一電晶體T1、所述第二電晶體T2所述第三電晶體T3以及所述第四電晶體T4處於導通狀態,所述第一掃描線S1藉由所述第一電晶體T1對所述第一結點A和所述存儲電容Cs充電。由於所述第四電晶體T4導通,所述第二結點B的電壓等於所述初始端Vini的電壓,即,所述發光二極體OLED兩端的電壓差小於其導通電壓,所述發光二極體OLED不發光。
請一併參閱圖5,所述畫素驅動電路200處於電壓補償階段Tcom時,所述第一掃描線S1和所述第三掃描線S3維持處於高電平狀態,所述第二掃描線S2切換至低電平,且所述資料線D1處於偏置電壓Vofs,所述第一電晶體T1、所述第二電晶體T2以及所述第三電晶體T3處於導通狀態,所述第四電晶體T4處於截止狀態。所述存儲電容Cs藉由所述第二電晶體T2進行放電,且當所述第二結點B的電壓等於資料線D1的偏置電壓Vofs與所述第二電晶體T2的閾值電壓Vth的差值,使得所述第二電晶體T2截止。此時,所述發光二極體OLED兩端的電壓差小於其導通電壓,所述發光二極體OLED不發光。
請一併參閱圖6所述畫素驅動電路200處於第一寫入階段Tw1時,所述第一掃描線S1維持處於高電平狀態,所述第二掃描線S2和所述第三掃描線S3均處於低電平狀態,且所述資料線D1由偏置電壓Vofs切換至寫入電壓Vsig(即,藉由資料線D1寫入資料),所述第一電晶體T1和所述第二電晶體T2處於導通狀態,所述第三電晶體T3和所述第四電晶體T4處於截止狀態,所述資料線D1的寫入電壓Vsig對第一結點A進行充電和所述寄生電容COLED進行充電,使得所述第二結點B的電壓提升。此時,所述第二結點B的電壓可根據所述寫入電壓Vsig、所述偏置電壓Vofs、所述第二電晶體T2的閾值電壓Vth、所述存儲電容Cs以及所述寄生電容COLED的數值根據公式一計算得出。
公式一:VB=Vofs-Vth+[(Vsig-Vofs)Cs/(Cs+COLED
)]
請一併參閱圖7,所述畫素驅動電路處於第二寫入階段Tw2時,所述第一掃描線S1、所述第二掃描線S2以及所述第三掃描線S3均處於低電平狀態,且所述資料線D1維持在寫入電壓Vsig,所述第一電晶體T1、所述第三電晶體T3以及所述第四電晶體T4處於截止狀態,以維持所述第二結點B的電壓。
在整個資料寫入階段Tw內,所述發光二極體OLED兩端的電壓差小於其導通電壓,所述發光二極體OLED不發光。
請一併參閱圖8,所述畫素驅動電路200處於發光階段Ti時,所述第一掃描線S1和所述第二掃描線S2處於低電平狀態,所述第三掃描線S3處於高電平狀態,且所述資料線D1切換至偏置電壓Vofs,所述第一電晶體T1和所述第四電晶體S4處於截止狀態,所述第二電晶體T2和所述第三電晶體T3處於導通狀態,所述電源線VDD藉由所述第三電晶體T3對所述第一結點A和所述寄生電容COLED繼續進行充電,使得所述第一結點A的電壓由寫入電壓Vsig提升為寫入電壓Vsig與提升電壓Vf之和,所述第二結點B的電壓可根據所述寫入電壓Vsig、所述偏置電壓Vofs、所述第二電晶體T2的閾值電壓Vth、所述存儲電容Cs以及所述寄生電容COLED的數值根據公式二計算得出。
公式二:VB
=Vofs-Vth+[(Vsig-Vofs)Cs/(Cs+COLED
)]+Vf
當所述第二結點B的電壓大於所述發光二極體OLED的導通電壓時,所述發光二極體OLED開始發光,同時所述第二電晶體T2由懸浮狀態切換至導通狀態。
上述顯示裝置100中,畫素驅動電路200採用三條掃描線、四個電晶體與時序電路的配合,使得在寫入階段結束時進入發光階段前鎖定並保持發光二極體陽極的電壓,同時採用四個電晶體相對於採用五個及以上電晶體的畫素驅動電路,減少畫素驅動電路200元件,提高了非顯示區域103的空間利用率,並保證了顯示裝置100的顯示效果。
綜上所述,本發明符合發明專利要件,爰依法提出專利申請。惟,以上所述者僅為本發明之較佳實施方式,舉凡熟悉本案技藝之人士,在爰依本案創作精神所作之等效修飾或變化,皆應包含於以下之申請專利範圍內。
100‧‧‧顯示裝置
S1-Sn‧‧‧掃描線
D1-Dn‧‧‧數據線
20‧‧‧畫素單元
101‧‧‧顯示區域
103‧‧‧非顯示區域
110‧‧‧第一驅動電路
120‧‧‧第二驅動電路
200‧‧‧驅動電路
T1‧‧‧第一電晶體
T2‧‧‧第二電晶體
T3‧‧‧第三電晶體
T4‧‧‧第四電晶體
Cs‧‧‧存儲電容
COLED‧‧‧寄生電容
VDD‧‧‧電源線
Vss‧‧‧接地端
Vini‧‧‧初始端
Tset‧‧‧重置階段
Tcom‧‧‧補償階段
Tw‧‧‧寫入階段
Tw1‧‧‧第一寫入階段
Tw2‧‧‧第二寫入階段
Ti‧‧‧發光階段
Vofs‧‧‧偏置電壓
Vsig‧‧‧寫入電壓
Vth‧‧‧閾值電壓
Vf‧‧‧提升電壓
無
200‧‧‧驅動電路
T1‧‧‧第一電晶體
T2‧‧‧第二電晶體
T3‧‧‧第三電晶體
T4‧‧‧第四電晶體
Cs‧‧‧存儲電容
COLED‧‧‧寄生電容
VDD‧‧‧電源線
Vss‧‧‧接地端
Vini‧‧‧初始端
Claims (8)
- 一種畫素驅動電路,其與三條掃描線和一條資料線電性連接;其中,所述畫素驅動電路包括第一電晶體、第二電晶體、第三電晶體、第四電晶體、有機發光二極體以及存儲電容; 所述第一電晶體的柵極與第一掃描線電性連接,汲極與資料線電性連接,源極藉由第一結點與第二電晶體的柵極電性連接; 所述第二電晶體的汲極與所述第三電晶體的源極電性連接,源極藉由第二結點與所述有機發光二極體的陽極電性連接; 所述第三電晶體的柵極與所述第三掃描線電性連接,汲極與電源線電性連接; 所述第四電晶體的柵極與所述第二掃線電性連接,汲極與所述第二結點電性連接,源極與初始電壓電性連接; 所述有機發光二極體的陽極與所述第二電晶體的源極電性連接,陰極與接地端電性連接; 所述存儲電容電性連接於所述第二電晶體的柵極和源極之間。
- 如申請專利範圍第1項所述之畫素驅動電路,其中,所述畫素驅動電路用於驅動一個畫素單元在一幀時間內依次經過重置階段、電壓補償階段、寫入階段以及發光階段;所述寫入階段包括第一寫入階段和第二寫入階段;當所述驅動電路處於所述第一寫入階段,所述第一電晶體和所述第二電晶體處於導通狀態,所述第三電晶體和所述第四電晶體處於截止狀態;當所述驅動電路處於所述第二寫入階段,所述第二電晶體處於導通階段,所述第一電晶體、所述第三電晶體以及所述第四電晶體均處於截止狀態,以保持所述第二結點的電壓不變。
- 如申請專利範圍第2項所述之畫素驅動電路,其中,所述驅動電路處於重置階段時,所述第一電晶體、所述第二電晶體、所述第三電晶體以及所述第四電晶體均處於導通狀態。
- 如申請專利範圍第2項所述之畫素驅動電路,其中,所述驅動電路處於補償階段時,所述第一電晶體、所述第二電晶體以及所述第三電晶體均處於導通狀態;所述第四電晶體處於導通狀態。
- 如申請專利範圍第2項所述之畫素驅動電路,其中,所述驅動電路處於發光階段時,所述第二電晶體和所述第三電晶體均處於導通狀態;所述第一電晶體和所述第四電晶體處於導通狀態。
- 如申請專利範圍第1項所述之畫素驅動電路,其中,所述第二結點的電壓利用公式Vofs-Vth+[(Vsig-Vofs)Cs/(Cs+COLED)]計算得出;其中,Vsig為資料線的寫入電壓,Vofs為資料線的偏置電壓,Vth為所述第二電晶體的閾值電壓,Cs為所述存儲電容的容值,COLED為所述寄生電容的容值。
- 如申請專利範圍第1項所述之畫素驅動電路,其中,所述驅動電路還包括所述寄生電容電性連接於所述有機發光二極體陰極和陽極之間。
- 一種顯示裝置,包括多條相互平行設置的掃描線以及多條相互平行且與所述掃描線正交設置的資料線;所述多條掃描線與所述多條資料線垂直絕緣相交,定義出多個畫素單元;每個所述畫素單元均對應有一個畫素驅動電路;其中,所述畫素驅動電路為申請專利範圍第1-7項中任意一項所述的畫素驅動電路。
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