TW201743670A - Circuit board structure and manufacturing method thereof - Google Patents

Abstract

Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on an upper surface of the glass film, such that the first circuit layer is electrically connected with the first conductive vias. A first polymer layer is formed on the first circuit layer. The first polymer layer covers surfaces of the first circuit layer and the upper surface of the glass film. A plurality of second conductive vias are formed in the first polymer layer. A second circuit layer is formed on the first polymer layer, such that the second circuit layer is electrically connected with the second conductive vias. The E-chuck is removed.

Description

Circuit board structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a circuit board structure and a method of fabricating the same.

As consumer electronics demand for portability and multi-function increases, semiconductor components are moving toward smaller size, higher performance, and lower cost. Under this trend, semiconductor components require more input/output (I/O) pads to be added to the board over a smaller area. In other words, as the degree of integration of semiconductor components is increasing, the demand for reliability and yield of semiconductor packaging technology is increasing.

In the conventional circuit board process, a glass substrate is often used as a carrier board, and a plurality of wiring layers and a plurality of dielectric layers are respectively formed on the glass substrate. Next, the glass substrate is peeled off to form a wiring board structure. However, when the glass substrate is peeled off, since the material of the dielectric layer is too soft, it is easy to cause a warpage problem due to a stress problem. The warpage problem can reduce the reliability and yield of the product.

The invention provides a circuit board structure and a manufacturing method thereof, which can solve the warpage problem to improve the reliability and the yield of the product.

The present invention provides a method of manufacturing a wiring board structure, the steps of which are as follows. A glass film having upper and lower surfaces is provided, and the lower surface of the glass film is placed on the electrostatic chuck. A plurality of first conductive vias are formed in the upper surface of the glass film. Forming a first circuit layer on the upper surface of the glass film such that the first circuit layer is electrically connected to the first via hole. A first polymer layer is formed on the first wiring layer. The first polymer layer covers the surface of the first wiring layer and the upper surface of the glass film. A plurality of second via holes are formed in the first polymer layer. The second via hole is electrically connected to the first circuit layer. Forming a second circuit layer on the first polymer layer such that the second circuit layer is electrically connected to the second via hole. The electrostatic chuck is removed to form a first wiring board structure.

In an embodiment of the invention, the step of forming the first via hole in the glass film is as follows. The glass film is irradiated with laser light to form a plurality of modified regions in the glass film. The area outside the modified area is a non-modified area. An etching process is performed to remove the glass film of the modified region to form a plurality of first via holes in the glass film. The first through hole penetrates the upper and lower surfaces of the glass film. The conductor material is filled in the first through hole.

In an embodiment of the invention, the etching rate of the modified region to the modified region is greater than the etching rate of the non-modified region.

In an embodiment of the invention, the etching selection ratio of the modified region to the non-modified region is between 20:1 and 100:1.

In an embodiment of the invention, the step of forming the second via hole in the first polymer layer is as follows. A patterned mask layer is formed on the first polymer layer. The lithography process is performed by patterning the mask layer as a mask to form a plurality of second via holes in the first polymer layer. The conductor material is filled in the second through hole.

In an embodiment of the invention, the material of the first polymer layer comprises a photosensitive material. Photosensitive materials include chemically amplified photosensitive materials.

In an embodiment of the invention, the glass film has a thickness of between 5 microns and 100 microns. The thickness of the preferred glass film can be, for example, 10 microns, 20 microns, 30 microns, 50 microns or 80 microns.

In an embodiment of the invention, after removing the electrostatic chuck, the method further includes performing a bump process to form a plurality of bumps on the second circuit layer.

In an embodiment of the invention, after the electrostatic chuck is removed, the following steps are further included. The first wiring board structure is placed on the electrostatic chuck such that the lower surface of the glass film faces upward. Forming a third circuit layer on the lower surface of the glass film such that the third circuit layer is electrically connected to the first via hole. A second polymer layer is formed on the third wiring layer. The second polymer layer covers the surface of the third wiring layer and the lower surface of the glass film. A plurality of third via holes are formed in the second polymer layer. The third via hole is electrically connected to the third circuit layer. Forming a fourth circuit layer on the second polymer layer such that the fourth circuit layer is electrically connected to the third via hole. Remove the electrostatic chuck.

The present invention provides a wiring board structure which is produced by the above-described manufacturing method of a wiring board structure. The circuit board structure includes a glass film, a plurality of first via holes, a first circuit layer, a first polymer layer, a plurality of second via holes, and a second circuit layer. The first via hole is located in the glass film. The first circuit layer is on the glass film. The first circuit layer is electrically connected to the first via hole. The first polymer layer is on the first circuit layer. The second via is located in the first polymer layer. The second via hole is electrically connected to the first circuit layer. The second circuit layer is on the first polymer layer. The second circuit layer is electrically connected to the second via hole.

Based on the above, the present invention provides a thin glass film on an electrostatic chuck. Next, the glass film is irradiated with laser light and an etching process is performed to form a plurality of through holes in the glass film. Then, a conductor material is filled in the via hole to form a plurality of via holes. Thereafter, a wiring layer is formed on the glass film, and the electrostatic chuck is removed. In other words, the present invention can omit the step of peeling off the glass substrate to complete the reconfiguration of the redistribution layer (RDL). Therefore, the present invention can avoid the warpage problem caused by the stress caused by the peeling of the reconfigured circuit layer structure. This will increase the reliability and yield of the product.

The above described features and advantages of the invention will be apparent from the following description.

The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not be repeated.

1A through 1H are schematic cross-sectional views showing a manufacturing process of a wiring layer structure in accordance with a first embodiment of the present invention.

Referring to FIG. 1A, a glass film 102 is provided on an electrostatic chuck 100, wherein the glass film 102 has opposing upper and lower surfaces 101a, 101b. Specifically, the electrostatic chuck 100 can adsorb the lower surface 101b of the glass film 102 by electrostatic force so that the glass film 102 is held on the electrostatic chuck 100 without warping. In one embodiment, the thickness of the glass film 102 can be, for example, between 5 micrometers and 100 micrometers. Preferably, the thickness of the glass film can be, for example, 10 micrometers, 20 micrometers, 30 micrometers, 50 micrometers, or 80 micrometers; The size of the glass film 102 can be adjusted according to user needs.

Referring to FIG. 1B, the glass film 102 is irradiated with laser light to form a plurality of modified regions 102a in the glass film 102, and a region other than the modified region 102a is a non-modified region 102b. In an embodiment, the laser light may be, for example, a carbon dioxide (CO ₂ ) laser; the wavelength of the laser light may be between 9 μm and 11 μm; the energy of the laser light may be between 200 mW and Between 10 mW, the preferred laser energy can be, for example, 150 mW, 100 mW, 70 mW, 50 mW, 30 mW or 20 mW. The processing time of the laser light may be between 50 minutes and 10 minutes, and the preferred laser processing time may be, for example, 40 minutes, 30 minutes or 20 minutes.

Referring to FIG. 1B and FIG. 1C, an etching process is performed to remove the glass film 102 of the modified region 102a, and a plurality of first via holes 10 are formed in the glass film 102. The first through holes 10 penetrate the glass film 102. Surface 101a and lower surface 101b. Specifically, since the etching rate of the modified region 102a is greater than the etching rate of the non-modified region 102b, the glass film 102 of the modified region 102a can be completely removed to expose the electrostatic chuck 100. surface. However, the present invention is not limited thereto. In other embodiments, a plurality of blind holes (not shown) may be formed in the glass film 102 without exposing the surface of the electrostatic chuck 100. In an embodiment, the etching process includes a wet etching process. The wet etching process can be, for example, hydrofluoric acid (HF), dilute hydrofluoric acid (DHF) or buffered oxidizing etch (BOE). In an embodiment, the etching selectivity ratio of the modified region 102a to the non-modified region 102b may be between 20:1 and 100:1, but the invention is not limited thereto.

Referring to FIGS. 1C and 1D, a seed layer 104 is formed on a portion of the upper surface 101a of the glass film 102 and on the surface of the first via 10. In detail, a seed material layer (not shown) is formed on the glass film 102, and the seed material layer conformally covers the upper surface 101a of the glass film 102 and the surface of the first via hole 10. Next, a lithography process and an etching process are performed to remove a portion of the seed material layer to form a seed layer 104. In an embodiment, the material of the seed layer 104 comprises a metal material, a metal nitride, a metal halide, or a combination thereof. The metal material may be, for example, titanium, copper, nickel, palladium, gold, silver or alloys thereof. The method of forming the seed layer 104 includes a physical vapor deposition method, a chemical vapor deposition method, an electroplating process, or an electroless plating process, and the physical vapor deposition method may be, for example, a sputtering method or an evaporation method.

Referring to FIG. 1D and FIG. 1E, an electroplating process or an electroless plating process is performed to form a conductor structure 106 on the surface of the seed layer 104. In detail, the conductor structure 106 includes a first via hole 106a filled in the first via hole 10 and a first wiring layer 106b disposed on the upper surface 101a of the glass film 102. The first via hole 106a is electrically connected to the first circuit layer 106b. In an embodiment, the material of the conductor structure 106 comprises a metallic material. The metal material may be, for example, titanium, copper, nickel, palladium, gold, silver or alloys thereof. Incidentally, the seed layer 104 can be considered as part of the conductor structure 106. Therefore, the seed layer 104 is not shown in FIG. 1E.

Referring to FIG. 1F, a first polymer layer 108 is formed on the first wiring layer 106b. The first polymer layer 108 covers the surface of the first wiring layer 106b and the upper surface 101a of the glass film 102. In an embodiment, the material of the first polymer layer 108 comprises a photosensitive material, which may be, for example, a chemically amplified photosensitive material. In one embodiment, the chemically amplified photosensitive material may have a coefficient of thermal expansion (CTE) of between 45 ppm/° C. and 55 ppm/° C. The first polymer layer 108 may have a thickness of between 5 microns and 20 microns and may be formed by spray coating.

Referring to FIG. 1F and FIG. 1G, a patterned mask layer (not shown) is formed on the first polymer layer 108. Thereafter, a lithography process is performed with the patterned mask layer as a mask to form a plurality of second via holes 20 in the first polymer layer 108. The second through hole 20 exposes a portion of the surface of the first wiring layer 106b. It should be noted that since the chemical amplification type photosensitive material is used as the first polymer layer 108 in this embodiment, the exposure energy of the lithography process may be less than 250 mJ and the exposure time during the lithography process. Can also be shortened. In this way, the embodiment can reduce the process time to improve the yield.

Referring to FIG. 1H, a seed layer (not shown) is formed on the surface of the first polymer layer 108 and the surface of the second via hole 20, and an electroplating process or an electroless plating process is performed to perform the seed layer (not The conductor structure 110 is formed on the surface of the drawing. The material and formation method of the conductor structure 110 is similar to the material and formation method of the conductor structure 106 in FIG. 1E, and will not be described herein. Similarly, the conductor structure 110 includes a second via hole 110a filled in the second via hole 20 and a second wiring layer 110b disposed on the first polymer layer 108. The second circuit layer 110b can be electrically connected to the conductor structure 106 through the second via hole 110a. Thereafter, the electrostatic chuck 100 is removed, and the lower surface 101b of the glass film 102 is exposed to form the first wiring board structure 1.

It should be noted that the present embodiment adsorbs and holds the thin glass film 102 on the electrostatic chuck 100 such that the conductor structure 106, the first polymer layer 108, and the conductor structure 110 are formed on the upper surface 101a of the glass film 102. There is no problem with flexibility when it comes to it. Thereafter, the step of removing the electrostatic chuck 100 does not cause the warpage caused by the stress problem of the prior art. Therefore, the manufacturing method of the circuit board structure of the present embodiment can avoid the problem of deflection and warpage, thereby improving the reliability and yield of the product. In addition, in this embodiment, the polymer material is used as a dielectric layer of the wiring board, and the polymer material has a low coefficient of thermal expansion and a small amount of out gas. Therefore, the circuit board of the embodiment has better dimensional stability and is less susceptible to environmental temperature, thereby improving reliability.

In addition, after the electrostatic chuck 100 is removed, the manufacturing method of the circuit board structure of the embodiment can selectively perform a bump process to form a plurality of bumps (not shown) on the second circuit layer 110b. The bumps can electrically connect the first circuit board structure 1 to an external circuit (not shown).

2A through 2D are schematic cross-sectional views showing a manufacturing process of a wiring layer structure in accordance with a second embodiment of the present invention.

Referring to FIG. 1H and FIG. 2A, the first circuit board structure 1 of FIG. 1H described above is flipped onto the electrostatic chuck 100 such that the lower surface 101b of the glass film 102 faces upward. Thereafter, the first wiring board structure 1 (more specifically, the second wiring layer 110b is adsorbed) is electrostatically adsorbed, so that the first wiring board structure 1 is held on the electrostatic chuck 100 without warping.

Referring to FIG. 2A and FIG. 2B, a third wiring layer 206 is formed on the lower surface 101b of the glass film 102 such that the third wiring layer 206 is electrically connected to the first via hole 106a. The material and formation method of the third circuit layer 206 is similar to the material and formation method of the first circuit layer 106b in FIG. 1E, and will not be described herein.

Next, a second polymer layer 208 is formed on the third wiring layer 206. The second polymer layer 208 covers the surface of the third wiring layer 206 and the lower surface 101b of the glass film 102. The material and formation method of the second polymer layer 208 is similar to the material and formation method of the first polymer layer 108 in FIG. 1F, and will not be described herein.

Referring to FIG. 2B and FIG. 2C, a patterned mask layer (not shown) is formed on the second polymer layer 208. Thereafter, a lithography process is performed using the patterned mask layer as a mask to form a plurality of third via holes 30 in the second polymer layer 208. The third through hole 30 exposes a portion of the surface of the third wiring layer 206.

Referring to FIG. 2C and FIG. 2D, a seed layer (not shown) is formed on the surface of the second polymer layer 208 and the surface of the third via hole 30, and an electroplating process or an electroless plating process is performed to seed the seed crystal. A conductor structure 210 is formed on the surface of a layer (not shown). The material and formation method of the conductor structure 210 is similar to the material and formation method of the conductor structure 106 in FIG. 1E, and will not be described herein. Similarly, the conductor structure 210 includes a third via hole 210a filled in the third via hole 30 and a fourth wiring layer 210b disposed on the second polymer layer 208. The fourth circuit layer 210b can be electrically connected to the third circuit layer 206 through the third via hole 210a. Thereafter, the electrostatic chuck 100 is removed to expose the surface of the second wiring layer 110b to form the second wiring board structure 2.

It should be noted that although the first circuit board structure 1 of FIG. 1H only shows the via holes 106a, 110a, one polymer layer 108, and two circuit layers 106b, 110b; and the second circuit board structure 2 of FIG. 2D only draws The vias 106a, 110a, 210a, the two polymer layers 108, 208, and the four wiring layers 106b, 110b, 206, 210b are shown, but the invention is not limited thereto. In other embodiments, the number of vias, polymer layers and circuit layers, and the manner in which they are connected can be adjusted according to the needs of the designer.

In addition, after the electrostatic chuck 100 is removed, the manufacturing method of the circuit board structure of the present embodiment can selectively perform a bump process to form a plurality of bumps (not shown) on the fourth circuit layer 210b. The bumps can electrically connect the second circuit board structure 2 to an external circuit (not shown).

In summary, the present invention provides a thin glass film on an electrostatic chuck. Next, the glass film is irradiated with laser light and an etching process is performed to form a plurality of through holes in the glass film. Then, a conductor material is filled in the via hole to form a plurality of via holes. Thereafter, a wiring layer is formed on the glass film, and the electrostatic chuck is removed. In other words, the present invention can omit the step of peeling off the glass substrate to complete the reconfiguration of the wiring layer structure. Therefore, the present invention can avoid the warpage problem caused by stress caused by peeling of the reconfigured wiring layer structure, thereby improving the reliability of the product. Degree and yield.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

1‧‧‧First circuit board structure
2‧‧‧Second circuit board structure
10‧‧‧First through hole
20‧‧‧Second through hole
30‧‧‧ third through hole
100‧‧‧Electrostatic suction cup
101a‧‧‧ upper surface
101b‧‧‧ lower surface
102‧‧‧ glass film
102a‧‧‧Modified area
102b‧‧‧Non-modified areas
104‧‧‧ seed layer
106‧‧‧Conductor structure
106a‧‧‧First via
106b‧‧‧First line layer
108‧‧‧First polymer layer
110‧‧‧Conductor structure
110a‧‧‧Second via
110b‧‧‧second circuit layer
206‧‧‧ third circuit layer
208‧‧‧Second polymer layer
210‧‧‧Conductor structure
210a‧‧‧3rd via
210b‧‧‧fourth circuit layer

1A through 1H are schematic cross-sectional views showing a manufacturing process of a wiring layer structure in accordance with a first embodiment of the present invention. 2A through 2D are schematic cross-sectional views showing a manufacturing process of a wiring layer structure in accordance with a second embodiment of the present invention.

1‧‧‧First circuit board structure

20‧‧‧Second through hole

101a‧‧‧ upper surface

101b‧‧‧ lower surface

102‧‧‧ glass film

102b‧‧‧Non-modified areas

106‧‧‧Conductor structure

106a‧‧‧First via

106b‧‧‧First line layer

108‧‧‧First polymer layer

110‧‧‧Conductor structure

110a‧‧‧Second via

110b‧‧‧second circuit layer

Claims (10)

A method for manufacturing a circuit board structure, comprising: providing a glass film having upper and lower surfaces, the lower surface of the glass film being disposed on an electrostatic chuck; forming a plurality of first via holes in the upper surface of the glass film; Forming a first circuit layer on the upper surface of the glass film, such that the first circuit layer is electrically connected to the first conductive vias; forming a first polymer layer on the first circuit layer, the first a polymer layer covering a surface of the first circuit layer and an upper surface of the glass film; forming a plurality of second via holes in the first polymer layer, wherein the second via holes and the first circuit layer are electrically Connecting a second circuit layer on the first polymer layer to electrically connect the second circuit layer to the second conductive vias; and removing the electrostatic chuck to form a first circuit board structure. The method for manufacturing a circuit board structure according to claim 1, wherein the step of forming the first via holes in the glass film comprises: irradiating the glass film with a laser light to form in the glass film a plurality of modified regions, wherein the regions other than the modified regions are non-modified regions; performing an etching process to remove the glass film of the modified regions to form a plurality of first passes in the glass film a hole, wherein the first through hole penetrates the upper and lower surfaces of the glass film; and a conductive material is filled in the first through holes. The method of fabricating a circuit board structure according to claim 2, wherein an etching rate of the modified regions is greater than an etching rate of the non-modified regions. The method for manufacturing a circuit board structure according to claim 2, wherein the modified regions have an etching selection ratio of between 20:1 and 100:1 for the non-modified regions. The method of manufacturing the circuit board structure of claim 1, wherein the forming the second via holes in the first polymer layer comprises: forming a patterned mask on the first polymer layer Cursing layer; performing a lithography process on the patterned mask layer to form a plurality of second via holes in the first polymer layer; and filling a conductor in the second via holes material. The method of manufacturing a circuit board structure according to claim 1, wherein the material of the first polymer layer comprises a photosensitive material, and the photosensitive material comprises a chemically amplified photosensitive material. The method of manufacturing a wiring board structure according to claim 1, wherein the glass film has a thickness of between 5 μm and 100 μm. The method for manufacturing a circuit board structure according to claim 1, after removing the electrostatic chuck, further comprising performing a bump process to form a plurality of bumps on the second circuit layer. The method for manufacturing a circuit board structure according to claim 1, after the electrostatic chuck is removed, the method further comprises: pouring the first circuit board structure on the electrostatic chuck, such that the lower surface of the glass film faces Forming a third circuit layer on the lower surface of the glass film, such that the third circuit layer is electrically connected to the first conductive vias; forming a second polymer layer on the third circuit layer, a second polymer layer covering a surface of the third circuit layer and a lower surface of the glass film; forming a plurality of third via holes in the second polymer layer, wherein the third via hole and the third circuit layer are electrically And forming a fourth circuit layer on the second polymer layer, such that the fourth circuit layer is electrically connected to the third conductive vias; and removing the electrostatic chuck. A circuit board structure obtained by the manufacturing method of the circuit board structure according to any one of claims 1 to 9, the circuit board structure comprising: a glass film; a plurality of first via holes located at a first circuit layer on the glass film, wherein the first circuit layer is electrically connected to the first via holes; a first polymer layer is located on the first circuit layer; The second via holes are located in the first polymer layer, wherein the second via holes are electrically connected to the first circuit layer; and a second circuit layer is located on the first polymer layer, wherein the The second circuit layer is electrically connected to the second conductive vias.