TW201742246A - Power MOSFET - Google Patents
Power MOSFET Download PDFInfo
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- TW201742246A TW201742246A TW105115306A TW105115306A TW201742246A TW 201742246 A TW201742246 A TW 201742246A TW 105115306 A TW105115306 A TW 105115306A TW 105115306 A TW105115306 A TW 105115306A TW 201742246 A TW201742246 A TW 201742246A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000005669 field effect Effects 0.000 claims description 44
- 239000000463 material Substances 0.000 claims description 15
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 239000002994 raw material Substances 0.000 claims description 4
- WJMXTYZCTXTFJM-UHFFFAOYSA-N 1,1,1,2-tetraethoxydecane Chemical compound C(C)OC(C(OCC)(OCC)OCC)CCCCCCCC WJMXTYZCTXTFJM-UHFFFAOYSA-N 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 128
- 238000005229 chemical vapour deposition Methods 0.000 description 40
- 238000000034 method Methods 0.000 description 18
- 238000005530 etching Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/435—Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
Abstract
Description
本發明是有關於一種金氧半導體場效電晶體技術，且特別是有關於一種功率金氧半導體場效電晶體。This invention relates to a MOS field effect transistor technology, and more particularly to a power MOS field effect transistor.
斷閘極式功率金氧半導體場效電晶體(split-gate power MOSFET)也可稱為遮蔽閘極式功率金氧半導體場效電晶體(shielded-gate power MOSFET)，其結構是將溝渠式金氧半場效電晶體內的閘極結構，以多晶矽間介電層(inter-poly-dielectric，IPD)隔開，而分為兩個電位。位於上方的閘極稱用於金氧半場效電晶體的通道(channel)形成，位於下方的閘極則會以金屬內連線電性耦合至源極(source)電位，用於截止(blocking)操作下二維電荷平衡的生成，並藉由多晶矽間介電層來改善傳統溝渠式金氧半場效電晶體中過高的閘極至汲極電容，從而降低切換損耗。A split-gate power MOSFET can also be called a shielded gate-power MOSFET, which is constructed as a trench-type gold MOSFET. The gate structure in the oxygen half field effect transistor is separated by an inter-poly-dielectric (IPD) and is divided into two potentials. The upper gate is called the channel for the gold-oxygen half-effect transistor, and the lower gate is electrically coupled to the source potential with the metal interconnect for blocking. The two-dimensional charge balance is generated under operation, and the excessive gate-to-drain capacitance in the conventional trench-type MOS field-effect transistor is improved by the polysilicon inter-turn dielectric layer, thereby reducing switching loss.
然而，由於在製造斷閘極式功率金氧半導體場效電晶體時所使用的熱氧化法，會造成摻雜離子的擴散，使得上述分開的兩個閘極不能有效地隔絕。進一步在斷閘極式功率金氧半導體場效電晶體進行高電壓的應用時，無法承受更高的電位。However, the thermal oxidation method used in the fabrication of the gate-power MOS field effect transistor causes diffusion of dopant ions, so that the above two separated gates cannot be effectively isolated. Further, when the gate-type power MOS field effect transistor is applied for high voltage, it cannot withstand higher potential.
本發明提供一種功率金氧半導體場效電晶體，能在高電壓場下維持功率金氧半導體場效電晶體的效能，並且使功率金氧半導體場效電晶體的製造信賴性獲得提升。The invention provides a power MOS field effect transistor capable of maintaining the performance of a power MOS field effect transistor in a high voltage field and improving the manufacturing reliability of the power MOS field effect transistor.
本發明的功率金氧半導體場效電晶體，包括基板、半導體層、第一閘極、第二閘極、熱氧化物層、第一CVD氧化物層以及閘極氧化層。半導體層形成於該基板上，且半導體層具有至少一溝渠。第一閘極位於溝渠內。第二閘極位於第一閘極上的溝渠內，其中第二閘極具有第一部分及第二部分，且第二部分位於半導體層及第一部分之間。熱氧化物層位於第一閘極與半導體層之間。第一CVD氧化物層則位於第一閘極與第二閘極之間。閘極氧化層位於第二閘極與半導體層之間。The power MOS field effect transistor of the present invention comprises a substrate, a semiconductor layer, a first gate, a second gate, a thermal oxide layer, a first CVD oxide layer, and a gate oxide layer. A semiconductor layer is formed on the substrate, and the semiconductor layer has at least one trench. The first gate is located in the trench. The second gate is located in the trench on the first gate, wherein the second gate has a first portion and a second portion, and the second portion is located between the semiconductor layer and the first portion. The thermal oxide layer is between the first gate and the semiconductor layer. The first CVD oxide layer is then between the first gate and the second gate. A gate oxide layer is between the second gate and the semiconductor layer.
在本發明的一實施例中，上述熱氧化物層還可位於第一CVD氧化物層與第一閘極之間。In an embodiment of the invention, the thermal oxide layer may also be located between the first CVD oxide layer and the first gate.
在本發明的一實施例中，上述閘極氧化層還可延伸至第一CVD氧化物層與半導體層之間以及熱氧化物層與半導體層之間。In an embodiment of the invention, the gate oxide layer may further extend between the first CVD oxide layer and the semiconductor layer and between the thermal oxide layer and the semiconductor layer.
在本發明的一實施例中，上述的功率金氧半導體場效電晶體還可包括位於第一閘極與熱氧化物層之間的第二CVD氧化物層以及位於第二CVD氧化物層與熱氧化物層之間的氮化矽層。In an embodiment of the invention, the power MOS field effect transistor may further include a second CVD oxide layer between the first gate and the thermal oxide layer and a second CVD oxide layer A layer of tantalum nitride between the thermal oxide layers.
在本發明的一實施例中，上述第二閘極的第二部分還可包括往下延伸至第一CVD氧化物層與閘極氧化層之間。In an embodiment of the invention, the second portion of the second gate may further include extending down to between the first CVD oxide layer and the gate oxide layer.
在本發明的一實施例中，上述的第二閘極中的第二部分還可覆蓋在上述第一部分上。In an embodiment of the invention, the second portion of the second gate may also cover the first portion.
在本發明的一實施例中，上述的第一閘極的材料包括金屬、多晶矽、非晶矽或上述之組合。In an embodiment of the invention, the material of the first gate includes metal, polysilicon, amorphous germanium or a combination thereof.
在本發明的一實施例中，上述的第二閘極的材料包括金屬、多晶矽、非晶矽或上述之組合。In an embodiment of the invention, the material of the second gate includes metal, polysilicon, amorphous germanium or a combination thereof.
在本發明的一實施例中，上述的第一部分的材料不同於上述的第二部分的材料。In an embodiment of the invention, the material of the first portion is different from the material of the second portion described above.
在本發明的一實施例中，上述的第一與第二CVD氧化物層各自獨立地包括高溫化學氣相沈積氧化物(HTO)層或是以四乙氧基矽烷(TEOS)為原料所形成的。In an embodiment of the invention, the first and second CVD oxide layers each independently comprise a high temperature chemical vapor deposited oxide (HTO) layer or are formed by using tetraethoxy decane (TEOS) as a raw material. of.
在本發明的一實施例中，上述的第一閘極可具有圓角。In an embodiment of the invention, the first gate may have rounded corners.
基於上述，本發明的功率金氧半導體場效電晶體藉由CVD氧化物層作為隔開第一與第二閘極的結構層，所以能在高操作電壓下有效防止漏電的情形發生此外，本發明的功率金氧半導體場效電晶體之第二閘極具有第一與第二部分，因此能藉由不同步形成的第一部分與第二部分來增加製程的變化。Based on the above, the power MOS field effect transistor of the present invention can effectively prevent leakage current at a high operating voltage by using a CVD oxide layer as a structural layer separating the first and second gates. The second gate of the inventive power MOS field effect transistor has first and second portions, so that variations in the process can be increased by the first portion and the second portion that are not formed synchronously.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
以下實施例中所附的圖式是為了能更完整地描述發明概念的示範實施例，但是，仍可使用許多不同的形式來實施本發明，且其不應該被視為受限於所記載的實施例。在圖式中，為了清楚起見，膜層、區域及/或結構元件的相對厚度及位置可能縮小或放大。此外，本文使用「第一」、「第二」等來描述不同的區域、膜層及/或區塊，但是這樣的用語僅用於區別一區域、膜層或區塊與另一區域、膜層或區塊。因此，以下所討論之第一區域、膜層或區塊可以被稱為第二區域、膜層或區塊而不違背實施例的教示。The drawings in the following embodiments are intended to provide a more complete description of the exemplary embodiments of the present invention, but the invention may be practiced in many different forms and should not be construed as being limited Example. In the drawings, the relative thickness and position of layers, regions, and/or structural elements may be reduced or exaggerated for clarity. In addition, "first", "second", etc. are used herein to describe different regions, layers, and/or blocks, but such terms are only used to distinguish one region, layer or block from another region, film. Layer or block. Thus, the first regions, layers or blocks discussed below may be referred to as the second regions, layers or blocks without departing from the teachings of the embodiments.
圖1是依照本發明的第一實施例的一種功率金氧半導體場效電晶體的剖面示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a power MOS field effect transistor in accordance with a first embodiment of the present invention.
請參照圖1，本實施例的功率金氧半導體場效電晶體10包括基板100、具有溝渠102a的半導體層102、第一閘極104、第二閘極106、熱氧化物層108a、閘極氧化層108b以及第一CVD氧化物層110。其中，半導體層102形成於基板100上，半導體層102例如是摻雜的矽層或摻雜磊晶層。而第一閘極104是位於溝渠102a內。在第一實施例中，第一閘極104具有圓角104a；也就是說，第一閘極104的邊角是圓的而不是具有突出的尖端結構(fangs)，因此可以藉此降低輸入電容(例如：閘極-源極電容(Cgs ))，或是減少產生反向漏電流(例如：閘極漏電流(Igss ))，可以使得功率金氧半導體場效電晶體10的信賴性獲得提升。Referring to FIG. 1, the power MOS field effect transistor 10 of the present embodiment includes a substrate 100, a semiconductor layer 102 having a trench 102a, a first gate 104, a second gate 106, a thermal oxide layer 108a, and a gate. The oxide layer 108b and the first CVD oxide layer 110. The semiconductor layer 102 is formed on the substrate 100, and the semiconductor layer 102 is, for example, a doped germanium layer or a doped epitaxial layer. The first gate 104 is located within the trench 102a. In the first embodiment, the first gate 104 has rounded corners 104a; that is, the corners of the first gate 104 are round rather than having protruding tip structures, thereby reducing input capacitance (eg, gate-source capacitance ( Cgs )), or reducing the generation of reverse leakage current (eg, gate leakage current ( Igs )), which can make the reliability of power MOS field effect transistor 10 Get promoted.
請繼續參照圖1，第二閘極106則位於第一閘極104上的溝渠102a內，其中第二閘極106具有第一部分106a及第二部分106b，且第二部分106b位於半導體層102及第一部分106a之間。在本實施例中，第一閘極104及的第二閘極106的材料例如各自獨立為金屬、多晶矽、非晶矽或上述之組合，且其形成的方法包括化學氣相沉積(Chemical Vapor Deposition)、物理氣相沉積(Physical vapor deposition)或其他適當的成膜製程。此外，在本實施例中，第二閘極106的第一部分106a與第二部分106b可以是不同時形成的，因此，第一部分106a的材料可不同於第二部分106b的材料。再者，在製作功率金氧半導體場效電晶體10期間，第二閘極106的第一部分106a可以作為蝕刻製程中保護第一CVD氧化物層110的保護層，因此第一部分106a較佳是具有比氧化物低的蝕刻速率(etching rate)的材料，以保護位於第一閘極104與第二閘極106之間的第一CVD氧化物層110，所以第二閘極106的第一部分106a除了一般可作為閘極的金屬、多晶矽、非晶矽等導電材料之外，也可選用具有比氧化物低的蝕刻速率的非導電材料，如氮化矽等。同時，第二閘極106之第二部分106b是位於第一部分106a的側壁並與其直接接觸，因此第二部分106b除了可以修補第一部分106a在作為蝕刻製程期間的保護層時，其側面所造成的缺陷，還能與第一部分106a形成完整的第二閘極106。Referring to FIG. 1 , the second gate 106 is located in the trench 102 a on the first gate 104 , wherein the second gate 106 has a first portion 106 a and a second portion 106 b , and the second portion 106 b is located on the semiconductor layer 102 . Between the first part 106a. In this embodiment, the materials of the first gate 104 and the second gate 106 are, for example, each independently metal, polysilicon, amorphous germanium or a combination thereof, and the method of forming the method includes chemical vapor deposition (Chemical Vapor Deposition). ), physical vapor deposition or other suitable film forming process. Further, in the present embodiment, the first portion 106a and the second portion 106b of the second gate 106 may not be formed at the same time, and therefore, the material of the first portion 106a may be different from the material of the second portion 106b. Moreover, during the fabrication of the power MOS field effect transistor 10, the first portion 106a of the second gate 106 can serve as a protective layer for protecting the first CVD oxide layer 110 during the etching process, and thus the first portion 106a preferably has a material having a lower etching rate than the oxide to protect the first CVD oxide layer 110 between the first gate 104 and the second gate 106, so that the first portion 106a of the second gate 106 is Generally, it can be used as a conductive material such as a gate metal, a polysilicon or an amorphous germanium, and a non-conductive material having a lower etching rate than an oxide such as tantalum nitride or the like can also be used. At the same time, the second portion 106b of the second gate 106 is located on the sidewall of the first portion 106a and is in direct contact therewith, so that the second portion 106b can be repaired by the side of the first portion 106a in addition to the protective layer during the etching process. The defect can also form a complete second gate 106 with the first portion 106a.
請繼續參照圖1，熱氧化物層108a位於第一閘極104與半導體層102之間。在本實施例中，使用熱氧化法製作的熱氧化物層108a在製作時例如採取較高的製程溫度(900℃~1200℃)，因此所形成的二氧化矽具有較高的緻密性，可以作為製程前期(即，在形成第一閘極104與第二閘極106之前)的表面保護。第一CVD氧化物層110則位在第一閘極104與第二閘極106之間，且熱氧化物層108a還可位於第一CVD氧化物層110與第一閘極104之間，。在本實施例中，第一CVD氧化物層110是指利用化學氣相沉積(CVD)形成的氧化物，例如高溫化學氣相沈積氧化物(high temperature CVD oxide，HTO)層或是一層以四乙氧基矽烷(tetraethyl orthosilicate，TEOS)為原料所形成的膜層，且其形成的方法例如低壓化學氣相沉積。由於第一CVD氧化物層110的氧化物品質比熱氧化法所形成的氧化物層優異，所以第一CVD氧化物層110可以有效地隔絕第一閘極104與第二閘極106，使得本實施例之功率金氧半導體場效電晶體10能承受更高的電位而不漏電。Referring to FIG. 1 , the thermal oxide layer 108 a is located between the first gate 104 and the semiconductor layer 102 . In the present embodiment, the thermal oxide layer 108a produced by the thermal oxidation method is, for example, subjected to a high process temperature (900 ° C to 1200 ° C) during fabrication, so that the formed cerium oxide has high density and can be Surface protection as a pre-process (i.e., prior to forming the first gate 104 and the second gate 106). The first CVD oxide layer 110 is between the first gate 104 and the second gate 106, and the thermal oxide layer 108a may also be located between the first CVD oxide layer 110 and the first gate 104. In the present embodiment, the first CVD oxide layer 110 refers to an oxide formed by chemical vapor deposition (CVD), such as a high temperature CVD oxide (HTO) layer or a layer of four. A film formed of a raw material of tetraethyl orthosilicate (TEOS) and formed by a method such as low pressure chemical vapor deposition. Since the oxide quality of the first CVD oxide layer 110 is superior to that of the oxide layer formed by the thermal oxidation method, the first CVD oxide layer 110 can effectively isolate the first gate 104 and the second gate 106, so that the present embodiment For example, the power MOS field effect transistor 10 can withstand higher potentials without leakage.
請繼續參照圖1，閘極氧化層108b位於第二閘極106與半導體層102之間，且在半導體層102內通常具有源極區112與井區114，所以在圖1顯示閘極氧化層108b大部分是在第二閘極106與井區114之間。至於汲極區(未繪出)通常配置在基板100未形成半導體層102的那一面。在第一實施例中，因為閘極氧化層108b可藉由製程設計而與熱氧化物層108a同時形成，之後再經由其他步驟減薄，所以基本上閘極氧化層108b與熱氧化物層108a可視為同一層，不過閘極氧化層108b的厚度t1通常比熱氧化物層108a的厚度t2要薄，且閘極氧化層108b可延伸至第一CVD氧化物層110與半導體層102之間。但本發明並不限於此，上述閘極氧化層108b的材料也可以不同於熱氧化物層108a的材料。例如，閘極氧化層108b也可與第一CVD氧化物層110使用相同方法製作。另外，在第二閘極106上可依照設計，配置絕緣層118之類的膜層。Referring to FIG. 1 , the gate oxide layer 108b is located between the second gate 106 and the semiconductor layer 102, and has a source region 112 and a well region 114 in the semiconductor layer 102. Therefore, the gate oxide layer is shown in FIG. Most of 108b is between the second gate 106 and the well region 114. The drain region (not shown) is usually disposed on the side of the substrate 100 where the semiconductor layer 102 is not formed. In the first embodiment, since the gate oxide layer 108b can be formed simultaneously with the thermal oxide layer 108a by a process design, and then thinned through other steps, the gate oxide layer 108b and the thermal oxide layer 108a are substantially The same layer can be considered, but the thickness t1 of the gate oxide layer 108b is generally thinner than the thickness t2 of the thermal oxide layer 108a, and the gate oxide layer 108b can extend between the first CVD oxide layer 110 and the semiconductor layer 102. However, the present invention is not limited thereto, and the material of the gate oxide layer 108b may be different from the material of the thermal oxide layer 108a. For example, the gate oxide layer 108b can also be fabricated in the same manner as the first CVD oxide layer 110. In addition, a film layer such as the insulating layer 118 may be disposed on the second gate 106 in accordance with the design.
圖2是依照本發明的第二實施例的一種功率金氧半導體場效電晶體的剖面示意圖，其中使用與第一實施例相同的元件符號來表示相同或近似的部份，並且其相關描述在此不予贅述。Figure 2 is a cross-sectional view showing a power MOS field effect transistor according to a second embodiment of the present invention, wherein the same or similar parts are denoted by the same reference numerals as in the first embodiment, and the related description is This will not be repeated.
請參照圖2，第二實施例之功率金氧半導體場效電晶體20的第二閘極200中的第二部分200b不但位於半導體層102及第一部分200a之間，還覆蓋在第一部分200a上；意即，第二部分200b包覆整個第一部分200a，因此，第二部分200b除了可以修補第一部分200a在蝕刻製程期間所受到的損害還能填滿第一部分200a的縫隙(gap filling)，即使第一部分200a不是導電材料，也因為第二部分200b配置於主動區內，所以第二閘極200能順利運作。Referring to FIG. 2, the second portion 200b of the second gate 200 of the power MOS field effect transistor 20 of the second embodiment is not only located between the semiconductor layer 102 and the first portion 200a but also over the first portion 200a. That is, the second portion 200b covers the entire first portion 200a, and therefore, the second portion 200b can fill the gap filling of the first portion 200a, in addition to repairing the damage suffered by the first portion 200a during the etching process, even if The first portion 200a is not a conductive material, and since the second portion 200b is disposed in the active region, the second gate 200 can operate smoothly.
圖3是依照本發明的第三實施例的一種功率金氧半導體場效電晶體的剖面示意圖。3 is a schematic cross-sectional view of a power MOS field effect transistor in accordance with a third embodiment of the present invention.
請參照圖3，本實施例的功率金氧半導體場效電晶體30包括基板300、具有溝渠302a的半導體層302、第一閘極304、第二閘極306、熱氧化物層308a、閘極氧化層308b、氮化矽層312、第一CVD氧化物層314以及第二CVD氧化物層310，其中半導體層302形成於基板300上，第一閘極304是位於溝渠302a內，第二閘極306則位於第一閘極304上的溝渠302a內，且第二閘極306具有第一部分306a和介於半導體層302及第一部分306a之間的第二部分306b。至於上述半導體層302、第一閘極304與第二閘極306的詳細材料或構造，可參照第一實施例的相同構件，故不再贅述。Referring to FIG. 3, the power MOS field effect transistor 30 of the present embodiment includes a substrate 300, a semiconductor layer 302 having a trench 302a, a first gate 304, a second gate 306, a thermal oxide layer 308a, and a gate. The oxide layer 308b, the tantalum nitride layer 312, the first CVD oxide layer 314, and the second CVD oxide layer 310, wherein the semiconductor layer 302 is formed on the substrate 300, the first gate 304 is located in the trench 302a, and the second gate The pole 306 is located in the trench 302a on the first gate 304, and the second gate 306 has a first portion 306a and a second portion 306b interposed between the semiconductor layer 302 and the first portion 306a. As for the detailed material or configuration of the semiconductor layer 302, the first gate 304 and the second gate 306, the same components of the first embodiment can be referred to, and thus will not be described again.
請繼續參照圖3，本實施例的功率金氧半導體場效電晶體30與第一實施例之間的差異在於具有第二CVD氧化物層310和氮化矽層312，其中第二CVD氧化物層310位於第一閘極304與熱氧化物層308a之間，而氮化矽層312是位於第二CVD氧化物層310與熱氧化物層308a之間。上述第二CVD氧化物層310與第一CVD氧化物層314都是指利用化學氣相沉積(CVD)形成的氧化物，且各自獨立地例如高溫化學氣相沈積氧化物(HTO)層或是一層以四乙氧基矽烷(TEOS)為原料所形成的膜層，且其形成的方法例如低壓化學氣相沉積。至於閘極氧化層308b除了位於第二閘極306與半導體層302之間，還延伸至第一CVD氧化物層314與半導體層302之間。而且，第二閘極306的第二部分306b還可往下延伸至第一CVD氧化物層314與閘極氧化層308b之間。在半導體層302內通常具有源極區316與井區318，至於汲極區(未繪出)通常配置在基板300未形成半導體層302的那一面。此外，如有需要，在第二閘極306上的溝渠302a內可配置絕緣層320之類的膜層。在本實施例中，上述氮化矽層312的形成的方法例如化學氣相沉積或其他適當的成膜製程。此外，氮化矽層312可以防止半導體層302或第二閘極306內的摻雜元素進一步的擴散，有效地隔絕半導體層302與第二閘極306，使得第三實施例之功率金氧半導體場效電晶體30的信賴性獲得提升。With continued reference to FIG. 3, the power MOS field effect transistor 30 of the present embodiment differs from the first embodiment in having a second CVD oxide layer 310 and a tantalum nitride layer 312, wherein the second CVD oxide Layer 310 is between first gate 304 and thermal oxide layer 308a, and tantalum nitride layer 312 is between second CVD oxide layer 310 and thermal oxide layer 308a. The second CVD oxide layer 310 and the first CVD oxide layer 314 are both oxides formed by chemical vapor deposition (CVD), and are each independently, for example, a high temperature chemical vapor deposited oxide (HTO) layer or A layer formed of tetraethoxy decane (TEOS) as a raw material, and a method of forming the same, such as low pressure chemical vapor deposition. As for the gate oxide layer 308b, between the second gate 306 and the semiconductor layer 302, it extends between the first CVD oxide layer 314 and the semiconductor layer 302. Moreover, the second portion 306b of the second gate 306 can also extend down between the first CVD oxide layer 314 and the gate oxide layer 308b. There is typically a source region 316 and a well region 318 within the semiconductor layer 302, and a drain region (not shown) is typically disposed on the side of the substrate 300 where the semiconductor layer 302 is not formed. In addition, a film layer such as an insulating layer 320 may be disposed in the trench 302a on the second gate 306, if necessary. In the present embodiment, the method of forming the above-described tantalum nitride layer 312 is, for example, chemical vapor deposition or other suitable film formation process. In addition, the tantalum nitride layer 312 can prevent further diffusion of doping elements in the semiconductor layer 302 or the second gate 306, effectively isolating the semiconductor layer 302 and the second gate 306, so that the power MOS of the third embodiment The reliability of the field effect transistor 30 is improved.
圖4是依照本發明的第四實施例的一種功率金氧半導體場效電晶體的剖面示意圖，其中使用與第三實施例相同的元件符號來表示相同或近似的部份，並且其相關描述在此不予贅述。4 is a cross-sectional view showing a power MOS field effect transistor according to a fourth embodiment of the present invention, wherein the same or similar parts are denoted by the same reference numerals as in the third embodiment, and the related description is This will not be repeated.
請參照圖4，第四實施例之功率金氧半導體場效電晶體40的第二閘極400中的第二部分400b不但位於半導體層302及第一部分400a之間，還覆蓋在第一部分400a上，所以整個第一部分400a被第二部分400b包覆。因此，第二部分400b可以修補第一部分400a在蝕刻製程期間所受到的損害以及填滿第一部分400a的縫隙(gap filling)。另一方面，假使第一部分400a不是導電材料，因為第二部分400b完整配置於主動區內，所以第二閘極400也能順利運作。Referring to FIG. 4, the second portion 400b of the second gate 400 of the power MOS field effect transistor 40 of the fourth embodiment is not only located between the semiconductor layer 302 and the first portion 400a but also over the first portion 400a. Therefore, the entire first portion 400a is covered by the second portion 400b. Therefore, the second portion 400b can repair the damage suffered by the first portion 400a during the etching process and fill the gap filling of the first portion 400a. On the other hand, if the first portion 400a is not a conductive material, since the second portion 400b is completely disposed in the active region, the second gate 400 can also operate smoothly.
綜上所述，本發明藉由在第一閘極與第二閘極之間形成CVD氧化物層，以有效地增進第一閘極與第二閘極之間的氧化物品質，所以本發明之功率金氧半導體場效電晶體能承受更高的操作電壓而不漏電，所以元件本身的信賴性可獲得提升。In summary, the present invention effectively forms the CVD oxide layer between the first gate and the second gate to effectively improve the oxide quality between the first gate and the second gate. The power MOS field effect transistor can withstand higher operating voltage without leakage, so the reliability of the component itself can be improved.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10、20、30、40‧‧‧功率金氧半導體場效電晶體
100、300‧‧‧基板
102、302‧‧‧半導體層
102a、302a‧‧‧溝渠
104、304‧‧‧第一閘極
104a‧‧‧圓角
106、200、306、400‧‧‧第二閘極
106a、200a、306a、400a‧‧‧第一部分
106b、200b、306b、400b‧‧‧第二部分
108a、308a‧‧‧熱氧化物層
108b、308b‧‧‧閘極氧化層
110、314‧‧‧第一CVD氧化物層
112、316‧‧‧源極區
114、318‧‧‧井區
116、320‧‧‧絕緣層
310‧‧‧第二CVD氧化物層
312‧‧‧氮化矽層
t1、t2‧‧‧厚度10, 20, 30, 40‧‧‧ power MOS field effect transistor
100, 300‧‧‧ substrate
102, 302‧‧‧ semiconductor layer
102a, 302a‧‧‧ Ditch
104, 304‧‧‧ first gate
104a‧‧‧ fillet
106, 200, 306, 400‧‧‧ second gate
106a, 200a, 306a, 400a‧‧‧ first part
106b, 200b, 306b, 400b‧‧‧ second part
108a, 308a‧‧‧ Thermal oxide layer
108b, 308b‧‧‧ gate oxide layer
110, 314‧‧‧First CVD oxide layer
112, 316‧‧‧ source area
114, 318‧‧‧ Well Area
116, 320‧‧‧Insulation
310‧‧‧Second CVD oxide layer
312‧‧‧矽 nitride layer
T1, t2‧‧‧ thickness
圖1是依照本發明的第一實施例的一種功率金氧半導體場效電晶體的剖面示意圖。 圖2是依照本發明的第二實施例的一種功率金氧半導體場效電晶體的剖面示意圖。 圖3是依照本發明的第三實施例的一種功率金氧半導體場效電晶體的剖面示意圖。 圖4是依照本發明的第四實施例的一種功率金氧半導體場效電晶體的剖面示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a power MOS field effect transistor in accordance with a first embodiment of the present invention. 2 is a schematic cross-sectional view of a power MOS field effect transistor in accordance with a second embodiment of the present invention. 3 is a schematic cross-sectional view of a power MOS field effect transistor in accordance with a third embodiment of the present invention. 4 is a cross-sectional view showing a power MOS field effect transistor in accordance with a fourth embodiment of the present invention.
10‧‧‧功率金氧半導體場效電晶體 10‧‧‧Power MOS field effect transistor
100‧‧‧基板 100‧‧‧Substrate
102‧‧‧半導體層 102‧‧‧Semiconductor layer
102a‧‧‧溝渠 102a‧‧‧ Ditch
104‧‧‧第一閘極 104‧‧‧First Gate
104a‧‧‧圓角 104a‧‧‧ fillet
106‧‧‧第二閘極 106‧‧‧second gate
106a‧‧‧第一部分 106a‧‧‧Part 1
106b‧‧‧第二部分 106b‧‧‧Part II
108a‧‧‧熱氧化物層 108a‧‧‧Thermal oxide layer
108b‧‧‧閘極氧化層 108b‧‧‧ gate oxide layer
110‧‧‧第一CVD氧化物層 110‧‧‧First CVD oxide layer
112‧‧‧源極區 112‧‧‧ source area
114‧‧‧井區 114‧‧‧ Well Area
116‧‧‧絕緣層 116‧‧‧Insulation
t1、t2‧‧‧厚度 T1, t2‧‧‧ thickness
Claims (11)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105115306A TWI577010B (en) | 2016-05-18 | 2016-05-18 | Power mosfet |
| US15/182,586 US9941357B2 (en) | 2016-05-18 | 2016-06-14 | Power MOSFET |
| CN201610421831.5A CN107403838B (en) | 2016-05-18 | 2016-06-15 | Power metal oxide semiconductor field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105115306A TWI577010B (en) | 2016-05-18 | 2016-05-18 | Power mosfet |
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| Publication Number | Publication Date |
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| TWI577010B TWI577010B (en) | 2017-04-01 |
| TW201742246A true TW201742246A (en) | 2017-12-01 |
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| TW105115306A TWI577010B (en) | 2016-05-18 | 2016-05-18 | Power mosfet |
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| Country | Link |
|---|---|
| US (1) | US9941357B2 (en) |
| CN (1) | CN107403838B (en) |
| TW (1) | TWI577010B (en) |
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| TWI737855B (en) * | 2017-11-15 | 2021-09-01 | 力智電子股份有限公司 | Power transistor and manufacturing method thereof |
| CN109888003A (en) * | 2019-03-12 | 2019-06-14 | 电子科技大学 | A kind of power MOS (Metal Oxide Semiconductor) device of separate gate enhancing |
| CN113539833B (en) * | 2021-07-23 | 2023-04-25 | 电子科技大学 | Manufacturing method of split gate power MOSFET device |
| WO2023188756A1 (en) * | 2022-03-28 | 2023-10-05 | ローム株式会社 | Semiconductor device |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7638841B2 (en) | 2003-05-20 | 2009-12-29 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
| JP2006128506A (en) * | 2004-10-29 | 2006-05-18 | Sharp Corp | Trench type mosfet and manufacturing method thereof |
| US7453119B2 (en) | 2005-02-11 | 2008-11-18 | Alphs & Omega Semiconductor, Ltd. | Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact |
| TWI400757B (en) | 2005-06-29 | 2013-07-01 | Fairchild Semiconductor | Methods for forming shielded gate field effect transistors |
| US7385248B2 (en) | 2005-08-09 | 2008-06-10 | Fairchild Semiconductor Corporation | Shielded gate field effect transistor with improved inter-poly dielectric |
| US8058687B2 (en) | 2007-01-30 | 2011-11-15 | Alpha & Omega Semiconductor, Ltd. | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET |
| US8497549B2 (en) * | 2007-08-21 | 2013-07-30 | Fairchild Semiconductor Corporation | Method and structure for shielded gate trench FET |
| US7833862B2 (en) * | 2008-03-03 | 2010-11-16 | Infineon Technologies Austria Ag | Semiconductor device and method for forming same |
| US9419129B2 (en) | 2009-10-21 | 2016-08-16 | Vishay-Siliconix | Split gate semiconductor device with curved gate oxide profile |
| US8610205B2 (en) | 2011-03-16 | 2013-12-17 | Fairchild Semiconductor Corporation | Inter-poly dielectric in a shielded gate MOSFET device |
| US8642425B2 (en) * | 2012-05-29 | 2014-02-04 | Semiconductor Components Industries, Llc | Method of making an insulated gate semiconductor device and structure |
| US8896060B2 (en) | 2012-06-01 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Trench power MOSFET |
| KR20150090674A (en) * | 2014-01-29 | 2015-08-06 | 에스케이하이닉스 주식회사 | Transistor having dual work function bruied gate electrode, method for manufacturing the same and electronic device having the same |
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2016
- 2016-05-18 TW TW105115306A patent/TWI577010B/en active
- 2016-06-14 US US15/182,586 patent/US9941357B2/en active Active
- 2016-06-15 CN CN201610421831.5A patent/CN107403838B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20170338309A1 (en) | 2017-11-23 |
| CN107403838A (en) | 2017-11-28 |
| TWI577010B (en) | 2017-04-01 |
| CN107403838B (en) | 2021-04-20 |
| US9941357B2 (en) | 2018-04-10 |
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