TW201737068A - 在基於處理器系統中基於負載路徑歷史使用位址預測表以提供負載位址預測 - Google Patents

在基於處理器系統中基於負載路徑歷史使用位址預測表以提供負載位址預測 Download PDF

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Publication number
TW201737068A
TW201737068A TW106106784A TW106106784A TW201737068A TW 201737068 A TW201737068 A TW 201737068A TW 106106784 A TW106106784 A TW 106106784A TW 106106784 A TW106106784 A TW 106106784A TW 201737068 A TW201737068 A TW 201737068A
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Taiwan
Prior art keywords
load
address
prediction
address prediction
processor
Prior art date
Application number
TW106106784A
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English (en)
Chinese (zh)
Inventor
雪克 瑞米 默漢麥德 艾爾
瑞谷藍 達莫達倫
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高通公司
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Publication of TW201737068A publication Critical patent/TW201737068A/zh

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3848—Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW106106784A 2016-03-31 2017-03-02 在基於處理器系統中基於負載路徑歷史使用位址預測表以提供負載位址預測 TW201737068A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/087,069 US11709679B2 (en) 2016-03-31 2016-03-31 Providing load address predictions using address prediction tables based on load path history in processor-based systems

Publications (1)

Publication Number Publication Date
TW201737068A true TW201737068A (zh) 2017-10-16

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Family Applications (1)

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TW106106784A TW201737068A (zh) 2016-03-31 2017-03-02 在基於處理器系統中基於負載路徑歷史使用位址預測表以提供負載位址預測

Country Status (9)

Country Link
US (1) US11709679B2 (enExample)
EP (1) EP3436930B1 (enExample)
JP (1) JP6744423B2 (enExample)
KR (1) KR20180127379A (enExample)
CN (1) CN108780398B (enExample)
BR (1) BR112018069818A2 (enExample)
CA (1) CA3016029A1 (enExample)
TW (1) TW201737068A (enExample)
WO (1) WO2017172232A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI768547B (zh) * 2020-11-18 2022-06-21 瑞昱半導體股份有限公司 管線式電腦系統與指令處理方法

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10936713B2 (en) 2015-12-17 2021-03-02 The Charles Stark Draper Laboratory, Inc. Techniques for metadata processing
US10235176B2 (en) 2015-12-17 2019-03-19 The Charles Stark Draper Laboratory, Inc. Techniques for metadata processing
US11281586B2 (en) * 2017-05-09 2022-03-22 Andes Technology Corporation Processor and way prediction method thereof
US10645133B2 (en) 2017-07-12 2020-05-05 Loon Llc Method and system for delivering content over transient access networks
US10503648B2 (en) * 2017-12-12 2019-12-10 Advanced Micro Devices, Inc. Cache to cache data transfer acceleration techniques
CN112041837B (zh) 2018-02-02 2024-12-03 查尔斯斯塔克德雷珀实验室公司 处理系统和处理指令的方法
WO2019152795A1 (en) 2018-02-02 2019-08-08 Dover Microsystems, Inc. Systems and methods for transforming instructions for metadata processing
EP3746921B1 (en) 2018-02-02 2023-12-27 Dover Microsystems, Inc. Systems and methods for policy linking and/or loading for secure initialization
EP3788488A1 (en) 2018-04-30 2021-03-10 Dover Microsystems, Inc. Systems and methods for checking safety properties
US10838731B2 (en) * 2018-09-19 2020-11-17 Qualcomm Incorporated Branch prediction based on load-path history
WO2020097179A1 (en) 2018-11-06 2020-05-14 Dover Microsystems, Inc. Systems and methods for stalling host processor
US12124566B2 (en) 2018-11-12 2024-10-22 Dover Microsystems, Inc. Systems and methods for metadata encoding
WO2020132012A1 (en) 2018-12-18 2020-06-25 Dover Microsystems, Inc. Systems and methods for data lifecycle protection
WO2020150351A1 (en) 2019-01-18 2020-07-23 Dover Microsystems, Inc. Systems and methods for metadata classification
US10929142B2 (en) * 2019-03-20 2021-02-23 International Business Machines Corporation Making precise operand-store-compare predictions to avoid false dependencies
US11243774B2 (en) 2019-03-20 2022-02-08 International Business Machines Corporation Dynamic selection of OSC hazard avoidance mechanism
US11829763B2 (en) 2019-08-13 2023-11-28 Apple Inc. Early load execution via constant address and stride prediction
US10896041B1 (en) * 2019-09-25 2021-01-19 Microsoft Technology Licensing, Llc Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices
WO2021076871A1 (en) 2019-10-18 2021-04-22 Dover Microsystems, Inc. Systems and methods for updating metadata
US11204771B2 (en) * 2019-10-24 2021-12-21 Arm Limited Methods and apparatus for handling processor load instructions
US11194575B2 (en) * 2019-11-07 2021-12-07 International Business Machines Corporation Instruction address based data prediction and prefetching
US12253944B2 (en) 2020-03-03 2025-03-18 Dover Microsystems, Inc. Systems and methods for caching metadata
GB2592661B (en) 2020-03-05 2022-05-11 Advanced Risc Mach Ltd An apparatus and method for performing branch prediction
US12124576B2 (en) 2020-12-23 2024-10-22 Dover Microsystems, Inc. Systems and methods for policy violation processing
US11630670B2 (en) 2021-07-21 2023-04-18 Apple Inc. Multi-table signature prefetch
US12045170B2 (en) * 2021-12-08 2024-07-23 Arm Limited Replacement control for candidate producer-consumer relationships trained for prefetch generation
US12067398B1 (en) 2022-04-29 2024-08-20 Apple Inc. Shared learning table for load value prediction and load address prediction
WO2025050307A1 (en) * 2023-09-06 2025-03-13 Huawei Technologies Co., Ltd. Efficient load value prediction based on program context and misprediction control mechanism for pipelined microprocessor designs
US12487825B2 (en) 2024-02-23 2025-12-02 International Business Machines Corporation Controlling speculative actions based on a hit/miss predictor
US12288075B1 (en) 2024-02-23 2025-04-29 International Business Machines Corporation Instruction execution scheduling using a hit/miss predictor
US20250335198A1 (en) * 2024-04-29 2025-10-30 International Business Machines Corporation Low power late-selected caches using a set-prediction history

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287467A (en) 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US6108775A (en) 1996-12-30 2000-08-22 Texas Instruments Incorporated Dynamically loadable pattern history tables in a multi-task microprocessor
JPH10260834A (ja) 1997-03-18 1998-09-29 Fujitsu Ltd ロードアドレス予測装置および並列処理装置およびそのロードアドレス予測方法
US5941981A (en) 1997-11-03 1999-08-24 Advanced Micro Devices, Inc. System for using a data history table to select among multiple data prefetch algorithms
US6230260B1 (en) 1998-09-01 2001-05-08 International Business Machines Corporation Circuit arrangement and method of speculative instruction execution utilizing instruction history caching
US6438673B1 (en) 1999-12-30 2002-08-20 Intel Corporation Correlated address prediction
DE10121792C2 (de) * 2000-05-26 2003-09-25 Ibm Universelle Ladeadresse/Wertevorhersageschema
US6868491B1 (en) 2000-06-22 2005-03-15 International Business Machines Corporation Processor and method of executing load instructions out-of-order having reduced hazard penalty
US7062638B2 (en) 2000-12-29 2006-06-13 Intel Corporation Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the stores
US6907520B2 (en) 2001-01-11 2005-06-14 Sun Microsystems, Inc. Threshold-based load address prediction and new thread identification in a multithreaded microprocessor
JP3594081B2 (ja) 2001-01-23 2004-11-24 日本電気株式会社 情報処理装置
JP4030314B2 (ja) 2002-01-29 2008-01-09 富士通株式会社 演算処理装置
US6976147B1 (en) 2003-01-21 2005-12-13 Advanced Micro Devices, Inc. Stride-based prefetch mechanism using a prediction confidence value
US7430650B1 (en) 2004-06-17 2008-09-30 Richard Ross Generating a set of pre-fetch address candidates based on popular sets of address and data offset counters
US7917731B2 (en) 2006-08-02 2011-03-29 Qualcomm Incorporated Method and apparatus for prefetching non-sequential instruction addresses
US7856548B1 (en) * 2006-12-26 2010-12-21 Oracle America, Inc. Prediction of data values read from memory by a microprocessor using a dynamic confidence threshold
US7640420B2 (en) 2007-04-02 2009-12-29 Intel Corporation Pre-fetch apparatus
US8392651B2 (en) * 2008-08-20 2013-03-05 Mips Technologies, Inc. Data cache way prediction
US8533438B2 (en) 2009-08-12 2013-09-10 Via Technologies, Inc. Store-to-load forwarding based on load/store address computation source information comparisons
US9189432B2 (en) * 2010-11-15 2015-11-17 Arm Limited Apparatus and method for predicting target storage unit
US9146739B2 (en) 2012-06-14 2015-09-29 International Business Machines Corporation Branch prediction preloading
US20140173294A1 (en) 2012-12-14 2014-06-19 Broadcom Corporation Techniques for emulating an eeprom device
US9367468B2 (en) 2013-01-15 2016-06-14 Qualcomm Incorporated Data cache way prediction
GB2506462B (en) 2013-03-13 2014-08-13 Imagination Tech Ltd Indirect branch prediction
US9244827B2 (en) 2013-09-25 2016-01-26 Intel Corporation Store address prediction for memory disambiguation in a processing device
US9606805B1 (en) 2015-10-19 2017-03-28 International Business Machines Corporation Accuracy of operand store compare prediction using confidence counter
US10437595B1 (en) 2016-03-15 2019-10-08 Apple Inc. Load/store dependency predictor optimization for replayed loads
US10353819B2 (en) * 2016-06-24 2019-07-16 Qualcomm Incorporated Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in a processor-based system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI768547B (zh) * 2020-11-18 2022-06-21 瑞昱半導體股份有限公司 管線式電腦系統與指令處理方法

Also Published As

Publication number Publication date
US20170286119A1 (en) 2017-10-05
CN108780398B (zh) 2022-06-07
EP3436930A1 (en) 2019-02-06
BR112018069818A2 (pt) 2019-01-29
CA3016029A1 (en) 2017-10-05
CN108780398A (zh) 2018-11-09
JP6744423B2 (ja) 2020-08-19
US11709679B2 (en) 2023-07-25
KR20180127379A (ko) 2018-11-28
EP3436930B1 (en) 2020-05-20
WO2017172232A1 (en) 2017-10-05
JP2019514110A (ja) 2019-05-30

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