TW201735358A - Semiconductor element and electric apparatus using same - Google Patents

Abstract

A semiconductor element 1 is characterized by comprising: a pair of an ohmic electrode 20 and a Schottky electrode 10 separated from each other; and a semiconductor layer 30 in contact with the ohmic electrode 20 and the Schottky electrode 10, wherein formula (I) is satisfied (in the formula, n represents the carrier concentration (cm-3) of the semiconductor layer, [epsilon] represents the dielectric constant (F/cm) of the semiconductor layer, Ve represents the forward effective voltage (V) between the ohmic electrode and the Schottky electrode, q represents the elementary charge (C), L represents the distance (cm) between the ohmic electrode and the Schottky electrode).

Description

Semiconductor component and electrical machine using the same

The present invention relates to a semiconductor device and a Schottky barrier diode, junction transistor, electronic circuit, and electrical machine using the same.

As a power semiconductor material that realizes a large current and a low power consumption, a new material such as SiC or GaN is exemplified as Si. Moreover, gallium oxide and diamond have also attracted attention as next-generation materials. On the other hand, since these materials are basically used in a single crystal form, there is a disadvantage that it is difficult to grow a single crystal on a heterogeneous substrate, and the selection of the substrate is limited. Regarding SiC, a preferred crystal structure as a power semiconductor is 4H-SiC, and the dielectric breakdown electric field is 3 MV/cm or more. However, since the mismatch of the crystal lattice is large, it is difficult to epitaxially grow the single crystal having a small defect on Si. In the case of 3C-SiC, epitaxial growth can be performed by performing microfabrication on the Si wafer or Si (211) plane, but the band gap is narrowed, so the dielectric breakdown electric field is limited to 1.2 MV/cm. Further, GaN also has an insulation breakdown electric field of 3 MV/cm or more similarly to 4H-SiC, and attempts to carry out crystal growth on Si in order to achieve mass production. However, although it is not as good as SiC in terms of lattice mismatch with Si, if the buffer layer such as AIN is not interposed, crystal growth is difficult, and there is a problem in mass productivity. Therefore, research is being conducted on a power device that is compatible with a hetero-substrate using a polycrystalline or amorphous oxide semiconductor as in Patent Document 1. In general, as disclosed in Non-Patent Document 1, in a unipolar power device, in order to obtain the lowest on-resistance, the relationship of the following equation holds, and if the withstand voltage design and the type of semiconductor material are determined, the optimum carrier concentration is determined. . However, amorphous or polycrystalline semiconductors have difficulty controlling the carrier concentration. [Number 1] (wherein, ε _s is the dielectric constant of the material, E _c is the maximum dielectric breakdown electric field, q is the basic charge, BV is the withstand voltage as a design value, and N _D is the carrier concentration). PRIOR ART DOCUMENT Patent Document Patent Document 1 :WO2015/025499A1 Non-Patent Document Non-Patent Document 1: "Fundamentals of Power Semiconductor Devices", B. Jayant Baliga, Springer Science & Business Media, 2010/04/02

It is an object of the present invention to provide a semiconductor device having high withstand voltage and low resistance without initial carrier concentration control. The present inventors have made an effort to study the problem that it is difficult to adjust the concentration of the initial carrier, and as a result, it has been found that as long as the semiconductor layer and the electrode satisfy a specific relationship, the operation is different according to the design guidelines related to the previous unipolar power device. According to the principle, an exogenous carrier can be used without depending on the carrier concentration, and a semiconductor element having high withstand voltage and low resistance can be obtained, thereby completing the present invention. According to the present invention, the following semiconductor elements and the like are provided. A semiconductor device comprising: a pair of ohmic electrodes and a Schottky electrode; and a semiconductor layer in contact with the ohmic electrode and the Schottky electrode, and satisfying the following formula (I). [Number 2] (wherein n is a carrier concentration (cm ^-3 ) of the semiconductor layer, ε is a dielectric constant (F/cm) of the semiconductor layer, and _Ve is a positive relationship between the ohmic electrode and the Schottky electrode To the effective voltage (V), q is the basic charge (C), and L is the distance (cm) between the ohmic electrode and the Schottky electrode. 2. The semiconductor device according to 1, wherein the semiconductor layer comprises Metal oxide. 3. The semiconductor device according to 2, wherein the metal oxide contains one or more elements selected from the group consisting of In, Zn, Ga, Sn, and Al. 4. The semiconductor device according to any one of 1 to 3, wherein the Schottky electrode comprises Pd, Mo, Pt, Ir, Ru, W, Cr, Re, Te, Mn, Os, Fe, One or more of Rh, Co and Ni or an oxide thereof. 5. The semiconductor device according to any one of 1 to 4, wherein the ohmic electrode comprises a metal selected from the group consisting of Ti, Mo, Ag, In, Al, W, Co, and Ni, or a compound thereof. 6. The semiconductor device according to any one of 1 to 5, wherein the semiconductor layer comprises amorphous or polycrystalline. 7. The semiconductor device according to any one of 1 to 6, wherein the semiconductor layer has a characteristic temperature of 1500 K or less. 8. The semiconductor device according to any one of 1 to 7, wherein the ohmic electrode surface is located inside the perpendicular line when the peripheral portion of the Schottky electrode is perpendicular to the ohmic electrode surface. 9. The semiconductor device according to any one of 1 to 8, characterized in that the withstand voltage is 0.5 MV/cm or more. 10. The semiconductor device according to any one of 1 to 9, wherein the semiconductor layer is interposed between the ohmic electrode and the Schottky electrode. 11. The semiconductor device according to 10, further comprising: a conductive germanium substrate, wherein the ohmic electrode or the Schottky electrode is in contact with the conductive germanium substrate. 12. The semiconductor device according to any one of 1 to 9, wherein the ohmic electrode is present on a surface of one of the semiconductor layers at a distance from the Schottky electrode. A Schottky barrier diode characterized by using the semiconductor device according to any one of 1 to 12. A junction transistor characterized by using the semiconductor element according to any one of 1 to 12. An electronic circuit characterized by using a semiconductor element according to any one of 1 to 12, such as a Schottky barrier diode of 13 or a junction transistor such as 14. 16. An electrical machine, an electronic machine, a vehicle or a power mechanism, characterized in that an electronic circuit such as 15 is used. According to the present invention, it is possible to provide a semiconductor element having high withstand voltage and low resistance without initial carrier concentration control.

The semiconductor device of the present invention has a pair of ohmic electrodes and a Schottky electrode, and a semiconductor layer that is in contact with the ohmic electrode and the Schottky electrode, and satisfies the following formula (I). [Number 3](where n is the carrier concentration of the above semiconductor layer (cm^-3 ), ε is the dielectric constant (F/cm) of the above semiconductor layer, V_e Is the forward effective voltage (V) between the ohmic electrode and the Schottky electrode, and q is the basic charge (1.602×10)^-19 C), L is the distance (cm) between the ohmic electrode and the Schottky electrode. The lower limit of n may be 0, but preferably 1 × 10¹⁰ the above. More preferably, it satisfies the following formula (I-1), and further preferably satisfies the following formula (I-2). [Number 4][Number 5]In the above formula, the carrier concentration is measured by CV (capacitance-voltage) and is calculated using the following formula (refer to APPLIED PHYSICS LETTERS, 101, 113505 (2012)). [Number 6]A: area of the portion where the Schottky electrode and the ohmic electrode are repeated (cm² C: The measured capacitance value (F) ε_s : Relative dielectric constant (-) ε₀ : dielectric constant of vacuum (8.854×10)^-14 F/cm) N_Depl : carrier concentration (cm^-3 ) V_Bi : Built-in voltage (V) k: Boltzmann constant (8.617×10)^-5 eV/K) T: sample temperature (K) during measurement q: basic charge (1.602×10)^-19 C) V: The applied voltage (V) L can be obtained by the method disclosed in the examples. V_e As described below, it can be 0.1 V. Regarding the dielectric constant ε, as long as the composition and the crystal system of the semiconductor type are determined, the relative dielectric constant of the literature value can be used to determine the product of the relative dielectric constant and the dielectric constant of the vacuum. Further, when the number of reports in the literature is small or the difference is large depending on the report case, actual measurement can also be performed. When the actual measurement is performed, the capacitance value of the film thickness (L) of three or more points can be measured by the film thickness dependence measured by CV, and if C/A is plotted on the vertical axis, When 1/L is plotted on the horizontal axis, the slope becomes the dielectric constant ε. In order to make the semiconductor element satisfy the formula (I), the carrier concentration in the semiconductor layer is lowered. Specifically, the dopant concentration in the semiconductor is lowered. For example, in the case of a semiconductor in which a hydrogen atom or an oxygen defect in a semiconductor functions as a dopant as in an oxide semiconductor, a film having few defects and a high film density is effective for reducing the carrier concentration. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention. The semiconductor element 1 (vertical) sequentially has a Schottky electrode 10, a semiconductor layer 30, and an ohmic electrode 20. Further, a conductive substrate 40 is provided on the side opposite to the side of the semiconductor layer 30 of the Schottky electrode 10. Fig. 2 is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present invention. The semiconductor element 2 (vertical) sequentially has a Schottky electrode 10, a semiconductor layer 30, and an ohmic electrode 20. Further, the conductive substrate 40 is provided on the side opposite to the side of the semiconductor layer 30 of the ohmic electrode 20. Further, the ohmic electrode 20 has an insulating layer 50 on both sides thereof, and the ohmic electrode 20 is formed in one layer with the insulating layers 50 on both sides. The semiconductor element 3 of FIG. 3 differs from the element 2 of FIG. 2 only in the case where the width of the ohmic electrode 20 is wide. Fig. 4 is a schematic perspective view showing a semiconductor element as another embodiment of the present invention. The semiconductor element 4 (horizontal type) is disposed on the first surface of the first and second surfaces facing the semiconductor layer 30, and the Schottky electrode 10 is disposed at a distance from the ohmic electrode 20. Further, an insulating substrate 60 is provided on the second surface of the semiconductor layer 30. In the semiconductor device of the present invention satisfying the above formula (I), the initial carrier concentration of the semiconductor layer is small, and the exogenous carrier functions as a main factor of conduction. The well density of the semiconductor layer is small and does not hinder the conduction of the exogenous carrier. Further, in Patent Document 1, there is a relationship of the following formula, and there is a problem in the controllability of the carrier concentration based on the previous carrier concentration design guide of the unipolar power device. [Number 7](where n, ε, V_e , q and L are the same as in the formula (I). The semiconductor device of the present invention has a small reverse leakage current and a low forward conduction resistance, and can extract a large current. Moreover, even if an inexpensive germanium substrate or a metal substrate is used as the conductive substrate, good rectifying characteristics are exhibited. Further, even when the oxide semiconductor layer is formed into a film having excellent productivity such as sputtering, it exhibits good rectifying characteristics. The semiconductor device of the present invention is particularly excellent for use in a vertical Schottky barrier diode. <Regarding Formula (I)> Generally, in the insulator in which no carrier is present, the following formula (1) holds. J_Ins =(9/8)με(V² /L³ ) (1) J_Ins : Current density (A/cm² ) μ: mobility (cm² /V·s) ε: dielectric constant of the substance (F/cm) V: applied voltage (V) L: thickness (cm) of the region through which the current flows. On the other hand, regarding the conductor in which the carrier is present, the following formula (2) holds. J_Ohm =qnμ(V/L) (2) J_Ohm : Current density (A/cm² q: basic charge (1.602 × 10^-19 C) n: carrier concentration (cm^-3 ) μ: mobility (cm² /V·s) V: Applied voltage (V) L: Thickness (cm) of the region through which the current flows. Yu J_Ins =J_Ohm Under the condition, the following formula (3) holds. [Number 8](In the formula, n, ε, V, q, and L are the same as in the formulas (1) and (2). Therefore, when the following formula (4) is established, it means J._Ins >J_Ohm The role of insulating conduction is greater. That is, it means that the exogenous carrier functions as a main factor of conduction. [Number 9](where n, ε, V, q, and L are the same as in equations (1) and (2)) for Schottky barrier diodes and junction field effect transistors (JFETs) that exhibit rectification characteristics in a single pole. There is a drift region in the metal oxide film semiconductor field effect transistor (MOSFET). Generally, in the drift region, the relationship of the above formula (2) holds. In this case, the applied voltage V means the voltage applied to the drift layer. In the above formula (I), V will be_e Defined as the forward effective voltage, but it refers to the voltage, that is, the built-in voltage V for canceling the band bending is removed with respect to the applied voltage V in consideration of the actual device configuration._Bi The effective voltage to the drift layer after the action. In Schottky barrier diodes, junction field effect transistors (JFETs), metal oxide semiconductor field effect transistors (MOSFETs), etc., there are a pair of ohmic electrodes and Schottky between the semiconductor layer devices. In the electrode, as long as the above formula (I) is established, the exogenous carrier functions as a main factor of electrical conduction. Dielectric constant ε-based semiconductor relative permittivity ε_r Dielectric constant ε with vacuum₀ (8.854×10^-14 The product of (8.854E-14) [F/cm]). ε_r The parameters are different depending on the material, but are preferably from 3 to 20, more preferably from 5 to 16, more preferably from 9 to 13. If the relative dielectric constant is too low, there is a small amount of injection of the exogenous carrier, and a high current cannot be obtained. If the relative dielectric constant is too large, there is an increase in parasitic capacitance or a hysteresis in current characteristics. About the forward effective voltage V_e If the actual forward characteristics are used, the applied voltage to the unipolar device is usually about 0.5 V to 1.5 V, and the built-in voltage V is_Bi Usually 0.7 to 1.3 V, you can put V_e It is considered to be around 0.1 V. The value of the basic charge is 1.602×10^-19 C /, so if ε_r Assuming 10, in view of formula (I), the upper limit of the carrier concentration n is determined by the interval L between one of the semiconductor layers and the ohmic electrode and the Schottky electrode, as shown in Table 1. [Table 1] L is preferably 10 nm < L < 100000 nm, more preferably 20 nm < L < 10000 nm, further preferably 30 nm < L < 1000 nm, and most preferably 50 nm < L < 300 nm. When the inter-electrode spacing L is too short, there is a problem in terms of withstand voltage. If L is too large, the current value is lowered or the thickness of the semiconductor layer in the vertical element is increased to cause time consuming film formation. L and n preferably satisfy the relationship represented by the following formula (Ia), more preferably satisfy the relationship represented by the following formula (Ib), and further preferably satisfy the relationship represented by the following formula (Ic); Preferably, the relationship shown by the following formula (Id) is satisfied. [Number 10](where n, ε, V_e , q and L are the same as in the formula (I). When n is too low, the trap existing in the inside of the semiconductor layer has an effect, and the effect of the diffusion current is large, and the current characteristics are deteriorated. On the other hand, if n becomes εV of the formula (I)_e /qL² As described above, the effect of the drift current is increased, and it is difficult to produce the effect of the present invention as it is close to the previous operational characteristics. <Withstand Voltage of Semiconductor Element> The semiconductor element of the present invention has a pair of ohmic electrodes and a Schottky electrode between the semiconductor layers. Compared with the previous power devices, the withstand voltage V is low due to the designed carrier concentration._BD Design relative to V_BD ~E_c L/2 becomes V_BD ~E_c L, it is expected to compare with the same L and increase the withstand voltage by about 2 times. Here, E_c For maximum insulation damage to the electric field, L is the length between the electrodes. Moreover, in the prior power device, since the initial carrier concentration is high, the leakage current when the reverse bias is applied is large, and when the peripheral portion (side surface) of the Schottky electrode is perpendicular to the ohmic electrode surface, It is difficult to obtain a component structure in which the ohmic electrode is covered in a plane perpendicular to the Schottky surface. In the present invention, the initial carrier concentration in the semiconductor layer is low, and when the forward voltage is applied, the external carrier is implanted only in the ohmic electrode surface when the peripheral portion of the Schottky electrode is perpendicular to the ohmic electrode surface. It is included in the range from the vertical line of the Schottky surface. On the other hand, when a reverse bias is applied, carriers are not present throughout the entire semiconductor layer, so the influence of leakage current due to rewinding is small. Fig. 5 is a view for explaining an electrode surface of the semiconductor element of Fig. 2. In FIG. 5, the outer peripheral portion of the Schottky electrode is indicated by the symbol 12, and the ohmic electrode surface is indicated by the numeral 22. A perpendicular line drawn from the outer peripheral portion 12 of the Schottky electrode to the ohmic electrode surface 22 is indicated by the symbol A. In a vertical power device, generally, the lower portion of the semiconductor layer is an ohmic electrode, but when the ohmic electrode is inside the vertical line drawn from the Schottky electrode, the Schottky electrode can be easily used for the lower portion of the semiconductor layer. Further, it is known that an electric field absorbing structure such as a guard ring is used in a normal power device to reduce the reverse leakage current. With such a configuration, the electric field mitigation structure which is a process defect can be omitted or reduced. In a power device in which the externally-induced carrier becomes the dominant unipolar, the withstand voltage becomes V as described above._BD ~E_c L, so according to the length between the electrodes L and the withstand voltage V_BD The measurement result can easily determine the dielectric breakdown electric field. Here, the withstand voltage of the unit L corresponds to the dielectric breakdown electric field. If the withstand voltage per unit film thickness is high, L can be reduced when designing the same withstand voltage element, so that the injection of the externally-induced carrier is increased, and the element having lower resistance can be provided. The withstand voltage of the unit L is preferably 0.5 MV/cm or more, more preferably 0.8 MV/cm or more, still more preferably 1.0 MV/cm or more, and particularly preferably 3.0 MV/cm or more. The withstand voltage of the unit L can be obtained by measuring the breakdown voltage (V) and dividing by the length of L. For example, in the case of a Schottky barrier diode, it will have reached 1×10 when sweeping the reverse voltage.^-3 The initial voltage value of the current value of A is defined as the breakdown voltage. Further, the withstand voltage of the unit L can be adjusted according to the material selection of the semiconductor layer. In the present invention, when the material of the semiconductor layer is a band gap of 1 eV or more and contains an amorphous or polycrystalline semiconductor layer, it can be 0.5 MV/cm or more. When it is a material having a band gap of 2 eV or more, it is 1.0 MV/cm or more, and when it is a band gap of 2 eV or more and contains an amorphous or polycrystalline semiconductor layer, it can reach 3.0 MV/cm or more. <Characteristic Temperature> The characteristic temperature is a parameter indicating the characteristics of the tail energy level at the lower end of the conduction band specific to amorphous or polycrystalline crystals, and is a semiconductor having a tail-level energy-dependent carrier at the lower end of the conduction band. The characteristics of the following formula (5). [Number 11]J: current density (A/cm² u: mobility (cm² /V·s) N_c : Effective state density of semiconductors (cm^-3 ) N_t : the tail energy density of the lower end of the conduction band (cm^-3 ε: dielectric constant of material (F/cm) V: applied voltage (V) L: thickness of region through which current flows (cm) e: basic charge (1.602×10)^-19 C) I: Tc/T Tc: characteristic temperature (K) T: actual temperature (K) The characteristic temperature Tc is a parameter of Tc>T, which has a large number of energy at the end of the tail, which prevents the injection of the externality by the trap. When the carrier is transmitted, it becomes a larger value. When the current-voltage measurement is performed, it can be seen from the equation (5) that the slope of the curve of Log(J)-Log(V) is I+1. Therefore, I is obtained from the slope, and Tc is calculated. However, the case where the value of Tc is fixed with respect to a continuous range of application voltage becomes an indicator that the semiconductor layer has a tail energy level. It is preferably Tc < 1500 K, more preferably Tc < 900 K, and further preferably Tc < 600 K. If the value of Tc is large, there is an increase in the number of carriers due to the trapping of the tail energy level, and the device characteristics are high resistance. The characteristic temperature can be determined from the slope of the curve of Log(J)-Log(V) by performing current-voltage measurement. The characteristic temperature can be lowered by increasing the short-range order of the atomic structure in amorphous or polycrystalline semiconductors. For example, in the case of an amorphous metal oxide semiconductor, a film having a low density tends to have a short distance order and a characteristic temperature tends to be high. It has been confirmed that in the amorphous metal oxide semiconductor formed by sputtering, the density is related to the film formation conditions. The closer the target-substrate distance is, the lower the sputtering pressure is, the higher the substrate temperature at the time of film formation or the higher the annealing temperature after film formation, or the higher the applied voltage applied to the target at the time of sputtering film formation, the easier it is to form. High density film. Further, when sputtering is performed, 0.1 to 10% by volume of H is added.₂ Or H₂ As a sputtering gas, O is easy to obtain a film of high density. When the amorphous or polycrystalline semiconductor layer contains a metal oxide semiconductor of one or more elements selected from the group consisting of In, Zn, Ga, and Sn, the s-track having a high target property can be utilized, so that it is less susceptible to the disorder of the periodic potential. Influence, the characteristic temperature tends to be low. <Lamination of Drift Layer (Limited to Vertical Element)> The following semiconductor element (vertical) can be obtained, that is, having a carrier concentration of the following formula (6)_L Lower semiconductor layer (L₁ , L₂ ,...L_n )(n_L And L_n Indicates the carrier concentration and film thickness of the layer with the lower concentration of the carrier at the nth when the Schottky electrode is counted toward the ohmic electrode) and the carrier concentration n_h Higher semiconductor layer (d₁ , d₂ ,...d_N-1 )(n_h And d_n The structure in which the carrier concentration and the film thickness of the layer having the higher carrier concentration of the nth carrier are repeated on the drift layer when the Schottky electrode is counted toward the ohmic electrode is shown. [Number 12](in the formula, n_L The carrier concentration of the layer at the lower concentration of the nth carrier when the Schottky electrode is counted toward the ohmic electrode, and ε represents the dielectric constant of the semiconductor layer having the lower carrier concentration of the nth, V_e Indicates the effective voltage of the semiconductor layer applied to the nth carrier with a lower concentration (can be set to V_e =0.1 V), q represents the basic charge, L_n The film thickness of the semiconductor layer having a lower carrier concentration of the nth layer is expected to be higher than the drift of the single layer by the lamination, and the resistance value can be expected to be reduced. In this case, L_n Preferably 10 nm < L_n <1000 nm, more preferably 20 nm<L_n <300 nm, and more preferably 30 nm<L_n <200 nm, especially 30 nm<L_n <100 nm. If L_n If it is too short, the difference will become larger if L_n If it is too long, the resistance value will become higher. Again, d_n Preferably 3 nm<d_n <30 nm, more preferably 5 nm<d_n <10 nm. If d_n If it is too long, the depletion layer does not spread to the entire region from the Schottky electrode to the ohmic electrode when a reverse bias is applied, which causes a problem in terms of withstand voltage. If d_n Too short, there is no play as L_n With L_{n + 1} The function of the spacer layer does not function as a laminate structure. n_h It is preferably the following formula (6-a), more preferably the following formula (6-b), and still more preferably the following formula (6-c). [Number 13](wherein ε represents the dielectric constant of the semiconductor layer having a higher concentration of the nth carrier, V_e Indicates the effective voltage of the semiconductor layer applied to the nth carrier with a higher concentration (can be set to V_e =0.1V), q represents the basic charge, d_n The film thickness of the semiconductor layer indicating the higher concentration of the carrier of the nth number)_h If it is too large, the semiconductor layer having a high carrier concentration suppresses the extension of the depletion layer when the reverse bias is applied, and it is difficult to maintain the withstand voltage. If n_h If it is too small, it is necessary to inject an exogenous carrier into the layer with a higher concentration of the carrier during the forward application. As a result, a plurality of semiconductor layers having a lower concentration of the carrier operate as a layer having a lower carrier concentration and the resistance value. Increased. Preferably, the layer with the Schottky electrode is a layer having a lower carrier concentration. <Series connection of semiconductor elements> In the voltage withstand design of the conventional unipolar power device, when the voltage with a rated withstand voltage is applied, the electric field strength of the semiconductor interface on the Schottky metal side reaches the vicinity of the dielectric breakdown electric field, making it difficult to carry out the semiconductor element. Link. For example, in the case of a Schottky barrier diode, it is difficult to obtain a withstand voltage of 600 V or more even if a plurality of components having a 600 V withstand voltage are connected in series. In the semiconductor device (power device) in which the initial carrier concentration of the present invention is low and the external injection carrier is used, in the case of a plurality of series connection, the breakdown voltage is multiplied by the rated withstand voltage corresponding to the number of the connected ones. And increase. Therefore, it is possible to easily provide the required pressure-resistant component. <Composition Layer of Semiconductor Element> (1) Semiconductor Layer The semiconductor layer is not particularly limited, and preferably contains polycrystalline or amorphous. Further, it is preferable to contain a metal oxide semiconductor, and more preferably a metal oxide semiconductor containing an element selected from one or more selected from the group consisting of In, Zn, Ga, Sn, and Al. When it is amorphous, the large-area uniformity is excellent, and the impact ionization at the time of applying a reverse bias is lowered and the withstand voltage is improved. If it is polycrystalline, it has a large area uniformity and a good conduction property. When a semiconductor layer is produced from a metal oxide semiconductor, a film formation method excellent in a large area using a sintered sputtering target can be employed. By using a metal oxide semiconductor containing an element selected from one or more of In, Zn, Ga, Sn, and Al in a semiconductor layer, the conduction characteristics of the s orbit of the metal element can be utilized, so that even if it is amorphous or The crystal also forms a semiconductor layer having overlapping tracks and excellent conduction characteristics. The metal oxide semiconductor may contain one or more metal oxides. Examples of the metal oxide include oxides of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. It is preferable to contain one or more elements selected from the group consisting of In, Zn, Ga, and Sn. The metal of the metal oxide semiconductor may substantially contain one or more selected from the group consisting of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. Further, the metal may be, for example, 95 atom% or more, 98 atom% or more, or 99 atom% or more, and may be one or more selected from the group consisting of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, or Al. . The metal oxide constituting the metal oxide semiconductor preferably has an atomic ratio satisfying the following formulas (A) to (C). In the case of such a composition, it is possible to set a high withstand voltage and a low on-resistance. 0≦x/(x+y+z)≦0.8 (A) 0≦y/(x+y+z)≦0.8 (B) 0≦z/(x+y+z)≦1.0 (C) (where x represents a selected from In, Sn, Ge, and The number of atoms of one or more elements in Ti, y represents the number of atoms of one or more elements selected from the group consisting of Zn, Y, Sm, Ce, and Nd, and z represents the number of atoms selected from one or more of Ga and Al) When x is more than 0.8, when x is In or Sn, the insulation of the metal oxide becomes low, the Schottky junction is not easily obtained, and when x is Ge or Ti, there is a metal oxide. The insulation becomes high and becomes a cause of heat generation due to ohmic loss. More preferably, the above compositions (A) to (C) are the following formulas (A-1) to (C-1), respectively. 0≦x/(x+y+z)≦0.7 (A-1) 0≦y/(x+y+z)≦0.8 (B-1) When z is Ga: 0.02≦z/(x+y+z)≦1.0 z is Al: 0.005≦z /(x+y+z)≦0.5 (C-1) (wherein x, y and z are the same as the above formulae (A) to (C)) When z is Ga, if it is less than 0.02, there is oxygen in the metal oxide Easy to get rid of, uneven electrical characteristics. Further, it is preferred that the above components (A) to (C) are the following formulas (A-2) to (C-2), respectively. 0.1≦x/(x+y+z)≦0.5 (A-2) 0.1≦y/(x+y+z)≦0.5 (B-2) 0.03≦z/(x+y+z)≦0.5 (C-2) (where x and y are The above formulae (A) to (C) are the same, and z is Ga). The above compositions (A) and (C) are preferably the following formulas (A-3) and (C-3), respectively. 0≦x/(x+y+z)≦0.25 (A-3) 0.3≦z/(x+y+z)≦1.0 (C-3) (wherein x, y, and z are the same as the above formulas (A) and (C)) The metal oxide of the metal oxide semiconductor layer may be amorphous or crystalline, and the crystal may be microcrystalline or single crystal. Preferably, the metal oxide is amorphous or microcrystalline. When the metal oxide is used as a single crystal, a method in which crystal growth is started from a seed crystal, or MBE (molecular beam epitaxy) or PLD (pulse laser deposition) is used. If SiO₂ Crystal growth on a surface or a metal surface is liable to cause crystal defects, and when used as a device for energization in the longitudinal direction, there is a problem that the crystal defect causes a defect. In SiO₂ In the case of crystal growth on the surface or the metal surface, the heating temperature, time, and the like are appropriately adjusted so that the particle diameter does not become excessive. On the other hand, in the case of amorphous, even if a dangling bond is present, since it does not exist as a crystal defect, it is possible to alleviate the unevenness of electrical characteristics or the characteristic deterioration of a large amount. Further, since the metal oxide and the Si semiconductor have different covalent bonds and have high ionic bonding properties, the energy level by the dangling bonds approaches the conductive tape or the full body. Therefore, the metal oxide has a smaller difference in electrical characteristics such as mobility due to structure than Si or SiC. When such a property of the metal oxide is actively utilized, a large current diode or a switching element having high withstand voltage and high reliability can be provided at a high yield even in the case of a single crystal. Here, "amorphous" means that a cross section of the metal oxide layer in the film thickness direction is obtained, and when it is evaluated by an electron beam diffraction method such as a transmission electron microscope, it is impossible to obtain a distinct diffracted light. Pointer. It is preferable to obtain a diffraction image from a wide area of about 10 nm from the irradiation region of the electron beam. The so-called obvious light spot refers to a diffraction point with symmetry observed from the diffraction image. Further, "amorphous" also includes a portion having partial crystallization or microcrystallization. When the electron beam is irradiated to the partially crystallized portion, the diffraction image can be confirmed. The term "microcrystalline structure" means that the size of the crystal grain size is submicron or less, and there is no clear grain boundary. By "polycrystalline" is meant that the size of the crystal grain size exceeds the micron size and there is a clear grain boundary. The carrier concentration of each layer constituting the metal oxide semiconductor layer is usually 1 × 10¹¹ ~1×10¹⁸ Cm^-3 , for example, 1×10¹³ ~1×10¹⁸ Cm^-3 . The carrier concentration can be determined, for example, by CV measurement. The properties required for the diode are high-speed switching, high withstand voltage, and low on-resistance, and these characteristics can be combined as long as a semiconductor element using a metal oxide is used. The reason is that the band gap of the metal oxide is originally wide and is high withstand voltage. Further, since the oxygen defect tends to be n-type and the p-type is not easily formed, this case is also advantageous for high-speed switching. In order to lower the on-resistance, it is only necessary to crystallize it to increase the mobility, but it is preferably limited to the extent that the grain boundary cannot be formed. Porosity is often present in the grain boundaries, and polarization occurs when an electric field is formed, which makes the pressure resistance performance lower. In the case where the reduction in withstand voltage is remarkable, it is preferably used directly in the form of amorphous. When it is used as an amorphous material, it depends on the type of the element forming the metal oxide layer. However, the heat treatment conditions may be set to, for example, 500 ° C or less and within 1 hour. By heating at a low temperature of 500 ° C or lower, a stable amorphous state can be obtained. The film thickness of the semiconductor layer is not limited and is usually from 100 to 8000 nm. (2) The metal of the Schottky electrode constituting the Schottky electrode is not particularly limited, and is preferably selected from the group consisting of Pd, Mo, Pt, Ir, Ru, Ni, W, Cr, Re, Te, Mn, Os, Fe, One or more metals (including an alloy) or an oxide of the metal of Rh and Co are more preferably one or more selected from the group consisting of Pd, Pt, Ir, and Ru (including an alloy) or an oxide of the metal. Further, a metal or metal oxide which is in contact with the Schottky which is excellent in the pressure-resistant layer of the oxide semiconductor layer is preferable. More preferably, in combination with an oxide semiconductor, a higher Schottky barrier Pd oxide, Pt oxide, Ir oxide, and Ru oxide are formed. The oxides usually have a semiconductor or an insulator formed by oxidation, but can maintain a high carrier density metal state by selecting a composition or film formation condition, and are formed by contact with an oxide semiconductor. Good Schottky contact. In order to form a good Schottky electrode for the oxide, it is preferred that the carrier concentration of the Schottky electrode is preferably 10¹⁸ Cm^-3 the above. If not up to 10¹⁸ Cm^-3 In the case where the contact with the oxide semiconductor layer is p-n junction, the advantage of the Schottky diode such as high-speed response is impaired. The carrier concentration can be obtained, for example, by Hall measurement or the like. The method for producing the metal oxide layer is not particularly limited, and can be preferably used in a method of performing reactive sputtering of the metal target in an oxygen-containing atmosphere. The thickness of the Schottky electrode is usually from 2 nm to 500 nm, preferably from 5 nm to 200 nm. If it is too thin, there is a possibility that the on-resistance at the time of forward bias is increased by the influence of the metal to be contacted. If it is too thick, the on-resistance at the time of forward bias is increased due to its own resistance, or the flatness of the Schottky interface is deteriorated, and the withstand voltage is lowered. Regarding the Schottky electrode, in order to reduce the contact resistance with the substrate or the current extraction electrode and to improve the adhesion, a layer containing a plurality of metals or metal oxides having different compositions may be laminated on the side opposite to the side in contact with the semiconductor layer. (3) The material of the ohmic electrode ohmic electrode is not particularly limited as long as it can perform good ohmic connection with the semiconductor layer, and is preferably one selected from the group consisting of Ti, Mo, Ag, In, Al, W, Co, and Ni. The above metal (including an alloy) or a compound thereof (oxide or the like) is more preferably a metal (including an alloy) or a compound thereof selected from the group consisting of Mo, Ti, Au, Ag, and Al. Further, the ohmic electrode may be formed by a plurality of layers. For example, a Mo electrode layer is used on the side in contact with the semiconductor layer, and in order to extract a large current and to thickly laminate a metal layer such as Au or Al, the layer can serve as a basis for wire bonding. The thickness of the ohmic electrode is usually 10 nm to 5 μm. (4) Film forming method The film forming method of each layer is not particularly limited, and a method of thermal CVD (chemical vapor deposition) or CAT-CVD (catalytic chemical vapor deposition) can be used. CVD method such as deposition method, photo CVD method, atomization CVD method, MO-CVD (Metal-organic Chemical Vapor Deposition), plasma CVD method, etc.; MBE (Molecular Beam Epitaxy) Atomic-level film formation methods such as epitaxial method and ALD (atomic layer deposition); PVD (Physical Vapor Deposition) such as ion plating, ion beam sputtering, and magnetron sputtering Method; a previously known method of using a ceramic step such as a doctor blade method, an injection method, an extrusion method, a hot press method, a sol-gel method, an aerosol deposition method, etc.; a coating method, a spin coating method, a printing method, a spray method Wet method such as electroplating method, plating method, and micellar electrolysis method. In the case of selecting a metal oxide semiconductor, the film formation method of the semiconductor layer is preferably sputtering. The film forming gas is preferably at least one selected from the group consisting of rare gases, oxygen, hydrogen, and water. The distance between the sputtering target and the substrate (TS interval) is preferably from 10 mm to 200 mm. If the TS interval is too short, there is a possibility that the TS cannot be discharged. When the TS interval is too long, the film quality of the semiconductor becomes sparse, and it may become a film having a large characteristic temperature. (5) Substrate The substrate of the semiconductor element is not particularly limited, and a known one can be used. Examples of the substrate include a conductive substrate, a semiconductor substrate, and an insulating substrate. In the vertical semiconductor element, as shown in FIGS. 1 and 2, a conductive substrate can be used. The conductive substrate can be disposed in contact with the Schottky electrode or the ohmic electrode. As the conductive substrate, a substrate which is excellent in surface smoothness such as a tantalum single crystal substrate, a tantalum polycrystalline substrate, or a tantalum crystal substrate can be used. Further, a semiconductor substrate such as a SiC substrate, a GaN substrate, or a GaAs substrate can be used in addition to the germanium substrate. A metal substrate having excellent conductivity such as an Al substrate, a Cu substrate, or a Ni substrate can be used. In view of mass productivity and cost, it is preferable to use a substrate. The germanium substrate has an n-type, an i-type, and a p-type depending on the presence or absence of doping, and when a current flows in the longitudinal direction, it is preferably an n-type or a p-type having a small electric resistance. As the dopant, previously known B, P, Sb, or the like can be used. Especially in the case of reducing the resistance, As or red phosphorus can also be used as a dopant. In the transverse semiconductor device, as shown in FIG. 4, an insulating substrate can be used. The insulating substrate can be disposed in contact with the semiconductor layer. The insulating substrate is not particularly limited as long as it has insulating properties, and the user can be arbitrarily selected without departing from the effects of the present invention. For example, in addition to quartz glass, bismuth borate glass, aluminoborosilicate glass, aluminosilicate glass, etc., an alkali-free glass substrate or a ceramic substrate produced by a melt method or a floating method, it can be used to be resistant. A plastic substrate or the like which is subjected to heat treatment at a temperature of the production step. Further, a dielectric substrate can also be used as the insulating substrate. Examples of the dielectric substrate include a lithium niobate substrate, a lithium niobate substrate, a zinc oxide substrate, a crystal substrate, and a sapphire substrate. Further, a substrate for an insulating film or a dielectric film can be provided on the surface of a metal substrate such as a stainless steel alloy. Further, an insulating film may be formed on the substrate as a base film. As the base film, a single layer or a laminate such as a ruthenium oxide film, a tantalum nitride film, a hafnium oxynitride film, or a hafnium oxynitride film can be formed by a CVD method or a sputtering method. The material of the semiconductor substrate is not particularly limited as long as the smoothness of the surface is maintained. As the semiconductor substrate, the carrier concentration is adjusted to 1 × 10¹⁸ Cm^-3 The following Si substrate, GaN substrate, SiC substrate, GaP substrate, GaAs substrate, ZnO substrate, Ga₂ O₃ A substrate, a GaSb substrate, an InP substrate, an InAs substrate, an InSb substrate, a ZnS substrate, a ZnTe substrate, a diamond substrate, or the like. The semiconductor substrate may be single crystal or polycrystalline. Further, it may be a substrate partially containing an amorphous substrate or an amorphous substrate. It can also be used on a conductor substrate, a semiconductor substrate, or an insulating substrate, and a substrate on which a semiconductor film is formed by a method such as CVD (Chemical Vapor Deposition). The substrate may be used on the conductive substrate, the semiconductor substrate, or the insulating substrate, and may have any structure, layer structure, circuit, wiring, electrode, or the like which is composed of a plurality of materials. Examples of the material of the arbitrary structure include a composite material of various metals or insulators such as a metal or an interlayer insulating film which is formed on a large-scale integrated circuit (LSI). The layer as the layer structure is not particularly limited, and an electrode layer, an insulating layer, a semiconductor layer, a dielectric layer, a protective film layer, a stress buffer layer, a light shielding layer, an electron/hole injection layer, and an electron/hole transport layer can be used. A well-known layer such as a light-emitting layer, an electron/hole blocking layer, a crystal growth layer, an adhesion improving layer, a memory layer liquid crystal layer, a capacitor layer, and an electricity storage layer. Examples of the electrode layer include an Al layer, a Si layer, a Sc layer, a Ti layer, a V layer, a Cr layer, a Ni layer, a Cu layer, a Zn layer, a Ga layer, a Ge layer, a Y layer, a Zr layer, and an Nb layer. Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Hf, Ta, W, Re, Os, Ir And a Pt layer, an Au layer, an alloy layer containing one or more metals of the layers, an oxide electrode layer, and the like. It is also possible to increase the carrier concentration of a semiconductor such as an oxide semiconductor or Si for the electrode layer. The insulating layer is generally selected from the group consisting of Al, Si, Sc, Ti, V, Cr, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag. An oxide insulating film, a nitride film, or the like of a metal of one or more of the group consisting of Cd, In, Sn, Sb, Te, Hf, Ta, W, Re, Os, Ir, Pt, and Au. The semiconductor layer is not limited to a single crystal, polycrystal, or amorphous crystal state, and widely includes a Si layer, a GaN layer, a SiC layer, a GaP layer, a GaAs layer, a GaSb layer, an InP layer, an InAs layer, an InSb layer, and a ZnS. Layer, ZnTe layer, diamond layer, Ga₂ O₃ An oxide semiconductor layer such as ZnO or InGaZnO or an organic semiconductor layer such as fused pentene. Examples of the dielectric layer include a lithium niobate layer, a lithium niobate layer, a zinc oxide layer, a crystal substrate layer, a sapphire layer, and BaTiO.₃ Layer, Pb(Zr,Ti)O₃ (PZT) layer, (Pb, La) (Zr, Ti) O₃ (PLZT) layer, Pb(Zr, Ti, Nb)O₃ (PZTN) layer, Pb(Ni, Nb)O₃ -PbTiO₃ (PNN-PT) layer, Pb(Ni, Nb)O₃ -PbZnO₃ (PNN-PZ) layer, Pb(Mg, Nb)O₃ -PbTiO₃ (PMN-PT) layer, SrBi₂ Ta₂ O₉ (SBT) layer, (K, Na) TaO₃ Layer, (K, Na) NbO₃ Layer, BiFeO₃ Layer, Bi(Nd, La)TiO_x Layer (x=2.5～3.0), HfSiO(N) layer, HfO₂ -Al₂ O₃ Layer, La₂ O₃ Layer, La₂ O₃ -Al₂ O₃ Layers, etc. As the film of the protective film layer, a film which is excellent in insulating properties and low in permeability of water or the like is exemplified, regardless of the inorganic substance or the organic substance. As the protective film layer, for example, SiO₂ Layer, SiN_x Layer (x=1.20~1.33), SiON layer, Al₂ O₃ Layers, etc. Examples of the stress buffer layer include an AlGaN layer and the like. Examples of the light shielding layer include a black matrix layer containing a metal, a metal-organic substance, and a color filter layer. Examples of the electron/hole injection layer include an oxide semiconductor layer, an organic semiconductor layer, and the like. Examples of the electron/hole transport layer include an oxide semiconductor layer, an organic semiconductor layer, and the like. Examples of the light-emitting layer include an inorganic semiconductor layer, an organic semiconductor layer, and the like. Examples of the electron/hole blocking layer include an oxide semiconductor layer and the like. Examples of the substrate include a power generation device, a light-emitting device, a sensor, a power conversion device, an arithmetic device, a protection device, an optoelectronic device, a display, a memory, a semiconductor device having a back-end process, a power storage device, and the like. The layer of the layer structure may be a single layer or a layer of two or more layers. The semiconductor device of the present invention can be used as a power semiconductor element, a (rectifier) diode element, a Schottky barrier diode element, an electrostatic discharge (ESD) protection diode, and a transient voltage protection (TVS) protection diode Body, LED, MOSFET, FET, JFET, MOSFET, Schottky source/drain MOSFET -Oxide-Semiconductor Field Effect Transistor, avalanche multiplying photoelectric conversion element, solid-state imaging element, solar cell element, photo sensor element, display element, resistance change memory, and the like. It is also especially suitable for power applications because it can extract large currents. Electronic circuits using the components can be applied to electrical machines, electronic machines, vehicles, power mechanisms, and the like. [Examples] Example 1 An n-type Si substrate (4 inches in diameter and 250 μm in thickness) having a specific resistance of 0.001 Ω·cm was attached to a sputtering apparatus (manufactured by CANON ANELVA: E-200S) to form a laminated electrode below. However, for the back surface of the substrate, in order to eliminate the contact resistance with the probe device during the measurement, Ti 100 nm/Au 50 nm treatment was performed. First, Ti is formed into a film of 15 nm in DC (Direct Current, DC) at 50 W, Ar, and then Pd is formed into a film of 50 nm in a DC 50 W, Ar environment. Finally, as a Schottky electrode, at DC50 W, Ar. With O₂ A 20 nm PdO film was formed in a mixed gas atmosphere. Then, the substrate was placed in a sputtering apparatus (manufactured by ULVAC: CS-200) together with a semiconductor region mask, and an InGaZnO (In:Ga:Zn (atomic ratio)=1:1:1 was formed at 200 nm. In the following, the oxide of the composition is referred to as "InGaZnO (1:1:1)", and the other composite oxides are similarly described as the pressure-resistant layer (semiconductor layer). Film formation conditions are set to: DC300 W, Ar and H₂ O mixed gas environment (H₂ O concentration: 1% by volume). The sputtering target-substrate distance (TS interval) was set to 80 mm. The substrate was taken out and annealed in an electric furnace at 300 ° C for 1 hour in the air. The substrate and the electrode were again placed in a sputtering apparatus with a region mask (pore diameter: 50 μm), and a 150 nm Mo was formed as an ohmic electrode (diameter: 50 μm). Thereafter, an Al electrode of 2 μm was formed using the same mask. The film formation conditions were all set to DC100 W and Ar environment. As a final treatment, an under-tempering treatment at 200 ° C for 1 hour was carried out. Further, the element configuration has a configuration in which a Schottky electrode is provided on the lower portion of the semiconductor layer as shown in FIG. 1, and an ohmic electrode surface is formed when the peripheral portion of the Schottky electrode is perpendicular to the ohmic electrode surface. Located inside the above vertical line. <Interelectrode Distance L> The interelectrode distance L is obtained by a cross-sectional TEM (transmission electron microscope) image and an EDX (energy dispersive X-ray spectroscopy) image of a cross-sectional TEM. It is assumed that the layer containing InGaZnO is a semiconductor layer, the Schottky electrode is a PdO layer, the ohmic electrode is Mo, and the contrast of the TEM cross-section image is defined by EDX and the portion including InGaZnO is a semiconductor layer. Defined as the distance L between the electrodes. Further, the semiconductor layer was sandwiched by Pd and Mo by EDX, and the distance L between the electrodes was 200 nm. When the semiconductor layer is depleted by reverse bias and is biased as a resistive layer by forward biasing, it is confirmed by CV (capacity-voltage) measurement that the thickness should function as a semiconductor in the above-mentioned L. no problem. The minimum capacity value C when the reverse voltage is applied_Min And the maximum capacity value C when a forward voltage is applied_Max , using C/A=ε_r ×ε₀ /d relational expression C_Min Corresponding film thickness d_Min And C_Max Corresponding film thickness d_Max Since the difference converges to L±50% with respect to L, it is verified that the distance L between the electrodes is 200 nm. However, the relative dielectric constant of InGaZnO (1:1:1) in the film formation method was confirmed to be 16 according to the film thickness measurement, so ε was used._r =16. It is generally reported that the relative dielectric constant of InGaZnO is about 10 to 19. C: capacity value (F) A: effective area of the electrode (cm² d: film thickness (cm) ε acting as a semiconductor_r : Relative dielectric constant ε₀ : Dielectric constant of vacuum, 8.854E-14 [F/cm] Here, the effective area A of the electrode indicates the area of the ohmic electrode and the Schottky electrode which are separated from each other with respect to the semiconductor layer. Regarding this embodiment, the area of the ohmic electrode having a diameter of 50 μm can be regarded as A. Further, in the CV measurement, the CMU (Capacitance Measure Unit) unit of B1505 described below was used, and the voltage was superposed by the bias voltage T to carry out the measurement. The measurement frequency is 1 kHz and the AC amplitude is set to 0.03 V. <Identification of Electrode Type> The identification of the electrode type was carried out after the identification of the above-mentioned semiconductor layer, and the type of the electrode sandwiching the semiconductor layer material was regarded as an ohmic electrode and a Schottky electrode. From the cross-sectional EDX image, it is presumed that the metal or metal compound containing Mo and Pd is an ohmic electrode or a Schottky electrode. Based on the confirmation of the rectification characteristics, it was judged that the Mo side was an ohm and the Pd side was a Schottky electrode type. Further, by XPS (X-ray photoelectron spectroscopy, X-ray photoelectron spectroscopy), the surface of the element was subjected to Ar sputtering to the depth method, and the XPS spectrum was confirmed. From the Mo side to the Mo/InGaZnO interface, the peak of oxygen from the Mo spectrum of XPS is accompanied by a gradual increase in the oxygen concentration of InGaZnO, and the Mo layer away from InGaZnO is focused on more than 90% of the XPS spectrum of Mo. Attributable to pure Mo, the ohmic electrode is set to Mo. On the other hand, in the state of InGaZnO/PdO from the side of InGaZnO to Pd, the peak of oxygen in the Pd spectrum of XPS is not accompanied by a gradual decrease in the oxygen concentration contained in InGaZnO, and a certain degree of oxygen is contained. In Pd. Moreover, in the region where Pd is observed by the EDX image, the contrast of the TEM image is clearly seen, and in the depth direction XPS between the region of pure Pd and the region of InGaZnO, there is an electron density of less than 20 nm. The area of the Pd of pure Pd. Thus, the Schottky electrode is a layer containing Pd or PdO of about 20 nm. As shown in Table 2-1, it is referred to as Pd(PdO). <Evaluation of Crystallinity> The crystallinity was evaluated by an electron beam diffraction method when observing the cross-sectional TEM of the semiconductor layer. A diffraction image is obtained from an area where the electron beam is irradiated in a region having a diameter of 10 nm or more. In the plurality of dots in the direction parallel to the film thickness direction and the cross section, the spot shape cannot be confirmed in the diffraction image, and therefore the semiconductor layer is determined to be amorphous, that is, amorphous. <Electrical characteristic result> For the obtained component, B1505 (HVSMU (High-voltage Source Measure Unit), HCSMU (Heavy-current Source Measure Unit), which is manufactured by KEYSIGHT TECHNOLOGIES, is used. MFCMU (Multi-frequency Capacitance Measure Unit), MPSMU (Medium-power Source Measure Unit), bias voltage T (N1272A), circuit switching machine (N1258A), and Cascade The company's high-voltage probe instrument, EPS 150 TESLA, measures voltage (V)-current characteristics (J) and voltage (V)-capacity (C) characteristics. In addition, the following items were evaluated. The results are shown in Table 2-1. However, each of the SMUs or CMUs described above is disposed on the Schottky electrode side at the time of measurement, and a bias voltage is applied. The ohmic electrode side is in a state of applying 0 V. (1) Measurement of carrier concentration The carrier concentration was obtained by the above apparatus and the above-described CV measurement. Made on the vertical axis, take A² /C² , taking the curve of the applied voltage V on the horizontal axis, using the slope between 0 V and 2 V as the starting point and the slope of the line and -2/(ε_r ε₀ N_Depl In proportion to this case, set the carrier concentration n=N_Depl The carrier concentration of the semiconductor layer was determined. The carrier concentration is 1.0×10 as shown in Table 2-1.¹⁴ Cm^-3 . Further, it is confirmed that the semiconductor is n-type based on the behavior of the CV measurement. Further, in the CV measurement, the CMU unit of the following B1505 was used, and the voltage was superposed by the bias voltage T to carry out the measurement. The measurement frequency is 1 kHz and the AC amplitude is set to 0.03 V. It was confirmed that the present semiconductor element satisfies the following formula (I). Furthermore, according to the above, the dielectric constant is calculated from the relative dielectric constant 16 of InGaZnO, V_e Set to 0.1 V and L to 200 nm to determine the size relationship. [Number 14](2) Measurement of characteristic temperature The characteristic temperature was determined by the method described above. The HCSMU using the above device is applied to 0 V to 3 V in a manner of applying a forward bias to the device (a positive voltage is applied to the HCSMU). Take the difference between LogJ-LogV on the vertical axis (LogJ₁ -LogJ₂ )/(LogV₁ -LogV₂ ) is the "power" of the J-V characteristic, and takes V on the horizontal axis. Here, J means current density (A/cm)² ), the value obtained by dividing the current value (A) by the effective area of the above electrode. J₁ , J₂ V₁ V₂ To measure the current density of points 1, 2 and the applied voltage value. The average power of the range from 2 V to 3 V is 2.5, and the maximum and minimum of the power of this interval is ±0.5 with respect to the average value. Therefore, the semiconductor layer can be regarded as having a tail at the lower end of the conductivity. The semiconductor of the energy level is applicable to the above formula (5). According to the above formula (5), "power" 2.5 is equal to I+1, I=Tc/T, and the actual temperature at the time of measurement is 300 K, so the characteristic temperature is found to be 450 K. (3) Determination of withstand voltage As described above, the withstand voltage can be obtained by measuring the breakdown voltage (V) and dividing by the length of L. In the case of the Ben Schottky barrier diode, it will reach 1×10 when sweeping the reverse voltage.^-3 The initial voltage value of the current value of A is defined as the breakdown voltage. When using HVSMU, when applying voltage to the reverse direction, the current value at -62 V is 1 × 10^-3 A, so the breakdown voltage is defined as -62 V. The withstand voltage of unit L is the absolute value obtained by dividing by 200 nm, that is, 3.1 MV/cm. (4) Determination of forward conduction resistance Ron@2 V As described above, the HCSMU using the above device is applied to 0 V to 2 V by applying a forward bias to the element (a positive voltage is applied to the HCSMU). Measuring the current density when applying 2 V_2V , defined as positive conduction resistance Ron@2 V=2[V]/J_{2 V} [A/cm² ]Calculation. (5) Determination of leakage current value @-5 V Using HVSMU, the current density when a voltage of -5 V was applied in the reverse direction was obtained. Since it is -5.0×10^-8 A/cm² Therefore, take the absolute value and determine the leakage current value @-5 V is 5.0×10^-8 A/cm² . (Examples 2 to 5, 9, and 18 to 19) A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Tables 2-1 and 2-2. The results are disclosed in Tables 2-1, 2-2. Further, the semiconductor elements of the embodiments satisfy the formula (I). Example 6 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 2-1. The results are disclosed in Table 2-1. Further, the semiconductor element of this embodiment satisfies the formula (I). In this embodiment, the ohmic electrode of Example 1 was changed from Mo to Ti. When L was evaluated, it was confirmed that the TEM image contrast including InGaZnO was shorter than 200 nm by the oxygen removal of the Ti electrode, and the thickness of the semiconductor layer was 180 nm. Example 7 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 2-1. The results are disclosed in Table 2-1. Further, the semiconductor element of this embodiment satisfies the formula (I). In the embodiment, when Pd is sputtered when the Schottky electrode is fabricated, Ar and O are not used.₂ The mixed gas was sputtered and only 70 Ar was used to form a film. As a result, at the InGaZnO/PdO interface, the peak from oxygen in the Pd spectrum of XPS from the InGaZnO/PdO interface is accompanied by a decrease in the oxygen concentration contained in InGaZnO, and it is impossible to determine that Pd contains oxygen. Further, in the region where Pd is observed by the EDX image, there is clearly no region where the contrast of the TEM image can be seen. Thus, it was judged that the Schottky electrode was a layer containing Pd of about 70 nm. As shown in Table 2-1, it is denoted as Pd. Example 8 An n-type Si substrate (4 inches in diameter and 250 μm in thickness) having a resistivity of 0.001 Ω·cm was mounted on a sputtering apparatus (manufactured by CANON ANELVA: E-200S), and a laminated electrode below the film was formed as an ohmic electrode layer. . However, for the reverse side of the substrate, Ti100 nm/Au50 nm treatment was performed in order to eliminate the contact resistance with the probe device during the measurement. First, 15 nm of Ti is formed in a DC50 W, Ar environment, and then 50 nm of Ni is formed in a DC 50 W, Ar environment. Finally, as a Schottky electrode, a film is formed in a DC 50 W, Ar environment. Mo of nm. Then, the substrate was placed in a sputtering apparatus (manufactured by ULVAC: CS-200) together with a semiconductor region mask, and InGaZnO (1:1:1) at 200 nm was formed as a withstand voltage layer (semiconductor layer). Film formation conditions are set to: DC300 W, Ar and H₂ O mixed gas environment (H₂ O concentration: 1% by volume). The sputtering target-substrate distance (TS interval) was set to 80 mm. The substrate was taken out and annealed in an electric furnace at 300 ° C for 1 hour in the air. The substrate and the electrode were again placed in a sputtering apparatus with a region mask (pore diameter: 50 μm), and a Pd target was placed in a mixed gas of argon gas and oxygen gas to form a 50 nm PdO as a Schottky electrode ( 50 μm in diameter). Thereafter, a Pd electrode of 100 μm was formed using the same mask. The film formation conditions were all set to DC100 W and Ar environment. As a final treatment, an under-tempering treatment at 200 ° C for 1 hour was carried out. Further, the element configuration is such that, as shown in FIG. 2, an ohmic electrode is provided on the lower portion of the semiconductor layer, and when the peripheral portion of the Schottky electrode is perpendicular to the ohmic electrode surface, the ohmic electrode surface is in the above-mentioned manner. The inside of the vertical line. The obtained semiconductor element was evaluated in the same manner as in Example 1. The results are disclosed in Table 2-1. Further, the semiconductor element of this embodiment satisfies the formula (I). Example 10 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 2-1. The results are disclosed in Table 2-1. Further, the semiconductor element of this embodiment satisfies the formula (I). In this example, the annealing temperature after film formation of the semiconductor layer was raised to 500 ° C, and as a result, it was found that the diffraction image at the time of cross-sectional TEM measurement was changed. The diffracted spot is wider but exists, and the spot position changes with respect to the measurement site of the complex point. From this, it was judged that the semiconductor film was polycrystalline. Further, it was observed that the thickness of the semiconductor layer also changed to 190 nm with crystallization. Example 11 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 2-2. The results are disclosed in Table 2-2. Further, the semiconductor element of this embodiment satisfies the formula (I). In this embodiment, the Schottky electrode uses Ru. The composition of Si/Ti/Ru/RuO/InGaZnO/Mo was formed. RuO is formed by sputtering using a mixed gas of Ar and oxygen. Example 12 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 2-2. The results are disclosed in Table 2-2. Further, the semiconductor element of this embodiment satisfies the formula (I). In this embodiment, the Schottky electrode uses Ni. A structure of Si/Ti/Ni/NiO/InGaZnO/Mo was formed. NiO is formed by sputtering using a mixed gas of Ar and oxygen. Example 13 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 2-2. The results are disclosed in Table 2-2. Further, the semiconductor element of this embodiment satisfies the formula (I). In this embodiment, the semiconductor layer was sputtered using an InSnZnO (1:1:1) target. Example 14 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 2-2. The results are disclosed in Table 2-2. Further, the semiconductor element of this embodiment satisfies the formula (I). Use Ga₂ O₃ The target sputters the semiconductor layer. Since it is an insulating sputtering target, it is DC300 W and uses RF (Radio Freqency) 300 W film forming conditions. Example 15 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 2-2. The results are disclosed in Table 2-2. Further, the semiconductor element of this embodiment satisfies the formula (I). In this embodiment, the environment in which the semiconductor layer was formed into a film was set to Ar 100% by volume, and the temperature at which the semiconductor was annealed was set to 150 ° C in the band. Use Ga₂ O₃ The target sputters the semiconductor layer. Since it is an insulating sputtering target, it becomes DC300 W and uses the film formation conditions of RF300W. Example 16 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 2-2. The results are disclosed in Table 2-2. Further, the semiconductor element of this embodiment satisfies the formula (I). In this embodiment, the semiconductor layer is sputtered using an InAlO (93:7) target. The obtained cross-sectional TEM measurement was found to change the diffraction image. The diffracted spot is wide but exists, and the position of the spot changes with respect to the measurement site of the complex point. However, even if a diffraction image was obtained in the film thickness direction, no change in the position of the light spot was observed. From this, it was judged that the semiconductor film was polycrystalline (columnar). Example 17 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 2-2. The results are disclosed in Table 2-2. Further, the semiconductor element of this embodiment satisfies the formula (I). In this embodiment, the semiconductor layer is sputtered using an InGaO (1:1) target. Further, in order to obtain crystallinity, the annealing temperature was raised to 600 °C. As a result, in the same manner as in the eighth embodiment, the PdO Schottky electrode was placed on the upper portion of the semiconductor layer as shown in FIG. The purpose is to reduce PdO to Pd by high temperature to suppress a decrease in Schottky barrier property. The obtained cross-sectional TEM measurement was found to change the diffraction image. The diffracted spot is wide but exists, and the position of the spot changes with respect to the measurement site of the complex point. However, even if a diffraction image was obtained in the film thickness direction, no change in the position of the light spot was observed. From this, it was judged that the semiconductor film was polycrystalline (columnar). Example 20 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 2-2. The results are disclosed in Table 2-2. In this embodiment, a configuration is provided in which a Schottky electrode is provided on the upper portion of the semiconductor layer as shown in FIG. 3, and an ohm is formed when the peripheral portion of the Schottky electrode is perpendicular to the ohmic electrode surface. The electrode faces are on the outer side of the above-mentioned vertical line. Although the formula (I) was satisfied, a decrease in withstand voltage and an increase in leakage current were observed as compared with Example 8. [table 2-1] [Table 2-2] Comparative Example 1 A semiconductor device was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 3. The results are revealed in 3. In this embodiment, the environment at the time of film formation of InGaZnO was set to Ar 100% by volume. Further, annealing after semiconductor film formation was not performed. As a result, the carrier concentration is outside the range of the formula (I). Moreover, the withstand voltage is also 0.1 MV/cm, which makes it difficult to adapt to power use characteristics. The leakage current is higher than the compliance current of the measuring device by 100 mA when -5 V is applied. It is impossible to make a measurement. Therefore, it is recorded as >1.0×10 in Table 3.^-3 A. Comparative Example 2 A semiconductor device was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 3. The results are disclosed in Table 3. In this embodiment, the film formation of the Pd/PdO layer is omitted, and the Schottky electrode becomes Ti. As a result, although the rectification characteristics were observed, the carrier concentration became outside the range of the formula (I). Further, the leakage current is high and the withstand voltage is also 0.3 MV/cm, which makes it difficult to adapt to power use characteristics. Comparative Example 3 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film formation conditions were changed as shown in Table 3. The results are disclosed in Table 3. In this embodiment, In is used₂ O₃ The target sputters the semiconductor layer. The obtained cross-sectional TEM measurement was found to change the diffraction image. The diffracted spot is wide but exists, and the position of the spot changes with respect to the measurement site of the complex point. However, even if a diffraction image was obtained in the film thickness direction, no change in the position of the light spot was observed. From this, it was judged that the semiconductor film was polycrystalline (columnar). Regarding the electrical characteristics, the carrier concentration was high, and the produced Schottky diode did not have a rectification ratio, and the carrier concentration could not be measured by CV measurement. Further, since the positive power is maintained at a value of 2 or less in the range of 2 to 3 V, the relationship of the judgment formula (5) is not satisfied, and the characteristic temperature cannot be evaluated. A decrease in withstand voltage and an increase in leakage current were observed. [table 3] [Industrial Applicability] The semiconductor element of the present invention can be used for a Schottky barrier diode and a junction transistor. Furthermore, these can be used in electronic circuits and used in various electric machines. The embodiments and/or the embodiments of the present invention are described in detail above, and the embodiments and/or embodiments of the present invention may be readily practiced without departing from the novel teachings and effects of the invention. Or the embodiment imposes a variety of changes. Accordingly, such various modifications are intended to be included within the scope of the present invention. The contents of the Japanese application form which is the basis of the priority of Paris in this case are all cited herein.

1‧‧‧Semiconductor components
2‧‧‧Semiconductor components
3‧‧‧Semiconductor components
4‧‧‧Semiconductor components
10‧‧‧Schottky electrode
12‧‧‧Outside the Schottky electrode
20‧‧‧ Ohmic electrode
22‧‧‧Ohm electrode surface
30‧‧‧Semiconductor layer
40‧‧‧Electrically conductive substrate
50‧‧‧Insulation
60‧‧‧Insulating substrate
A‧‧‧ vertical line

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present invention. Fig. 3 is a schematic perspective view showing a semiconductor device according to another embodiment of the present invention. Fig. 4 is a schematic perspective view showing a semiconductor device according to another embodiment of the present invention. Fig. 5 is a view for explaining an electrode surface of the semiconductor element of Fig. 2.

1‧‧‧Semiconductor components

10‧‧‧Schottky electrode

20‧‧‧ Ohmic electrode

30‧‧‧Semiconductor layer

40‧‧‧Electrically conductive substrate

Claims (16)

A semiconductor device comprising: a pair of ohmic electrodes and a Schottky electrode; and a semiconductor layer connected to the ohmic electrode and the Schottky electrode, and satisfying the following formula (I): 15] (wherein n is a carrier concentration (cm ^-3 ) of the semiconductor layer, ε is a dielectric constant (F/cm) of the semiconductor layer, and _Ve is a positive relationship between the ohmic electrode and the Schottky electrode To the effective voltage (V), q is the basic charge (C), and L is the distance (cm) between the above ohmic electrode and the above Schottky electrode. The semiconductor device of claim 1, wherein the semiconductor layer comprises a metal oxide. The semiconductor device according to claim 2, wherein the metal oxide contains one or more elements selected from the group consisting of In, Zn, Ga, Sn, and Al. The semiconductor device according to claim 1 or 2, wherein the Schottky electrode comprises one selected from the group consisting of Pd, Mo, Pt, Ir, Ru, W, Cr, Re, Te, Mn, Os, Fe, Rh, Co, and Ni. More than one metal or an oxide thereof. The semiconductor element according to claim 1 or 2, wherein the ohmic electrode comprises a metal selected from the group consisting of Ti, Mo, Ag, In, Al, W, Co, and Ni or a compound thereof. The semiconductor element of claim 1 or 2, wherein the semiconductor layer comprises amorphous or polycrystalline. The semiconductor element according to claim 1 or 2, wherein the semiconductor layer has a characteristic temperature of 1500 K or less. The semiconductor element according to claim 1 or 2, wherein the ohmic electrode surface is located inside the perpendicular line when the peripheral portion of the Schottky electrode is perpendicular to the ohmic electrode surface. The semiconductor element of claim 1 or 2 has a withstand voltage of 0.5 MV/cm or more. A semiconductor element according to claim 1 or 2, wherein said semiconductor layer is interposed between said ohmic electrode and said Schottky electrode. The semiconductor device of claim 10, further comprising a conductive germanium substrate, wherein the ohmic electrode or the Schottky electrode is in contact with the conductive germanium substrate. A semiconductor element according to claim 1 or 2, wherein said ohmic electrode is present on a surface of said one of said semiconductor layers at a distance from said Schottky electrode. A Schottky barrier diode characterized by using the semiconductor device according to any one of claims 1 to 12. A junction transistor characterized by using the semiconductor element according to any one of claims 1 to 12. An electronic circuit characterized by using a semiconductor element according to any one of claims 1 to 12, a Schottky barrier diode of claim 13, or a junction transistor as claimed in claim 14. An electrical machine, an electronic machine, a vehicle or a power mechanism, characterized in that an electronic circuit as claimed in claim 15 is used.