TWI769929B - Semiconductor components and electrical equipment using the same - Google Patents

Semiconductor components and electrical equipment using the same Download PDF

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TWI769929B
TWI769929B TW110135936A TW110135936A TWI769929B TW I769929 B TWI769929 B TW I769929B TW 110135936 A TW110135936 A TW 110135936A TW 110135936 A TW110135936 A TW 110135936A TW I769929 B TWI769929 B TW I769929B
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霍間勇輝
関谷隆司
笘井重和
川嶋絵美
上岡義弘
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日本商出光興產股份有限公司
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Abstract

本發明係一種半導體元件1，其特徵在於：具有隔開之一對歐姆電極20及肖特基電極10、以及與上述歐姆電極20及上述肖特基電極10相接之半導體層30，且滿足下述式(I)(式中，n為上述半導體層之載子濃度(cm-3 )，ε為上述半導體層之介電常數(F/cm)，Ve 為上述歐姆電極與上述肖特基電極之間之正向有效電壓(V)，q為基本電荷(C)，L為上述歐姆電極與上述肖特基電極之間之距離(cm))。

Figure 110135936-A0101-11-0001-1
The present invention relates to a semiconductor element 1, which is characterized by having a pair of ohmic electrodes 20 and Schottky electrodes 10 separated from each other, and a semiconductor layer 30 in contact with the ohmic electrodes 20 and the Schottky electrodes 10, and satisfies the requirement The following formula (I) (wherein, n is the carrier concentration (cm -3 ) of the semiconductor layer, ε is the dielectric constant (F/cm) of the semiconductor layer, and V e is the ohmic electrode and the Schott The forward effective voltage (V) between the base electrodes, q is the base charge (C), and L is the distance (cm) between the ohmic electrode and the Schottky electrode.
Figure 110135936-A0101-11-0001-1

Description

半導體元件及使用其之電氣機器Semiconductor components and electrical equipment using the same

本發明係關於一種半導體元件以及使用其之肖特基能障二極體、接面場效電晶體、電子電路及電氣機器。The present invention relates to a semiconductor element and a Schottky energy barrier diode using the same, a junction field effect transistor, an electronic circuit and an electrical machine.

作為實現大電流、低耗電之功率半導體材料，以Si為代表，可列舉SiC、GaN等新材料。又，氧化鎵、金剛石亦作為下一代材料而受到關注。另一方面，因該等材料基本上係以單晶形式加以利用，故而具有難以於異質基板上單晶生長，基板之選擇受到限制之缺點。 關於SiC，作為功率半導體較佳之結晶構造為4H-SiC，且絕緣破壞電場實現了3 MV/cm以上。然而，因晶格之失配較大，故難以於Si上使缺陷較少之單晶良率較好地磊晶生長。若為3C-SiC，則可藉由對Si晶圓實施微細加工，或使用Si(211)面而進行磊晶生長，但帶隙變窄，故絕緣破壞電場限於1.2 MV/cm。又，GaN亦與4H-SiC同樣地絕緣破壞電場為3 MV/cm以上，且為實現量產而嘗試了於Si上進行結晶生長。然而，雖然就與Si之晶格失配之方面而言並未達到如SiC般之程度，但若不介隔AIN等緩衝層，則結晶難以生長，於量產性方面存在問題。 因此，正在對如專利文獻1般之實現與使用多晶或非晶之氧化物半導體之異質基板匹配之功率器件展開研究。通常，如非專利文獻1所揭示，於單極之功率器件中，為獲得最低導通電阻，下述式之關係成立，且若耐壓設計及半導體材料種類確定，則最佳載子濃度得以確定。然而，非晶或多晶半導體難以控制載子濃度。 [數1]

Figure 02_image003
(式中，εs 為材料之介電常數，Ec 為最大絕緣破壞電場，q為基本電荷，BV為作為設計值之耐壓，ND 為載子濃度) 先前技術文獻 專利文獻 專利文獻1：WO2015/025499A1 非專利文獻 非專利文獻1：“ Fundamentals of Power Semiconductor Devices”, B. Jayant Baliga, Springer Science & Business Media, 2010/04/02As a power semiconductor material that realizes high current and low power consumption, Si is represented, and new materials such as SiC and GaN can be cited. In addition, gallium oxide and diamond are also attracting attention as next-generation materials. On the other hand, since these materials are basically used in the form of single crystals, it is difficult to grow single crystals on heterogeneous substrates, and the choice of substrates is limited. Regarding SiC, the crystal structure that is preferable as a power semiconductor is 4H-SiC, and the dielectric breakdown electric field is 3 MV/cm or more. However, due to the large lattice mismatch, it is difficult to epitaxially grow a single crystal with fewer defects on Si with better yield. In the case of 3C-SiC, epitaxial growth can be performed by microfabricating Si wafers or using Si (211) planes, but the band gap is narrowed, so the dielectric breakdown electric field is limited to 1.2 MV/cm. In addition, GaN also has a dielectric breakdown electric field of 3 MV/cm or more like 4H-SiC, and attempts have been made to grow crystals on Si in order to achieve mass production. However, although the lattice mismatch with Si is not as high as that of SiC, if a buffer layer such as AIN is not interposed, it is difficult to grow crystals, and there is a problem in mass productivity. Therefore, as in Patent Document 1, research is being conducted on a power device that realizes matching with a heterogeneous substrate using a polycrystalline or amorphous oxide semiconductor. Generally, as disclosed in Non-Patent Document 1, in a unipolar power device, in order to obtain the lowest on-resistance, the following relationship is established, and if the withstand voltage design and the type of semiconductor material are determined, the optimal carrier concentration can be determined . However, amorphous or polycrystalline semiconductors have difficulty controlling the carrier concentration. [Number 1]
Figure 02_image003
(In the formula, εs is the dielectric constant of the material, Ec is the maximum dielectric breakdown electric field, q is the basic charge, BV is the withstand voltage as a design value, and N D is the carrier concentration) PRIOR ART DOCUMENT Patent Document Patent Document 1 : WO2015/025499A1 Non-patent literature Non-patent literature 1: "Fundamentals of Power Semiconductor Devices", B. Jayant Baliga, Springer Science & Business Media, 2010/04/02

本發明之目的在於，提供一種無需初始載子濃度控制之高耐壓且低電阻之半導體元件。 本發明者等人針對難以進行初始載子之濃度調整之問題進行努力研究，結果發現，只要半導體層與電極滿足特定之關係式，則根據與先前之單極功率器件相關之設計指南不同之動作原理，可不依賴於載子濃度而利用外因性載子，而獲得高耐壓且低電阻之半導體元件，從而完成了本發明。 根據本發明，提供以下之半導體元件等。 1.一種半導體元件，其特徵在於： 具有隔開之一對歐姆電極及肖特基電極、以及 與上述歐姆電極及上述肖特基電極相接之半導體層，且 滿足下述式(I)。 [數2]

Figure 02_image005
(式中，n為上述半導體層之載子濃度(cm-3 )，ε為上述半導體層之介電常數(F/cm)，Ve 為上述歐姆電極與上述肖特基電極之間之正向有效電壓(V)，q為基本電荷(C)，L為上述歐姆電極與上述肖特基電極之間之距離(cm)) 2.如1之半導體元件，其特徵在於：上述半導體層包含金屬氧化物。 3.如2之半導體元件，其特徵在於：上述金屬氧化物含有選自In、Zn、Ga、Sn及Al中之一種以上之元素。 4.如1至3中任一項之半導體元件，其特徵在於：上述肖特基電極包含選自Pd、Mo、Pt、Ir、Ru、W、Cr、Re、Te、Mn、Os、Fe、Rh、Co及Ni中之一種以上之金屬或其氧化物。 5.如1至4中任一項之半導體元件，其特徵在於：上述歐姆電極包含選自Ti、Mo、Ag、In、Al、W、Co及Ni中之一種以上之金屬或其化合物。 6.如1至5中任一項之半導體元件，其特徵在於：上述半導體層包含非晶或多晶。 7.如1至6中任一項之半導體元件，其特徵在於：上述半導體層之特性溫度為1500 K以下。 8.如1至7中任一項之半導體元件，其特徵在於：於自肖特基電極之外周部向歐姆電極面劃垂線時，上述歐姆電極面處於上述垂線之內側。 9.如1至8中任一項之半導體元件，其特徵在於：耐壓為0.5 MV/cm以上。 10.如1至9中任一項之半導體元件，其特徵在於：上述半導體層介於上述歐姆電極與上述肖特基電極之間。 11.如10之半導體元件，其特徵在於：進而具有導電性矽基板，且 上述歐姆電極或上述肖特基電極與上述導電性矽基板相接。 12.如1至9中任一項之半導體元件，其特徵在於：上述歐姆電極與上述肖特基電極隔開間隔地存在於上述半導體層之一表面上。 13.一種肖特基能障二極體，其特徵在於：使用如1至12中任一項之半導體元件。 14.一種接面場效電晶體，其特徵在於：使用如1至12中任一項之半導體元件。 15.一種電子電路，其特徵在於：使用如1至12中任一項之半導體元件、如13之肖特基能障二極體或如14之接面場效電晶體。 16.一種電氣機器、電子機器、車輛或動力機構，其特徵在於：使用如15之電子電路。 根據本發明，能夠提供一種無需初始載子濃度控制之高耐壓且低電阻之半導體元件。An object of the present invention is to provide a semiconductor element with high withstand voltage and low resistance that does not require initial carrier concentration control. The inventors of the present invention have made diligent studies on the problem that it is difficult to adjust the concentration of the initial carrier, and found that, as long as the semiconductor layer and the electrode satisfy a specific relational expression, the behavior is different from the design guidelines related to the conventional unipolar power device. In principle, it is possible to obtain a semiconductor element with high withstand voltage and low resistance by utilizing external carriers without depending on the carrier concentration, thereby completing the present invention. According to the present invention, the following semiconductor elements and the like are provided. 1. A semiconductor element comprising a pair of ohmic electrodes and Schottky electrodes separated from each other, and a semiconductor layer in contact with the ohmic electrodes and the Schottky electrodes, and satisfying the following formula (I). [Number 2]
Figure 02_image005
(wherein, n is the carrier concentration (cm -3 ) of the above-mentioned semiconductor layer, ε is the dielectric constant (F/cm) of the above-mentioned semiconductor layer, and V e is the positive value between the above-mentioned ohmic electrode and the above-mentioned Schottky electrode To the effective voltage (V), q is the basic charge (C), L is the distance (cm) between the above-mentioned ohmic electrode and the above-mentioned Schottky electrode) 2. The semiconductor element according to 1, characterized in that: the above-mentioned semiconductor layer contains Metal oxide. 3. The semiconductor device according to 2, wherein the metal oxide contains one or more elements selected from the group consisting of In, Zn, Ga, Sn, and Al. 4. The semiconductor device according to any one of 1 to 3, wherein the Schottky electrode comprises a material selected from the group consisting of Pd, Mo, Pt, Ir, Ru, W, Cr, Re, Te, Mn, Os, Fe, One or more metals of Rh, Co and Ni or their oxides. 5. The semiconductor device according to any one of 1 to 4, wherein the ohmic electrode comprises one or more metals selected from Ti, Mo, Ag, In, Al, W, Co and Ni or a compound thereof. 6. The semiconductor device according to any one of 1 to 5, wherein the semiconductor layer comprises amorphous or polycrystalline. 7. The semiconductor element according to any one of 1 to 6, wherein the characteristic temperature of the semiconductor layer is 1500 K or lower. 8. The semiconductor device according to any one of 1 to 7, wherein when a vertical line is drawn from the outer peripheral portion of the Schottky electrode to the ohmic electrode surface, the ohmic electrode surface is located inside the vertical line. 9. The semiconductor element according to any one of 1 to 8, wherein the withstand voltage is 0.5 MV/cm or more. 10. The semiconductor device according to any one of 1 to 9, wherein the semiconductor layer is interposed between the ohmic electrode and the Schottky electrode. 11. The semiconductor device according to 10, further comprising a conductive silicon substrate, and the ohmic electrode or the Schottky electrode is in contact with the conductive silicon substrate. 12. The semiconductor element according to any one of 1 to 9, wherein the ohmic electrode and the Schottky electrode are present on one surface of the semiconductor layer with a space therebetween. 13. A Schottky energy barrier diode, characterized by using the semiconductor element according to any one of 1 to 12. 14. A junction field effect transistor, characterized by using the semiconductor element according to any one of 1 to 12. 15. An electronic circuit, characterized by using the semiconductor element of any one of 1 to 12, the Schottky barrier diode of 13, or the junction field effect transistor of 14. 16. An electrical machine, electronic machine, vehicle or powertrain, characterized in that the electronic circuit as described in 15 is used. According to the present invention, it is possible to provide a semiconductor element with high withstand voltage and low resistance that does not require initial carrier concentration control.

本發明之半導體元件具有隔開之一對歐姆電極及肖特基電極、以及與歐姆電極及肖特基電極相接之半導體層，且滿足下述式(I)。 [數3]

Figure 02_image007
(式中，n為上述半導體層之載子濃度(cm-3 )，ε為上述半導體層之介電常數(F/cm)，Ve 為上述歐姆電極與上述肖特基電極之間之正向有效電壓(V)，q為基本電荷(1.602×10-19 C)，L為上述歐姆電極與上述肖特基電極之間之距離(cm)) n之下限可為0，但較佳為1×1010 以上。 更佳為滿足以下之式(I-1)，進而較佳為滿足以下之式(I-2)。 [數4]
Figure 02_image009
[數5]
Figure 02_image011
於上述式中，載子濃度係藉由CV(capacitance-voltage，電容-電壓)測定，且使用下述式而算出(參照APPLIED PHYSICS LETTERS,101,113505(2012))。 [數6]
Figure 02_image013
A：肖特基電極及歐姆電極重複之部分之面積(cm2 ) C：所測定出之電容值(F) εs ：相對介電常數(-) ε0 ：真空之介電常數(8.854×10-14 F/cm) Ndepl ：載子濃度(cm-3 ) Vbi ：內建電壓(V) k：玻耳茲曼常數(8.617×10-5 eV/K) T：測定時之試樣溫度(K) q：基本電荷(1.602×10-19 C) V：施加電壓(V) L可藉由實施例中揭示之方法求出。 Ve 如下所述般，可為0.1 V。 關於介電常數ε，只要確定半導體種類之組成及晶系，則可利用文獻值之相對介電常數，根據相對介電常數及真空之介電常數之乘積而確定。又，於文獻中之報告例較少或根據報告例不同差異較大之情形時，亦可進行實際測定。於進行實際測定之情形時，可利用如下方法算出，即，根據CV測定之膜厚依存性，測定3點以上之膜厚(L)之電容值，若於縱軸對C/A進行繪圖，於橫軸對1/L進行繪圖，則其斜率成為介電常數ε。 為了使半導體元件滿足式(I)，降低半導體層中之載子濃度。具體而言，降低半導體中之摻雜劑濃度。例如，於如氧化物半導體般，存在於半導體中之氫原子或氧缺陷作為摻雜劑發揮功能之半導體之情形時，形成缺陷較少且膜密度較高之膜對降低載子濃度有效。 圖1係本發明之一實施形態之半導體元件之概略剖視圖。 該半導體元件1(立式)依序具有肖特基電極10、半導體層30、歐姆電極20。進而，於肖特基電極10之與半導體層30側為相反之側具有導電性基板40。 圖2係本發明之其他實施形態之半導體元件之概略剖視圖。 該半導體元件2(立式)依序具有肖特基電極10、半導體層30、歐姆電極20。進而，於歐姆電極20之與半導體層30側為相反之側具有導電性基板40。又，歐姆電極20之兩側具有絕緣層50，以歐姆電極20與兩側之絕緣層50形成1層。圖3之半導體元件3與圖2之元件2僅歐姆電極20之寬度較寬這一情況不同。 圖4係作為本發明之其他實施形態之半導體元件之概略立體圖。 該半導體元件4(橫置式)於半導體層30之對向之第1及第2面中之第1面之上，肖特基電極10與歐姆電極20隔開間隔地配置。進而，於半導體層30之第2面上具有絕緣性基板60。 於滿足上述式(I)之本發明之半導體元件中，半導體層之初始載子濃度較小，外因性載子作為導電之主因子發揮功能。半導體層之阱密度較小，不妨礙外因性載子之傳導。 再者，於專利文獻1中，存在下述式之關係，基於先前之單極功率器件之載子濃度設計指南，於載子濃度之控制性上存在問題。 [數7]
Figure 02_image015
(式中，n、ε、Ve 、q及L與式(I)相同) 本發明之半導體元件之反向漏電流較小，正向導通電阻較低，可提取大電流。又，即便使用廉價之矽基板或金屬基板作為導電性基板，亦表現出良好之整流特性。進而，即便以濺鍍等生產性優異之方式對氧化物半導體層製膜，亦表現出良好之整流特性。本發明之半導體元件尤其於立式肖特基能障二極體用途中優異。 ＜關於式(I)＞ 通常於不存在載子之絕緣體中，下述式(1)成立。 Jins ＝(9/8)με(V2 /L3 ) (1) Jins ：電流密度(A/cm2 ) μ：遷移率(cm2 /V·s) ε：物質之介電常數(F/cm) V：施加電壓(V) L：電流流經之區域之厚度(cm)。 另一方面，關於存在載子之導電體，下述式(2)成立。 Johm ＝qnμ(V/L)  (2) Johm ：電流密度(A/cm2 ) q：基本電荷(1.602×10-19 C) n：載子濃度(cm-3 ) μ：遷移率(cm2 /V·s) V：施加電壓(V) L：電流流經之區域之厚度(cm)。 於Jins ＝Johm 之條件下，下述式(3)成立。 [數8]
Figure 02_image017
(式中，n、ε、V、q及L與式(1)、(2)相同) 因此，於下述式(4)成立之情形時，意指Jins ＞Johm ，絕緣性傳導之作用較大。即，意指外因性載子作為導電之主因子發揮功能。 [數9]
Figure 02_image019
(式中，n、ε、V、q及L與式(1)、(2)相同) 於以單極表示整流特性之肖特基能障二極體、接面場效電晶體(JFET)、金屬氧化膜半導體場效電晶體(MOSFET)中存在漂移區域，通常，於漂移區域中，上述式(2)之關係成立。於此情形時，施加電壓V意指施加於漂移層之電壓。於上述式(I)中，將Ve 定義為正向有效電壓，但其係指如下電壓，即，於考慮到實際之器件構成之情形時，相對於施加電壓V，去除了用於解除能帶彎曲之內建電壓Vbi 等之作用後之對漂移層之有效電壓。 於肖特基能障二極體、接面場效電晶體(JFET)、金屬氧化膜半導體場效電晶體(MOSFET)等器件中，在半導體層器件之間具有一對歐姆電極及肖特基電極，只要上述式(I)成立，則外因性載子作為電氣傳導之主因子發揮功能。 介電常數ε係半導體之相對介電常數εr 與真空之介電常數ε0 (8.854×10-14 (8.854E-14)[F/cm])之乘積。εr 根據材料不同而為不同參數，但較佳為3～20，更佳為5～16，進而較佳為9～13。若相對介電常數過低，則有外因性載子之注入變少而無法獲得高電流之虞。若相對介電常數過大，則有寄生電容之增加或電流特性產生遲滯之虞。 關於正向有效電壓Ve ，若考慮到實際之正向特性使用時對單極器件之施加電壓通常為0.5 V~1.5 V左右，且內建電壓Vbi 通常為0.7～1.3 V左右，則可將Ve 視為0.1 V左右。基本電荷之值為1.602×10-19 C/個，故若將εr 假設為10，則鑒於式(I)，載子濃度n之上限值係藉由半導體層之一對歐姆電極及肖特基電極之間隔L而確定，如表1所示。 [表1] L(nm) n(cm-3 ) 10 5.47E+17 20 1.37E+17 50 2.19E+16 100 5.47E+15 200 1.37E+15 300 6.07E+14 500 2.19E+14 1000 5.47E+13 2000 1.37E+13 5000 2.19E+12 10000 5.47E＋11 L較佳為10 nm＜L＜100000 nm，更佳為20 nm＜L＜10000 nm，進而較佳為30 nm＜L＜1000 nm，最佳為50 nm＜L＜300 nm。若電極間間隔L過短，則有於耐壓之觀點上產生問題之虞，若L過大，則有電流值降低或於立式元件中半導體層之膜厚增加而導致成膜費時之虞。 L與n較佳為滿足下述式(I-a)所示之關係，更佳為滿足下述式(I-b)所示之關係，進而較佳為滿足下述式(I-c)所示之關係，特佳為滿足下述式(I-d)所示之關係。 [數10]
Figure 02_image021
(式中，n、ε、Ve 、q及L與式(I)相同) 若n過低，則有存在於半導體層內部之阱產生影響而擴散電流之作用變大，電流特性變差之虞。另一方面，若n成為式(I)之εVe /qL2 以上，則漂移電流之作用變大，接近先前之動作特性而難以產生本發明之效果。 ＜半導體元件之耐壓＞ 本發明之半導體元件於半導體層之間具有一對歐姆電極及肖特基電極。與先前之功率器件相比，因設計載子濃度變低，故耐壓VBD 之設計相對於VBD ～Ec L/2而成為VBD ～Ec L，可期待以相同L進行對比，提高2倍左右之耐壓。於此，Ec 為最大絕緣破壞電場，L為電極間長度。 又，於先前之功率器件中，由於初始載子濃度較高，故於施加逆向偏壓時之漏電流較大，於自肖特基電極之外周部(側面)向歐姆電極面劃垂線時，難以取得歐姆電極面內包於來自肖特基面之垂線般之元件構成。於本發明中，半導體層中之初始載子濃度較低，於施加正向電壓時，外因性載子僅注入在自肖特基電極之外周部向歐姆電極面劃垂線時，歐姆電極面內包於來自肖特基面之垂線之範圍內。另一方面，於施加逆向偏壓時，遍及半導體層之整體不存在載子，故因迴繞所致之漏電流之影響較小。 圖5係用於說明圖2之半導體元件之電極面之圖。於圖5中，肖特基電極之外周部係以符號12所示之部分，歐姆電極面係以符號22所示之部分。自肖特基電極之外周部12向歐姆電極面22所劃之垂線以符號A表示。 於立式之功率器件中，通常，半導體層下部為歐姆電極，但於歐姆電極處於自肖特基電極所劃之垂線之內側時，能夠容易地將肖特基電極用於半導體層下部。又，已知於通常之功率器件中使用保護環等電場緩和構造以實現逆向漏電流之減少，藉由此種之構成，可省略或削減成為製程缺點之該等電場緩和構造。 於外因性載子成為支配之單極之功率器件中，如上文所述般耐壓成為VBD ～Ec L，故根據電極間長度L與耐壓VBD 之測定結果可容易地確定絕緣破壞電場。於此，單位L之耐壓相當於絕緣破壞電場。若單位膜厚之耐壓較高，則於設計相同耐壓元件時可減小L，故外因性載子之注入增加，而能夠提供更低電阻之元件。關於單位L之耐壓，較佳為0.5 MV/cm以上，更佳為0.8 MV/cm以上，進而較佳為1.0 MV/cm以上，特佳為3.0 MV/cm以上。單位L之耐壓可藉由測定崩潰電壓(V)，並除以L之長度而求出。例如，於肖特基能障二極體之情形時，在掃引逆向電壓之情形時，將已達到1×10-3 A之電流值之最初之電壓值定義為崩潰電壓。 又，單位L之耐壓可根據半導體層之材料選擇進行調整。於本發明中，在半導體層之材料為帶隙1 eV以上且包含非晶或多晶之半導體層時，可達到0.5 MV/cm以上。於為帶隙2 eV以上之材料時，達到1.0 MV/cm以上，於為帶隙2 eV以上且包含非晶或多晶之半導體層時，可達到3.0 MV/cm以上。 ＜特性溫度＞ 特性溫度係表示非晶或多晶體所特有之傳導帶下端之帶尾能階之特徵的參數，關於在傳導帶下端具有帶尾能階之外因性載子成為支配之半導體，遵循下述式(5)之特性。 [數11]
Figure 02_image023
J：電流密度(A/cm2 ) u：遷移率(cm2 /V·s) Nc ：半導體之有效狀態密度(cm-3 ) Nt ：傳導帶下端部之帶尾能階密度(cm-3 ) ε：物質之介電常數(F/cm) V：施加電壓(V) L：電流流經之區域之厚度(cm) e：基本電荷(1.602×10-19 C) I：Tc/T Tc：特性溫度(K) T：實際溫度(K) 特性溫度Tc係成為Tc＞T之參數，於帶尾能階數較多，妨礙藉由阱而注入之外因性載子之傳導之情形時，成為較大之值。實施電流-電壓測定，根據式(5)可知，Log(J)－Log(V)之曲線之斜率為I＋1，因此，根據斜率求出I，並算出Tc。但是，Tc之值相對於某連續之範圍之施加電壓成為固定之情形成為半導體層具有帶尾能階之指標。較佳為Tc＜1500 K，更佳為Tc＜900 K，進而較佳為Tc＜600 K。若Tc之值較大，則有帶尾能階所捕獲之外因性載子數增加，器件特性高電阻化之虞。 特性溫度可藉由實施電流-電壓測定，根據Log(J)－Log(V)之曲線之斜率而求出。特性溫度可藉由於非晶或多晶半導體中提高原子結構之短距離秩序性而降低。例如，於非晶金屬氧化物半導體之情形時，密度較低之膜有短距離秩序性變低，特性溫度變高之傾向。可確認於藉由濺鍍成膜之非晶金屬氧化物半導體中，密度與成膜條件存在關係。靶-基板距離越近，濺鍍壓力越低，成膜時之基板溫度越高或成膜後之退火溫度越高，或濺鍍成膜時之施加於靶之施加電壓越高，越易於形成高密度之膜。又，於濺鍍成膜時若添加0.1～10體積%之H2 或H2 O作為濺鍍氣體，則易於獲得高密度之膜。若為非晶或多晶半導體層含有選自In、Zn、Ga及Sn中之一種以上之元素之金屬氧化物半導體，則可利用對象性較高之s軌道，故不易受到週期電位之混亂之影響，特性溫度易於變低。 ＜漂移層之積層化(限定於立式之元件)＞ 可獲得如下之半導體元件(立式)，即，具有以成為下述式(6)之載子濃度nL 較低之半導體層(L1 、L2 、…Ln )(nL 及Ln 表示自肖特基電極向歐姆電極計數時，位於第n號之載子濃度較低之層的載子濃度及膜厚)與載子濃度nh 較高之半導體層(d1 、d2 、…dn-1 )(nh 及dn 表示自肖特基電極向歐姆電極計數時，位於第n號之載子濃度較高之層的載子濃度及膜厚)於漂移層上重複之構造。 [數12]
Figure 02_image025
(式中，nL 表示自肖特基電極向歐姆電極計數時位於第n號之載子濃度之較低之層的載子濃度，ε表示第n號之載子濃度較低之半導體層之介電常數，Ve 表示施加於第n號之載子濃度較低之半導體層之有效電壓(可設為Ve ＝0.1 V)，q表示基本電荷，Ln 表示第n號之載子濃度較低之半導體層之膜厚) 較單層之漂移構成而言藉由進行積層而可期待耐壓之提高及電阻值之減少。於此情形時，Ln 較佳為10 nm＜Ln ＜1000 nm，更佳為20 nm＜Ln ＜300 nm，進而較佳為30 nm＜Ln ＜200 nm，特佳為30 nm＜Ln ＜100 nm。有若Ln 過短則差異變大，若Ln 過長則電阻值變高之虞。又，dn 較佳為3 nm＜dn ＜30 nm，更佳為5 nm＜dn ＜10 nm。若dn 過長，則有施加逆向偏壓時空乏層未擴展至自肖特基電極至歐姆電極之全域而於耐壓之觀點上產生問題之虞。若dn 過短，則有未發揮作為Ln 與Ln ＋ 1 之間隔層之作用而未作為積層構成發揮功能之虞。nh 較佳為下述式(6-a)，更佳為下述式(6-b)，進而較佳為下述式(6-c)。 [數13]
Figure 02_image027
(式中，ε表示第n號之載子濃度較高之半導體層之介電常數，Ve 表示施加於第n號之載子濃度較高之半導體層之有效電壓(可設為Ve ＝0.1V)，q表示基本電荷，dn 表示第n號之載子濃度較高之半導體層之膜厚) 若nh 過大，則有於載子濃度較高之半導體層抑制施加逆向偏壓時空乏層之延伸而難以維持耐壓之虞。若nh 過小，則有於正向施加時亦需要向載子濃度較高之層注入外因性載子，結果，複數個載子濃度較低之半導體層作為一個載子濃度較低之層工作而電阻值增高之虞。 與肖特基電極相接者較佳為載子濃度較低之層。 ＜半導體元件之串聯連結＞ 於先前之單極功率器件之耐壓設計中，在施加額定耐壓之電壓時，肖特基金屬側之半導體界面之電場強度達到絕緣破壞電場附近，難以進行半導體元件之連結。例如，於肖特基能障二極體之情形時，即便將600 V耐壓之元件複數個串聯，亦難以獲得600 V以上之耐壓。於本發明之初始載子濃度較低且使用外部注入載子之半導體元件(功率器件)中，在複數個串聯連接之情形時，相應於所連結之個數，耐壓以額定耐壓之乘積而增加。因此，能夠容易地提供所需之耐壓之元件。 ＜半導體元件之構成層＞ (1)半導體層 半導體層並無特別限定，較佳為包含多晶或非晶。又，較佳為包含金屬氧化物半導體，更佳為包含含有選自In、Zn、Ga、Sn及Al中之一種以上之元素之金屬氧化物半導體。若為非晶，則大面積均勻性優異，對施加逆向偏壓時之衝擊離子化降低且耐壓提高有效。若為多晶，則大面積均勻性且傳導特性較佳。由金屬氧化物半導體製造半導體層時，可採用使用燒結體濺鍍靶之大面積性優異之成膜方法。藉由將含有選自In、Zn、Ga、Sn及Al中之一種以上之元素之金屬氧化物半導體利用於半導體層，而可利用金屬元素之s軌道之傳導特性，故即便為非晶、多晶，亦形成軌道重疊且傳導特性優異之半導體層。 金屬氧化物半導體可包含1種或2種以上之金屬氧化物。作為金屬氧化物，可列舉In、Sn、Ge、Ti、Zn、Y、Sm、Ce、Nd、Ga或Al之氧化物等。較理想為包含選自In、Zn、Ga及Sn中之一種以上之元素。 金屬氧化物半導體之金屬本質上可包含選自In、Sn、Ge、Ti、Zn、Y、Sm、Ce、Nd、Ga及Al中之一種以上。又，金屬之例如95原子%以上、98原子%以上、或99原子%以上亦可為選自In、Sn、Ge、Ti、Zn、Y、Sm、Ce、Nd、Ga或Al中之一種以上。 構成金屬氧化物半導體之金屬氧化物較佳為滿足下述式(A)～(C)之原子比。若為此種組成，則可設為高耐壓、低導通電阻。 0≦x/(x＋y＋z)≦0.8     (A) 0≦y/(x＋y＋z)≦0.8     (B) 0≦z/(x＋y＋z)≦1.0     (C) (式中，x表示選自In、Sn、Ge及Ti中之一種以上之元素之原子數， y表示選自Zn、Y、Sm、Ce及Nd中之一種以上之元素之原子數， z表示選自Ga及Al中之一種以上之原子數) 若x超過0.8，則於x為In或Sn之情形時，有金屬氧化物之絕緣性變低，而不易獲得肖特基接合之虞，且於x為Ge或Ti之情形時，有金屬氧化物之絕緣性變高，而成為因歐姆損失所致之發熱之原因之虞。 更佳為上述組成(A)～(C)分別為下述式(A-1)～(C-1)。 0≦x/(x＋y＋z)≦0.7     (A-1) 0≦y/(x＋y＋z)≦0.8     (B-1) z為Ga時：0.02≦z/(x＋y＋z)≦1.0 z為Al時：0.005≦z/(x＋y＋z)≦0.5     (C-1) (式中，x、y及z與上述式(A)～(C)相同) z為Ga時，若低於0.02，則有金屬氧化物中之氧容易脫離，電氣特性不均之虞。 進而較佳為上述組成(A)～(C)分別為下述式(A-2)～(C-2)。 0.1≦x/(x＋y＋z)≦0.5  (A-2) 0.1≦y/(x＋y＋z)≦0.5  (B-2) 0.03≦z/(x＋y＋z)≦0.5 (C-2) (式中，x及y與上述式(A)～(C)相同，z為Ga) 又，上述組成(A)及(C)較佳為分別為下述式(A-3)及(C-3)。 0≦x/(x＋y＋z)≦0.25   (A-3) 0.3≦z/(x＋y＋z)≦1.0  (C-3) (式中，x、y及z與上述式(A)、(C)相同) 構成金屬氧化物半導體層之金屬氧化物可為非晶質亦可為晶質，結晶可為微晶亦可為單晶。較佳為金屬氧化物為非晶質或微晶。於將金屬氧化物設為單晶時，使用以晶種為起點使結晶生長、或MBE(分子束磊晶)或PLD(脈衝雷射沈積)等方法。若於SiO2 表面或金屬表面上結晶生長，則容易產生結晶缺陷，於用作在縱向上通電之器件時，有該結晶缺陷導致不良狀況之虞。於在SiO2 表面或金屬表面上結晶生長之情形時，以粒徑不會變得過大之方式，適當地調整加熱溫度、時間等。 另一方面，於非晶質之情形時，即便存在有懸鍵，由於未作為結晶缺陷而存在，故亦可緩和電氣特性之不均或大幅度之特性劣化。進而，金屬氧化物與Si半導體等之共價鍵不同而離子鍵結性較強，故藉由懸鍵而成之能階接近導電帶或充滿體。因此，金屬氧化物與Si或SiC等相比，因構造所致之遷移率等電氣特性之差較小。若積極地利用金屬氧化物之此種性質，則即便為單晶，亦能夠以較高之良率提供高耐壓且可靠性較高之大電流二極體或開關元件。 於此，所謂「非晶質」係指取得金屬氧化物層之膜厚方向之剖面，於藉由穿透式電子顯微鏡等之電子束繞射方法進行評價之情形時，無法獲得明顯之繞射光點者。較理想為自電子束之照射區域10 nm左右之較寬之區域取得繞射像。所謂明顯之光點係指自繞射像觀察到具有對稱性之繞射點。 又，「非晶質」亦包含具有局部結晶化或微晶化之部分之情形。若將電子束照射至局部結晶化之部分，則有可確認到繞射像之情形。 所謂「微晶結構」係指結晶粒徑之尺寸為次微米以下，且不存在明確之晶界者。 所謂「多晶」係指結晶粒徑之尺寸超過微米尺寸，且存在明確之晶界者。 構成金屬氧化物半導體層之各層之載子濃度通常為1×1011 ～1×1018 cm-3 ，例如為1×1013 ～1×1018 cm-3 。載子濃度例如可藉由CV測定而求出。 二極體所需之性質有高速切換、高耐壓、低導通電阻，只要使用利用金屬氧化物之半導體元件，則可兼具該等特性。其原因在於，金屬氧化物之帶隙原本較寬，且為高耐壓。又，藉由氧缺陷易於成為n型而不易形成p型，此情形亦有利於高速切換。 為了降低導通電阻，只要使之結晶化以提高遷移率即可，但較佳為限於無法形成晶界之程度。晶界中經常會存在孔隙，有形成電場時產生極化，該極化使耐壓性能降低之虞。於耐壓之降低顯著之情形時，較佳為直接以非晶質之形式使用。於作為非晶質而使用之情形時，雖然亦取決於形成金屬氧化物層之元素之種類，但只要將加熱處理條件設定為例如500℃以下且1小時以內即可。藉由以500℃以下之低溫進行加熱，能夠獲得穩定之非晶質狀態。 半導體層之膜厚並無限定，通常為100～8000 nm。 (2)肖特基電極 構成肖特基電極之金屬並無特別限定，較佳為選自Pd、Mo、Pt、Ir、Ru、Ni、W、Cr、Re、Te、Mn、Os、Fe、Rh及Co中之一種以上之金屬(包含合金)或該金屬之氧化物，更佳為選自Pd、Pt、Ir及Ru中之一種以上之金屬(包含合金)或該金屬之氧化物。 又，較佳為與上述氧化物半導體層之耐壓層形成良好之肖特基接觸之金屬或金屬氧化物。更佳為，於與氧化物半導體之組合中，形成較高之肖特基障壁之Pd氧化物、Pt氧化物、Ir氧化物、Ru氧化物。 該等氧化物通常有藉由氧化之狀態而形成半導體或絕緣體之情形，但可藉由選擇組成或製膜條件而維持高載子密度之金屬狀態，且藉由與氧化物半導體之接觸而形成良好之肖特基接觸。為使氧化物形成良好之肖特基電極，較佳為，肖特基電極之載子濃度理想為1018 cm-3 以上。若未達1018 cm-3 ，則有與氧化物半導體層之接觸成為p-n接合，有損高速響應等肖特基二極體之優點之情形。載子濃度例如可藉由霍爾測定等求出。 作為用於獲得金屬氧化物層之製造方法，並無特別限定，可較佳地使用於含氧環境下，進行該金屬靶之反應性濺鍍之方法。 肖特基電極之厚度通常為2 nm～500 nm，較佳為5 nm～200 nm。若過薄，則有受到所接觸之金屬之影響而使正向偏壓時之導通電阻增加之虞。若過厚，則有由於自身之電阻，仍導致正向偏壓時之導通電阻增加，或肖特基界面之平坦性變差、耐壓性降低之虞。 關於肖特基電極，為了降低與基板或電流提取電極之接觸電阻及提高密接性，可於與半導體層相接之側之相反側，積層包含複數個組成不同之金屬或金屬氧化物之層。 (3)歐姆電極 歐姆電極之材料只要為能夠與半導體層進行良好之歐姆連接，則並無特別限定，較佳為選自Ti、Mo、Ag、In、Al、W、Co及Ni中之一種以上之金屬(包含合金)或其化合物(氧化物等)，更佳為選自Mo、Ti、Au、Ag及Al中之一種以上之金屬(包含合金)或其化合物。又，亦可藉由複數個層構成歐姆電極。例如，於與半導體層相接之側使用Mo電極層，為了提取大電流，進而較厚地積層Au或Al等金屬層，該層可作為打線接合之基礎。 歐姆電極之厚度通常為10 nm～5 μm。 (4)製膜方法 各層之製膜方法並無特別限定，可使用如下方法，即，熱CVD(chemical vapor deposition，化學氣相沈積)法、CAT-CVD(catalytic chemical vapor deposition，催化化學氣相沈積)法、光CVD法、霧化CVD法、MO-CVD(Metal-organic Chemical Vapor Deposition，金屬有機化合物化學氣相沈積)法、電漿CVD法等CVD法；MBE(Molecular Beam Epitaxy，分子束磊晶法)、ALD(atomic layer deposition，原子層沈積法)等原子等級控制之製膜方法；離子鍍覆、離子束濺鍍、磁控濺鍍等PVD(Physical Vapor Deposition，物理氣相沈積)法；刮刀法、射出法、擠壓法、熱加壓法、溶膠凝膠法、氣溶膠沈積法等先前公知之使用陶瓷步驟之方法；塗佈法、旋轉塗佈法、印刷法、噴霧法、電鍍法、鍍覆法、膠束電解法等濕式法等。 於選擇金屬氧化物半導體之情形時，半導體層之成膜方法較佳為濺鍍。成膜氣體較佳為自稀有氣體、氧氣、氫氣、水中選擇至少1種以上。濺鍍靶與基板距離(TS間隔)較佳為10 mm～200 mm。若TS間隔過短，則有無法放電之虞。於TS間隔過長之情形時，半導體之膜質變得稀疏，有可能成為特性溫度較大之膜。 (5)基板 半導體元件之基板並無特別限定，可使用公知者。作為基板，可列舉導電性基板、半導體基板、絕緣性基板等。 於立式半導體元件中，如圖1，2所示般，可使用導電性基板。導電性基板可與肖特基電極或歐姆電極接觸而配置。作為導電性基板，可使用矽單晶基板、矽多晶基板、矽結晶基板等先前公知之表面平滑性優異之基板。又，除矽基板以外亦可使用SiC基板、GaN基板、GaAs基板等半導體基板。亦可利用Al基板、Cu基板、Ni基板等導電性優異之金屬基板。若考慮到量產性及成本，則較佳為矽基板。矽基板根據摻雜之有無及種類而存在n型、i型、p型，於縱向上流動電流時，較佳為電阻較小之n型或p型。作為摻雜劑，可使用先前公知之B、P、Sb等。尤其於欲降低電阻之情形時，亦可使用As或紅磷作為摻雜劑。 於橫置式半導體元件中，如圖4所示般，可使用絕緣性基板。絕緣性基板可與半導體層接觸而配置。作為絕緣性基板，只要為具有絕緣性者，則並無特別限制，可於不喪失本發明之效果之範圍內任意地選擇通常所使用者。例如，除石英玻璃、鋇硼矽酸鹽玻璃、鋁硼矽酸鹽玻璃、鋁矽酸鹽玻璃等以熔融法或浮式法所製作之無鹼玻璃基板、陶瓷基板以外，可使用具有可耐受本製作步驟之處理溫度之耐熱性之塑料基板等。 又，亦可使用介電基板作為絕緣性基板。 作為介電基板，可列舉鈮酸鋰基板、鉭酸鋰基板、氧化鋅基板、水晶基板、藍寶石基板等。 又，可使用於不鏽鋼合金等之金屬基板之表面設有絕緣膜或介電膜之基板。又，亦可於基板形成絕緣膜作為基底膜。作為基底膜，可使用CVD法或濺鍍法等，形成氧化矽膜、氮化矽膜、氮氧化矽膜、或氧氮化矽膜等之單層或積層。 關於半導體基板，只要保持表面之平滑性，則材料並無特別限定。 作為半導體基板，可列舉：將載子濃度調整至1×1018 cm-3 以下之Si基板、GaN基板、SiC基板、GaP基板、GaAs基板、ZnO基板、Ga2 O3 基板、GaSb基板、InP基板、InAs基板、InSb基板、ZnS基板、ZnTe基板、金剛石基板等。 半導體基板可為單晶亦可為多晶。又，亦可為部分地含有非晶質基板或非晶質之基板。亦可使用於導電體基板、半導體基板、絕緣性基板上，利用CVD(化學氣相沈積)等方法形成有半導體膜之基板。 作為基板，亦可使用於上述導電性基板、半導體基板或絕緣性基板上，具有由複數個材料構成之任意構造、層構造、電路、配線、電極等之基材。 作為任意構造之材料，例如可列舉形成大規模積體電路(LSI)上之後段製程之金屬、層間絕緣膜等各種金屬或絕緣物之複合材料。 作為層構造之層，並無特別限定，可使用電極層、絕緣層、半導體層、介電層、保護膜層、應力緩衝層、遮光層、電子/電洞注入層、電子/電洞傳輸層、發光層、電子/電洞阻擋層、結晶生長層、密接性提高層、記憶體層液晶層、電容器層、蓄電層等公知之層。 作為電極層，通常可列舉：Al層、Si層、Sc層、Ti層、V層、Cr層、Ni層、Cu層、Zn層、Ga層、Ge層、Y層、Zr層、Nb層、Mo層、Tc層、Ru層、Rh層、Pd層、Ag層、Cd層、In層、Sn層、Sb層、Te層、Hf層、Ta層、W層、Re層、Os層、Ir層、Pt層、Au層、含有該等層之金屬一種以上之合金層、及氧化物電極層等。亦可增加氧化物半導體或Si等半導體之載子濃度，用於電極層。 作為絕緣層，通常可列舉：包含選自由Al、Si、Sc、Ti、V、Cr、Ni、Cu、Zn、Ga、Ge、Y、Zr、Nb、Mo、Tc、Ru、Rh、Pd、Ag、Cd、In、Sn、Sb、Te、Hf、Ta、W、Re、Os、Ir、Pt及Au所組成之群中之一種以上之金屬的氧化物絕緣膜、氮化膜等。 作為半導體層，不限單晶、多晶、非晶之結晶狀態而可廣泛地列舉Si層、GaN層、SiC層、GaP層、GaAs層、GaSb層、InP層、InAs層、InSb層、ZnS層、ZnTe層、金剛石層、Ga2 O3 、ZnO、InGaZnO等氧化物半導體層、稠五苯等有機半導體層等。 作為介電層，可列舉：鈮酸鋰層、鉭酸鋰層、氧化鋅層、水晶基板層、藍寶石層、BaTiO3 層、Pb(Zr,Ti)O3 (PZT)層、(Pb,La)(Zr,Ti)O3 (PLZT)層、Pb(Zr,Ti,Nb)O3 (PZTN)層、Pb(Ni,Nb)O3 -PbTiO3 (PNN-PT)層、Pb(Ni,Nb)O3 -PbZnO3 (PNN-PZ)層、Pb(Mg,Nb)O3 -PbTiO3 (PMN-PT)層、SrBi2 Ta2 O9 (SBT)層、(K,Na)TaO3 層、(K,Na)NbO3 層、BiFeO3 層、Bi(Nd,La)TiOx 層(x＝2.5～3.0)、HfSiO(N)層、HfO2 -Al2 O3 層、La2 O3 層、La2 O3 -Al2 O3 層等。 作為保護膜層之膜，不論無機物或有機物，可列舉絕緣性均優異且水等之透過性較低之膜。作為保護膜層，例如可列舉：SiO2 層、SiNx 層(x＝1.20～1.33)、SiON層、Al2 O3 層等。 作為應力緩衝層，可列舉AlGaN層等。 作為遮光層，例如可列舉包含金屬、金屬-有機物等之黑矩陣層、彩色濾光片層。 作為電子/電洞注入層，可列舉氧化物半導體層、有機半導體層等。 作為電子/電洞傳輸層，可列舉氧化物半導體層、有機半導體層等。 作為發光層，可列舉無機半導體層、有機半導體層等。 作為電子/電洞阻擋層，可列舉氧化物半導體層等。 作為基材，可列舉發電器件、發光器件、感測器、電力轉換器件、運算器件、保護器件、光電子器件、顯示器、記憶體、具有後段製程之半導體器件、蓄電器件等。 層構造之層可為單層亦可為2層以上之層。 本發明之半導體元件可用作功率半導體元件、(整流)二極體元件、肖特基能障二極體元件、靜電放電(ESD)保護二極體、暫態電壓保護(TVS)保護二極體、發光二極體、金屬半導體場效電晶體(MESFET)、接面場效電晶體(JFET)、金屬氧化膜半導體場效電晶體(MOSFET)、肖特基源極/汲極MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor，金屬氧化物半導體場效應電晶體)、雪崩倍增型光電轉換元件、固體拍攝元件、太陽電池元件、光感測器元件、顯示元件、電阻變化記憶體等。由於可提取大電流，故亦尤其適用於功率用途。使用該元件之電子電路可應用於電氣機器、電子機器、車輛、動力機構等。 實施例 實施例1 將電阻率0.001 Ω·cm之n型Si基板(直徑4英吋、厚度250 μm)安裝於濺鍍裝置(CANON ANELVA製造：E-200S)，成膜以下之積層電極。但是對於基板背面，為了消除測定時與探針儀之接觸電阻，而進行Ti　100 nm/Au　50 nm處理。首先使Ti於DC(Direct Current，直流)50 W、Ar環境下成膜15 nm，其次使Pd於DC50 W、Ar環境下成膜50 nm，最後，作為肖特基電極，於DC50 W、Ar與O2 之混合氣體環境下成膜20 nm之PdO。 繼而，將該基板與半導體用區域遮罩一起放置於濺鍍裝置(ULVAC製造：CS-200)，成膜200 nm之InGaZnO(In：Ga：Zn(原子比)＝1：1：1，於下文中將該組成之氧化物記為「InGaZnO(1：1：1)」，關於其他複合氧化物，亦同樣地記載除氧以外之原子比)作為耐壓層(半導體層)。成膜條件設為：DC300 W、Ar與H2 O之混合氣體環境(H2 O濃度：1體積%)。濺鍍靶-基板間距離(TS間隔)設為80 mm。取出該基板，使用電氣爐於空氣中300℃之條件下退火1小時。再次將該基板與電極用區域遮罩(孔直徑50 μm)一起放置於濺鍍裝置之後，成膜150 nm之Mo作為歐姆電極(直徑50 μm)。之後，使用相同遮罩成膜2 μm之Al電極。成膜條件均設為DC100 W、Ar環境。作為最終處理，實施200℃1小時之大氣下熟化處理。 再者，元件構成成為具有如下特徵之構成，即，如圖1所示般，於半導體層下部具有肖特基電極，自肖特基電極之外周部向歐姆電極面劃垂線時，歐姆電極面處於上述垂線之內側。 ＜電極間距離L＞ 電極間距離L係藉由剖面TEM(穿透式電子顯微鏡)像及剖面TEM之EDX(能量分散型X射線光譜法)像而取得。假設將包含InGaZnO之層設為半導體層，將肖特基電極設為PdO層，將歐姆電極設為Mo，將TEM剖面像之對比度基於EDX而與包含InGaZnO之層一致之部位設為半導體層並定義為電極間距離L。又，上述半導體層藉由EDX被Pd與Mo所夾持，且電極間距離L為200 nm。 利用半導體層經逆向偏壓而耗盡，經正向偏壓化而作為電阻層發揮作用這一情況，藉由CV(容量-電壓)測定而確認應該作為半導體發揮作用之厚度於上述L中並無問題。根據施加逆向電壓時之最小之容量值Cmin 及施加正向電壓時之最大之容量值Cmax ，使用C/A＝εr ×ε0 /d之關係式求出Cmin 所對應之膜厚dmin 及Cmax 所對應之膜厚dmax ，其差量相對於L收斂於L±50%之值，故驗證了電極間距離L為200 nm。但是，本成膜方法之InGaZnO(1：1：1)之相對介電常數根據膜厚測定確認為16，故使用εr ＝16。通常報告有InGaZnO之相對介電常數為10～19左右之值。 C：容量值(F) A：電極之有效面積(cm2 ) d：作為半導體發揮作用之膜厚(cm) εr ：相對介電常數 ε0 ：真空之介電常數，8.854E-14[F/cm] 於此，電極之有效面積A表示隔開之一對歐姆電極及肖特基電極中，相對於半導體層相互內包之面積。關於本實施例，可將直徑50 μm之歐姆電極之面積視作A。 再者，於CV測定時，使用下述B1505之CMU(Capacitance Measure Unit，電容測量單元)單元，藉由偏壓T將電壓重疊而實施測定。測定頻率使用1 kHz，且AC振幅設為0.03 V。 ＜電極種類之鑑定＞ 電極種類之鑑定係於上述半導體層之鑑定之後，將夾住半導體層材料之電極種類視作歐姆電極及肖特基電極而實施。藉由剖面EDX像，推定包含Mo及Pd之金屬或金屬化合物為歐姆電極或肖特基電極。根據整流特性之確認，判斷Mo側為歐姆、Pd側為肖特基之電極種類。進而，藉由深度方向XPS(X-ray photoelectron spectroscopy，X射線光電子光譜法)，一面對元件向深度方法進行Ar濺鍍，一面確認XPS光譜。自Mo側向Mo/InGaZnO界面，XPS之Mo光譜中之來自氧之峰值伴隨著InGaZnO所包含之氧濃度平緩地增加，且在遠離InGaZnO之Mo層上著眼於Mo之XPS光譜之9成以上可歸屬於純Mo，故歐姆電極設為Mo。 另一方面，成為如下狀態，即，於InGaZnO/PdO界面上自InGaZnO側向Pd，XPS之Pd光譜中之來自氧之峰值未伴隨InGaZnO所包含之氧濃度平緩地減少，某一定程度之氧包含於Pd中。又，於藉由EDX像觀察到Pd之區域中，明確地看到TEM像之對比度，且於深度方向XPS在純Pd之區域與InGaZnO之區域之間，存在有包含20 nm之電子密度少於純Pd之Pd之區域。由此，肖特基電極設為包含20 nm左右之Pd或PdO之層。如表2-1所示般，記為Pd(PdO)。 ＜結晶性之評價＞ 於觀察半導體層之剖面TEM時藉由電子束繞射方法，進行結晶性之評價。自電子束之照射區域為直徑10 nm以上之區域取得繞射像。於與膜厚方向及剖面平行之方向之複數個點中，繞射像中無法確認到光點形狀，故判斷半導體層為非晶質即非晶。 ＜電氣特性結果＞ 對於所得之元件，使用KEYSIGHT TECHNOLOGIES公司製造之B1505(HVSMU(High-voltage Source Measure Unit，高電壓源測量單元)、HCSMU(Heavy-current Source Measure Unit，強電流源測量單元)、MFCMU(Multi-frequency Capacitance Measure Unit，多頻電容測量單元)、MPSMU(Medium-power Source Measure Unit，中等功率源測量單元)搭載)、偏壓T(N1272A)、電路切換機(N1258A)、及Cascade公司製造之高電壓探針儀EPS 150 TESLA，對電壓(V)-電流特性(J)及電壓(V)-容量(C)特性進行測定。又，對以下之各項目進行評價。將結果示於表2-1。 但是，於測定時上述各SMU或CMU配置於肖特基電極側，且施加偏壓。歐姆電極側為施加0 V之狀態。 (1)載子濃度之測定 使用上述裝置及上述之CV測定取得載子濃度。製作於縱軸取A2 /C2 ，於橫軸取施加電壓V之曲線圖，利用以0 V～2 V之間為起點且直線之斜率與-2/(εr ε0 Ndepl )成正比這一情況，設為載子濃度n＝Ndepl 而求出半導體層之載子濃度。載子濃度如表2-1所示般為1.0×1014 cm-3 。又，可根據CV測定之行為確認半導體為n型。 再者，於CV測定時使用下述B1505之CMU單元，藉由偏壓T將電壓重疊而實施測定。測定頻率使用1 kHz，AC振幅設為0.03 V。 可確認本半導體元件滿足下述式(I)。再者，根據上述內容，介電常數由InGaZnO之相對介電常數16算出，Ve 設為0.1 V，L設為200 nm，從而確定了大小關係。 [數14]
Figure 02_image029
(2)特性溫度之測定 按照前文所述之方法求出特性溫度。利用上述裝置之HCSMU，以向元件施加正向偏壓之方式(HCSMU施加正電壓)施加至0 V～3 V。於縱軸取LogJ－LogV之差量值(LogJ1 －LogJ2 )/(LogV1 －LogV2 )即J-V特性之『冪』，且於橫軸取V。於此，J意指電流密度(A/cm2 )，為測定電流值(A)除以上述電極之有效面積所得之值。J1 、J2 、V1 、V2 為測定點1、2之電流密度及施加電壓值。於2 V～3 V之範圍內平均之『冪』為2.5，本區間之『冪』之最大最小值相對於平均值為±0.5，故視作本半導體層可作為於傳導度下端具有帶尾能階之半導體而適用於前文所述之式(5)。根據前文所述之式(5)，『冪』2.5等於I＋1，I＝Tc/T，測定時之實際溫度為300 K，故求出特性溫度為450 K。 (3)耐壓之確定 如前文所述，耐壓可藉由測定崩潰電壓(V)，並除以L之長度而求出。於本肖特基能障二極體之情形時，在掃引逆向電壓之情形時，將達到1×10-3 A之電流值之最初之電壓值定義為崩潰電壓。使用HVSMU，向逆向施加電壓時，由於-62 V下電流值為1×10-3 A，故將崩潰電壓定義為-62 V。單位L之耐壓為除以200 nm所得之絕對值即3.1 MV/cm。 (4)正向導通電阻Ron@2 V之確定 如前文所述，利用上述裝置之HCSMU，以向元件施加正向偏壓之方式(HCSMU施加正電壓)施加至0 V～2 V。測定施加2 V時之電流密度J2V ，定義為正向導通電阻Ron@2 V＝2[V]/J2 V [A/cm2 ]進行計算。 (5)漏電流值@-5 V之確定 使用HVSMU，求出向逆向施加-5 V之電壓時之電流密度。由於為   -5.0×10-8 A/cm2 ，故取絕對值，確定漏電流值@-5 V為5.0×10-8 A/cm2 。 實施例2～5、9、18～19 除如表2-1，2-2所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-1，2-2。又，該等實施例之半導體元件滿足式(I)。 實施例6 除如表2-1所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-1。又，該實施例之半導體元件滿足式(I)。 於該實施例中，將實施例1之歐姆電極自Mo變更為Ti。 評價L時，可確認藉由Ti電極之奪氧，包含InGaZnO之TEM像對比度短於200 nm，且半導體層之厚度為180 nm。 實施例7 除如表2-1所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-1。又，該實施例之半導體元件滿足式(I)。 於實施例中，在製作肖特基電極時之濺鍍Pd時，未以Ar及O2 混合氣體進行濺鍍，70 nm自始至終僅使用Ar成膜。 其結果，於InGaZnO/PdO界面上自InGaZnO側向Pd，XPS之Pd光譜中之來自氧之峰值伴隨著InGaZnO所包含之氧濃度平緩地減少，無法斷定Pd中含有氧。又，藉由EDX像觀察到Pd之區域中，明確地不存在可看見TEM像之對比度之區域。由此，判斷肖特基電極為70 nm左右之包含Pd之層。如表2-1所示般記為Pd。 實施例8 將電阻率0.001 Ω·cm之n型Si基板(直徑4英吋，厚度250 μm)安裝於濺鍍裝置(CANON ANELVA製造：E-200S)，成膜以下之積層電極作為歐姆電極層。但是對於基板反面，為了消除測定時與探針儀之接觸電阻，而進行Ti100 nm/Au50 nm處理。首先，於DC50 W、Ar環境下成膜15 nm之Ti，其次，於DC50 W、Ar環境下成膜50 nm之Ni，最後，作為肖特基電極，於DC50 W、Ar環境下成膜20 nm之Mo。 繼而，將該基板與半導體用區域遮罩一起放置於濺鍍裝置(ULVAC製造：CS-200)，成膜200 nm之InGaZnO(1：1：1)作為耐壓層(半導體層)。成膜條件設為：DC300 W、Ar與H2 O之混合氣體環境(H2 O濃度：1體積%)。濺鍍靶-基板間距離(TS間隔)設為80 mm。取出該基板，使用電氣爐於空氣中300℃之條件下退火1小時。再次將該基板與電極用區域遮罩(孔直徑50 μm)一起放置於濺鍍裝置之後，將Pd靶置於氬氣與氧氣之混合氣體中成膜50 nm之PdO而作為肖特基電極(直徑50 μm)。之後，使用相同遮罩成膜100 μm之Pd電極。成膜條件均設為DC100 W、Ar環境。作為最終處理，實施200℃1小時之大氣下熟化處理。 再者，元件構成成為具有如下特徵之構成，即，如圖2所示般，於半導體層下部具有歐姆電極，自肖特基電極之外周部向歐姆電極面劃垂線時，歐姆電極面處於上述垂線之內側。 對於所獲得之半導體元件，與實施例1同樣地進行評價。將結果揭示於表2-1。又，該實施例之半導體元件滿足式(I)。 實施例10 除如表2-1所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-1。又，該實施例之半導體元件滿足式(I)。 於該實施例中，將半導體層成膜後之退火溫度上升至500℃，結果發現剖面TEM測定時之繞射像發生變化。繞射光點較寬但存在，光點位置相對於複數點之測定部位發生變化。由此判斷本半導體膜為多晶。又，觀察到伴隨著結晶化，半導體層之厚度亦變化為190 nm。 實施例11 除如表2-2所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-2。又，該實施例之半導體元件滿足式(I)。 於該實施例中，肖特基電極使用Ru。形成Si/Ti/Ru/RuO/InGaZnO/Mo之構成。RuO藉由利用Ar與氧氣之混合氣體所進行之濺鍍而形成。 實施例12 除如表2-2所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-2。又，該實施例之半導體元件滿足式(I)。 於該實施例中，肖特基電極使用Ni。形成Si/Ti/Ni/NiO/InGaZnO/Mo之構成。NiO藉由利用Ar與氧氣之混合氣體所進行之濺鍍而形成。 實施例13 除如表2-2所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-2。又，該實施例之半導體元件滿足式(I)。 於該實施例中，使用InSnZnO(1：1：1)靶對半導體層進行濺鍍。 實施例14 除如表2-2所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-2。又，該實施例之半導體元件滿足式(I)。 使用Ga2 O3 靶對半導體層進行濺鍍。由於為絕緣性之濺鍍靶，故變為DC300 W而使用RF(Radio Freqency，射頻)300 W之成膜條件。 實施例15 除如表2-2所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-2。又，該實施例之半導體元件滿足式(I)。 於該實施例中，將半導體層成膜時之環境設為Ar100體積%，將半導體退火之溫度設為帶域中150℃。使用Ga2 O3 靶對半導體層進行濺鍍。由於為絕緣性之濺鍍靶，故變為DC300 W而使用RF300 W之成膜條件。 實施例16 除如表2-2所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-2。又，該實施例之半導體元件滿足式(I)。 於該實施例中，使用InAlO(93：7)靶對半導體層進行濺鍍。發現所得之剖面TEM測定時之繞射像發生變化。繞射光點較寬但存在，且光點位置相對於複數點之測定部位發生變化。但，即便於膜厚方向取得繞射像，亦未觀察到光點位置之變化。由此判斷本半導體膜為多晶(柱狀)。 實施例17 除表2-2所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-2。又，該實施例之半導體元件滿足式(I)。 於該實施例中，使用InGaO(1：1)靶對半導體層進行濺鍍。又，為獲得結晶性，將退火溫度高溫化至600℃。伴隨此，與實施例8同樣地設為如圖2所示般使PdO肖特基電極位於半導體層上部之構成。其目的在於，藉由高溫將PdO還原成Pd，以抑制肖特基阻隔性降低。 發現所得之剖面TEM測定時之繞射像發生變化。繞射光點較寬但存在，且光點位置相對於複數點之測定部位發生變化。但，即便於膜厚方向取得繞射像，亦未觀察到光點位置之變化。由此判斷本半導體膜為多晶(柱狀)。 實施例20 除如表2-2所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表2-2。 於該實施例中，設為具有如下特徵之構成，即，如圖3所示般，於半導體層上部具有肖特基電極，自肖特基電極之外周部向歐姆電極面劃垂線時，歐姆電極面處於上述垂線之外側。 雖然滿足式(I)，但與實施例8相比觀察到耐壓之降低及漏電流之上升。 [表2-1]    實施例 1 2 3 4 5 6 7 8 9 10 元件構成 半導體層 半導體材料 InGaZnO (1：1：1) InGaZnO (1：1：1) InGaZnO (1：1：1) InGaZnO (1：1：1) InGaZnO (1：1：1) InGaZnO (1：1：1) InGaZnO (1：1：1) InGaZnO (1：1：1) InGaZnO (1：1：1) InGaZnO (1：1：1) 成膜時導入氣體 Ar：99% H2 O：1% Ar：90% H2 O：10% Ar：89% H2 O：l% O2 ：10% Ar：90% O2 ：10% Ar：99% H2 O：l% Ar：99% H2 O：l% Ar：99% H2 O：l% Ar：99% H2 O：1% Ar：99% H2 O：1% Ar：99% H2 O：l% 結晶性 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 多晶 TS間隔(mm) 80 80 80 80 150 80 80 80 80 80 退火溫度(℃) 300 300 300 300 300 300 300 300 400 500 電極間距離L(nm) 200 200 200 200 200 180 200 200 200 190 歐姆電極 Mo Mo Mo Mo Mo Ti Mo Mo Mo Mo 肖特基電極 Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd Pd (PdO) Pd (PdO) Pd (PdO) 元件構成 圖1 圖1 圖1 圖1 圖1 圖1 圖1 圖2 圖1 圖1 評價結果 載子濃度n(cm-3 ) 1.0×1014 5.0×1014 5.0×1013 1.0×1015 6.0×1014 1.0×1015 1.0×1014 1.0×101 4 3.0×1014 2.0×1015 特性溫度(K) 450 550 350 800 700 450 450 500 400 870 耐壓(MV/cm) 3.1 2.1 3.5 1.5 2.3 2.5 0.8 1.8 2.7 1.3 正向導通電阻Ron(Ωcm2 )@2 V 4.0×104 8.0×10-4 3.0×10-4 3.0×10-3 1.0×10-3 2.5×10-4 3.0×10-4 5.0×10-4 3.2×10-4 1.2×10-3 漏電流值(A)@-5 V 5.0×10-8 1.0×10-7 1.0×10-8 5.0×10-7 2.0×10-7 9.0×108 1.0×10-4 1.0×10-6 3.0×107 5.0×104 相對介電常數εr 16 16 16 16 16 16 16 16 16 15 εVe /qL2 (cm-3 ) 2.2×1015 2.2×1015 2.2×1015 2.2×1015 2.2×1015 2.7×1015 2.2×1015 2.2×1015 2.2×1015 2.3×1015 [表2-2]    實施例 11 12 13 14 15 16 17 18 19 20 元件構成 半導體層 半導體材料 InGaZnO (1：1：1) InGaZnO (1：1：1) InSnZnO (1：1：1) Ga2 O3 Ga2 O3 InAlO (93：7) InGaO (1：1) InGaZnO (1：1：1) InGaZnO (1：1：1) InGaZnO (1：1：1) 成膜時導入氣體 Ar：99% H2 O：1% Ar：99% H2 O：1% Ar：99% H2 O：1% Ar：99% H2 O：1% Ar：100% Ar：99% H2 O：1% Ar：99% H2 O：1% Ar：99% H2 O：1% Ar：99% H2 O：1% Ar：99% H2 O：l% 結晶性 非晶 非晶 非晶 非晶 非晶 多晶(柱狀) 多晶(柱狀) 非晶 非晶 非晶 TS間隔(mm) 80 80 80 80 80 80 80 80 80 80 退火溫度(℃) 300 300 300 300 150 300 600 300 300 300 電極間距離L(nm) 200 200 200 200 200 200 200 100 500 200 歐姆電極 Mo Mo Mo Mo Mo Mo In Mo Mo Mo 肖特基電極 Ru (RuO) Ni (NiO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) 元件構成 圖1 圖1 圖1 圖1 圖1 圖1 圖2 圖1 圖1 圖3 評價結果 載子濃度n(cm-3 ) 2.0×1014 3.0×1014 8.0×1013 2.0×1011 3.0×1014 8.0×1014 2.0×1012 1.0×1014 3.0×101 4 1.0×1014 特性溫度(K) 480 500 380 580 850 330 410 400 500 450 耐壓(MV/cm) 2.4 2.1 2.4 3.9 2.2 1.9 1.3 3.3 2.9 0.9 正向導通電阻Ron(Ωcm2 )@2 V 4.5×10-4 5.0×10-4 2.0×10-4 9.0×103 3.0×10-3 8.0×10-5 2.0×10-4 4.0×10-5 9.0×10-3 5.0×10-4 漏電流值(A)@-5 V 5.0×10-6 5.0×10-5 8.0×10-8 1.0×10-9 4.0×10-9 7.0×10-7 1.5×10-6 1.0×10-7 1.0×10-8 5.0×10-5 相對介電常數εr 16 16 12 14 14 11 12 16 16 16 εVe /qL2 (cm-3 ) 2.2×1015 2.2×1015 1.7×1015 1.9×1015 1.9×1015 1.5×1015 1.7×1015 8.8×1015 3.5×1014 2.2×1015 比較例1 除如表3所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於3。 於該實施例中，將InGaZnO之成膜時之環境設為Ar100體積%。又，未實施半導體成膜後之退火。其結果，載子濃度成為式(I)之範圍以外。又，耐壓亦成為0.1 MV/cm，而成為難以適應功率用途之特性。漏電流於施加-5 V時高於測定裝置之依從性電流值100 mA。而無法進行測定。由此，於表3中記為＞1.0×10-3 A。 比較例2 除如表3所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表3。 於該實施例中，省略Pd/PdO層之成膜，肖特基電極成為Ti。結果，雖然觀察到整流特性，但載子濃度成為式(I)之範圍以外。又，漏電流較高，耐壓亦達到0.3 MV/cm，而成為難以適應功率用途之特性。 比較例3 除如表3所示般變更成膜條件以外，與實施例1同樣地製造半導體元件並進行評價。將結果揭示於表3。 於該實施例中，使用In2 O3 靶對半導體層進行濺鍍。發現所得之剖面TEM測定時之繞射像發生變化。繞射光點較寬但存在，且光點位置相對於複數點之測定部位發生變化。但，即便於膜厚方向取得繞射像，亦未觀察到光點位置之變化。由此判斷本半導體膜為多晶(柱狀)。 關於電氣特性，載子濃度較高，所製作之肖特基二極體未獲得整流比，無法以CV測定進行載子濃度測定。又，由於正向之『冪』亦於2～3 V範圍內持續維持2以下之值，故判斷式(5)之關係性不成立，視作無法評價特性溫度。觀察到耐壓之降低及漏電流之上升。 [表3]    比較例 1 2 3 元件構成 半導體層 半導體材料 InGaZnO (1：1：1) InGaZnO (1：1：1) In2 O3 成膜時導入氣體 Ar：100% Ar：99% H2 O：1% Ar：99% H2 O：1% 結晶性 非晶 非晶 多晶(柱狀) TS間隔(mm) 80 80 80 退火溫度(℃) 無 300 300 電極間距離L(nm) 200 200 200 歐姆電極 Mo Mo Mo 肖特基電極 Pd (PdO) Ti Pd (PdO) 元件構成 圖1 圖1 圖1 評價結果 載子濃度n(cm-3 ) 2.0×1017 6.0×1015 - 特性溫度(K) 1300 700 - 耐壓(MV/cm) 0.1 0.3 0.1 正向導通電阻Ron(Ωcm2 )@2 V 6.0×10-5 7.0×10-4 5.0×10-5 漏電流值(A)@-5 V ＞1.0×103 8.0×10-4 ＞1.0×10-3 相對介電常數εr 16 16 10 εVe /qL2 (cm-3 ) 2.2×1015 2.2×1015 1.4×1015 [產業上之可利用性] 本發明之半導體元件可使用於肖特基能障二極體及接面場效電晶體。進而，該等可使用於電子電路，利用於各種電氣機器。 於上述中詳細說明了若干本發明之實施形態及/或實施例，業者在不實質性地脫離本發明之新穎之教導及效果的情況下，可容易地對該等作為示例之實施形態及/或實施例施加多種變更。因此，該等多種變更包含於本發明之範圍。 將成為本案之巴黎優先權之基礎之日本申請案說明書之內容全部引用於此。The semiconductor device of the present invention has a pair of ohmic electrodes and Schottky electrodes separated from each other, and a semiconductor layer connected to the ohmic electrodes and the Schottky electrodes, and satisfies the following formula (I). [Number 3]
Figure 02_image007
(wherein, n is the carrier concentration (cm -3 ) of the above-mentioned semiconductor layer, ε is the dielectric constant (F/cm) of the above-mentioned semiconductor layer, and V e is the positive value between the above-mentioned ohmic electrode and the above-mentioned Schottky electrode to the effective voltage (V), q is the basic charge (1.602×10 -19 C), L is the distance between the ohmic electrode and the Schottky electrode (cm)) The lower limit of n can be 0, but preferably 1×10 10 or more. It is more preferable to satisfy the following formula (I-1), and it is still more preferable to satisfy the following formula (I-2). [Number 4]
Figure 02_image009
[Number 5]
Figure 02_image011
In the above formula, the carrier concentration is measured by CV (capacitance-voltage) and calculated using the following formula (refer to APPLIED PHYSICS LETTERS, 101, 113505 (2012)). [Number 6]
Figure 02_image013
A: The area of the overlapping portion of the Schottky electrode and the ohmic electrode (cm 2 ) C: The measured capacitance value (F) ε s : Relative permittivity (-) ε 0 : The permittivity of vacuum (8.854× 10 -14 F/cm) N depl : carrier concentration (cm -3 ) V bi : built-in voltage (V) k : Boltzmann constant (8.617×10 -5 eV/K) T : Test at the time of measurement Sample temperature (K) q: basic charge (1.602×10 -19 C) V: applied voltage (V) L can be obtained by the method disclosed in the examples. V e may be 0.1 V as described below. Regarding the permittivity ε, as long as the composition and crystal system of the semiconductor species are determined, the relative permittivity of the literature value can be used to determine the product of the relative permittivity and the permittivity of vacuum. In addition, when there are few reported examples in the literature, or when there are large differences among the reported examples, the actual measurement can also be performed. In the case of actual measurement, it can be calculated by the following method. That is, the capacitance value of the film thickness (L) at 3 or more points is measured according to the film thickness dependence of CV measurement, and C/A is plotted on the vertical axis. When 1/L is plotted on the horizontal axis, the slope becomes the dielectric constant ε. In order for the semiconductor element to satisfy the formula (I), the carrier concentration in the semiconductor layer is reduced. Specifically, the dopant concentration in the semiconductor is reduced. For example, in the case of a semiconductor in which hydrogen atoms or oxygen vacancies present in the semiconductor function as dopants like an oxide semiconductor, forming a film with fewer defects and higher film density is effective in reducing the carrier concentration. FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. The semiconductor element 1 (vertical type) has a Schottky electrode 10 , a semiconductor layer 30 , and an ohmic electrode 20 in this order. Furthermore, the conductive substrate 40 is provided on the side opposite to the semiconductor layer 30 side of the Schottky electrode 10 . 2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. The semiconductor element 2 (vertical type) has a Schottky electrode 10 , a semiconductor layer 30 , and an ohmic electrode 20 in this order. Furthermore, the conductive substrate 40 is provided on the side opposite to the semiconductor layer 30 side of the ohmic electrode 20 . In addition, the insulating layers 50 are provided on both sides of the ohmic electrode 20, and one layer is formed by the ohmic electrode 20 and the insulating layers 50 on both sides. The semiconductor element 3 of FIG. 3 is different from the element 2 of FIG. 2 only in that the width of the ohmic electrode 20 is wider. FIG. 4 is a schematic perspective view of a semiconductor element as another embodiment of the present invention. The semiconductor element 4 (horizontal type) is placed on the first surface among the opposing first and second surfaces of the semiconductor layer 30 , and the Schottky electrode 10 and the ohmic electrode 20 are arranged at intervals. Furthermore, the insulating substrate 60 is provided on the second surface of the semiconductor layer 30 . In the semiconductor device of the present invention satisfying the above formula (I), the initial carrier concentration of the semiconductor layer is small, and the extrinsic carriers function as the main factor of conduction. The well density of the semiconductor layer is small, which does not hinder the conduction of external carriers. Furthermore, in Patent Document 1, there is a relationship of the following formula, and there is a problem in the controllability of the carrier concentration based on the carrier concentration design guidelines of the conventional unipolar power device. [Number 7]
Figure 02_image015
(In the formula, n, ε, Ve , q and L are the same as formula (I)) The semiconductor element of the present invention has a small reverse leakage current and a low forward on-resistance, which can extract a large current. In addition, even if an inexpensive silicon substrate or a metal substrate is used as the conductive substrate, good rectification characteristics are exhibited. Furthermore, even if the oxide semiconductor layer is formed into a film with excellent productivity such as sputtering, good rectification characteristics are exhibited. The semiconductor device of the present invention is particularly excellent in vertical Schottky barrier diode applications. <Regarding formula (I)> Generally, the following formula (1) holds true in an insulator in which a carrier does not exist. J ins =(9/8)με(V 2 /L 3 ) (1) J ins : current density (A/cm 2 ) μ: mobility (cm 2 /V·s) ε : dielectric constant of the substance ( F/cm) V: applied voltage (V) L: thickness (cm) of the region through which the current flows. On the other hand, regarding the conductor in which a carrier exists, the following formula (2) holds. J ohm =qnμ(V/L) (2) J ohm : current density (A/cm 2 ) q: elementary charge (1.602×10 −19 C) n: carrier concentration (cm −3 ) μ : mobility ( cm 2 /V·s) V: applied voltage (V) L: thickness (cm) of the region through which the current flows. Under the condition of J ins =J ohm , the following formula (3) holds. [Number 8]
Figure 02_image017
(In the formula, n, ε, V, q and L are the same as the formulae (1) and (2)) Therefore, when the following formula (4) is established, it means that J ins > J ohm , and the insulating conduction Great effect. That is, it means that the exogenous carrier functions as a main factor of conduction. [Number 9]
Figure 02_image019
(In the formula, n, ε, V, q and L are the same as formulas (1) and (2)) For Schottky barrier diodes and junction field effect transistors (JFETs) whose rectification characteristics are expressed by unipolar . There is a drift region in a metal oxide semiconductor field effect transistor (MOSFET). Usually, in the drift region, the relationship of the above formula (2) is established. In this case, the applied voltage V means the voltage applied to the drift layer. In the above formula (I), V e is defined as the forward effective voltage, but it refers to the voltage, that is, when considering the actual device configuration, with respect to the applied voltage V, excluding the voltage for releasing energy. The effective voltage to the drift layer after the action of the built-in voltage V bi and so on with bending. In Schottky barrier diodes, junction field effect transistors (JFET), metal oxide semiconductor field effect transistors (MOSFET) and other devices, there is a pair of ohmic electrodes and Schottky between the semiconductor layer devices. As long as the above-mentioned formula (I) holds true for the electrode, the extrinsic carrier functions as the main factor of electrical conduction. The dielectric constant ε is the product of the relative dielectric constant ε r of the semiconductor and the dielectric constant ε 0 of the vacuum (8.854×10 −14 (8.854E-14) [F/cm]). ε r is a parameter that varies depending on the material, but is preferably 3 to 20, more preferably 5 to 16, and still more preferably 9 to 13. If the relative permittivity is too low, there is a possibility that the injection of extrinsic carriers is reduced, and high current cannot be obtained. If the relative permittivity is too large, the parasitic capacitance may increase or the current characteristic may be hysteresis. Regarding the forward effective voltage V e , if the actual forward characteristic is considered, the applied voltage to the unipolar device is usually about 0.5 V to 1.5 V, and the built-in voltage V bi is usually about 0.7 to 1.3 V. Consider Ve to be around 0.1 V. The value of the basic charge is 1.602×10 -19 C/unit, so if ε r is assumed to be 10, then in view of formula (I), the upper limit of the carrier concentration n is determined by one of the semiconductor layers to the ohmic electrode and the shovel. The interval L between the Teky electrodes is determined, as shown in Table 1. [Table 1] L(nm) n(cm -3 ) 10 5.47E+17 20 1.37E+17 50 2.19E+16 100 5.47E+15 200 1.37E+15 300 6.07E+14 500 2.19E+14 1000 5.47E+13 2000 1.37E+13 5000 2.19E+12 10000 5.47E+11 L is preferably 10 nm<L<100000 nm, more preferably 20 nm<L<10000 nm, more preferably 30 nm<L<1000 nm, and most preferably 50 nm<L<300 nm. If the inter-electrode interval L is too short, problems may arise from the viewpoint of withstand voltage, and if L is too large, the current value may decrease or the film thickness of the semiconductor layer in the vertical element may increase, resulting in a time-consuming film formation. L and n preferably satisfy the relationship represented by the following formula (Ia), more preferably satisfy the relationship represented by the following formula (Ib), and more preferably satisfy the relationship represented by the following formula (Ic), especially Preferably, the relationship represented by the following formula (Id) is satisfied. [Number 10]
Figure 02_image021
(In the formula, n, ε, V e , q and L are the same as in formula (I)) If n is too low, the well existing in the semiconductor layer will have an influence, the effect of the diffusion current will be increased, and the current characteristics will be deteriorated. Yu. On the other hand, when n is equal to or greater than εV e /qL 2 in the formula (I), the effect of the drift current becomes large, and the operation characteristics are approached to the previous ones, and it becomes difficult to produce the effect of the present invention. <Withstand Voltage of Semiconductor Element> The semiconductor element of the present invention has a pair of ohmic electrodes and a Schottky electrode between semiconductor layers. Compared with the conventional power device, the design carrier concentration is lower, so the design of the withstand voltage V BD becomes V BD ∼ E c L with respect to V BD ∼E c L/2, and it is expected to compare with the same L, Increase the withstand voltage by about 2 times. Here, E c is the maximum dielectric breakdown electric field, and L is the length between electrodes. In addition, in the previous power device, due to the high initial carrier concentration, the leakage current is large when reverse bias is applied. It is difficult to obtain an element structure in which the ohmic electrode surface is enclosed by a perpendicular line from the Schottky surface. In the present invention, the initial carrier concentration in the semiconductor layer is relatively low, and when a forward voltage is applied, the exogenous carriers are only injected into the ohmic electrode surface when a vertical line is drawn from the outer periphery of the Schottky electrode to the ohmic electrode surface. contained within the vertical line from the Schottky plane. On the other hand, when a reverse bias is applied, there are no carriers throughout the entire semiconductor layer, so the effect of leakage current due to wraparound is small. FIG. 5 is a view for explaining the electrode surface of the semiconductor element of FIG. 2 . In FIG. 5 , the outer peripheral portion of the Schottky electrode is the portion indicated by the reference numeral 12 , and the ohmic electrode surface is the portion indicated by the reference numeral 22 . A vertical line drawn from the outer peripheral portion 12 of the Schottky electrode to the ohmic electrode surface 22 is denoted by symbol A. In a vertical power device, usually, the lower part of the semiconductor layer is an ohmic electrode, but when the ohmic electrode is inside the vertical line drawn from the Schottky electrode, the Schottky electrode can be easily used for the lower part of the semiconductor layer. In addition, it is known that electric field relaxation structures such as guard rings are used in conventional power devices to reduce reverse leakage current. With such a configuration, these electric field relaxation structures, which are disadvantages of the process, can be omitted or reduced. In a unipolar power device dominated by extrinsic carriers, the withstand voltage is V BD to E c L as described above, so the dielectric breakdown can be easily determined from the measurement results of the inter-electrode length L and the withstand voltage V BD . electric field. Here, the withstand voltage per unit L corresponds to the dielectric breakdown electric field. If the withstand voltage per unit film thickness is higher, L can be reduced when designing the same withstand voltage element, so the injection of extrinsic carriers is increased, and a lower resistance element can be provided. The withstand voltage per unit L is preferably 0.5 MV/cm or more, more preferably 0.8 MV/cm or more, still more preferably 1.0 MV/cm or more, and particularly preferably 3.0 MV/cm or more. The withstand voltage of unit L can be obtained by measuring the breakdown voltage (V) and dividing by the length of L. For example, in the case of the Schottky barrier diode, in the case of sweeping the reverse voltage, the initial voltage value that has reached the current value of 1×10 −3 A is defined as the breakdown voltage. In addition, the withstand voltage of the unit L can be adjusted according to the selection of the material of the semiconductor layer. In the present invention, when the material of the semiconductor layer has a band gap of 1 eV or more and includes an amorphous or polycrystalline semiconductor layer, it can reach more than 0.5 MV/cm. When it is a material with a band gap of 2 eV or more, it can reach 1.0 MV/cm or more, and when it is a semiconductor layer with a band gap of 2 eV or more and includes an amorphous or polycrystalline semiconductor layer, it can reach 3.0 MV/cm or more. <Characteristic temperature> The characteristic temperature is a parameter that expresses the characteristics of the band tail energy level at the lower end of the conduction band unique to amorphous or polycrystalline crystals. Regarding the semiconductor that has the outer tail energy level at the lower end of the conduction band, the resulting carrier is dominated by the following: The characteristics of the following formula (5). [Number 11]
Figure 02_image023
J: current density (A/cm 2 ) u: mobility (cm 2 /V·s) N c : effective state density of semiconductor (cm -3 ) N t : band tail energy level density at the lower end of the conduction band (cm -3 ) ε: Dielectric constant of the substance (F/cm) V: Applied voltage (V) L: Thickness of the region through which the current flows (cm) e: Elementary charge (1.602×10 -19 C) I: Tc/ T Tc: Characteristic temperature (K) T: Actual temperature (K) Characteristic temperature Tc is a parameter where Tc>T, and the number of band tail energy orders is large, which hinders the conduction of externally induced carriers injected through the well , becomes the larger value. The current-voltage measurement is carried out, and it can be seen from equation (5) that the slope of the Log(J)-Log(V) curve is I+1. Therefore, I was obtained from the slope, and Tc was calculated. However, when the value of Tc becomes constant with respect to an applied voltage in a certain continuous range, it is an indicator that the semiconductor layer has a tail energy level. Preferably, Tc<1500K, more preferably Tc<900K, and still more preferably Tc<600K. If the value of Tc is large, the number of extrinsic carriers captured by the band tail energy level may increase, and the device characteristics may be increased in resistance. The characteristic temperature can be obtained from the slope of the Log(J)-Log(V) curve by performing current-voltage measurement. The characteristic temperature can be lowered by increasing the short-range order of the atomic structure in amorphous or polycrystalline semiconductors. For example, in the case of an amorphous metal oxide semiconductor, a film with a low density tends to have a low short-range order and a high characteristic temperature. In the amorphous metal oxide semiconductor film-formed by sputtering, it was confirmed that there is a relationship between the density and the film-forming conditions. The closer the target-substrate distance is, the lower the sputtering pressure, the higher the substrate temperature during film formation or the higher the annealing temperature after film formation, or the higher the applied voltage to the target during sputtering film formation, the easier it is to form High density film. Moreover, when 0.1-10 volume% of H 2 or H 2 O is added as a sputtering gas during sputtering film formation, a high-density film can be easily obtained. If the amorphous or polycrystalline semiconductor layer contains one or more elements selected from the group consisting of In, Zn, Ga, and Sn, the metal oxide semiconductor can utilize the s orbital, which has high objectivity, and is therefore less susceptible to disturbance by periodic potential. As a result, the characteristic temperature tends to decrease. <Layering of Drift Layers (Limited to Vertical Devices)> A semiconductor device (vertical) can be obtained which has a semiconductor layer ( L 1 , L 2 , ...L n ) (n L and L n represent the carrier concentration and film thickness of the layer with the lower carrier concentration at the nth when counting from the Schottky electrode to the ohmic electrode) and the carrier The semiconductor layer with higher concentration n h (d 1 , d 2 , ... d n-1 ) (n h and d n represent when counting from the Schottky electrode to the ohmic electrode, the nth carrier concentration is higher The carrier concentration and film thickness of the layer) are repeated on the drift layer. [Number 12]
Figure 02_image025
(In the formula, n L represents the carrier concentration of the layer with the lower carrier concentration of the nth number when counting from the Schottky electrode to the ohmic electrode, and ε represents the concentration of the nth semiconductor layer with the lower carrier concentration. Dielectric constant, V e represents the effective voltage applied to the nth semiconductor layer with lower carrier concentration (can be set to Ve = 0.1 V), q represents the basic charge, L n represents the nth carrier concentration The film thickness of the lower semiconductor layer) can be expected to increase in withstand voltage and decrease in resistance value by lamination compared to the drift structure of a single layer. In this case, L n is preferably 10 nm<L n <1000 nm, more preferably 20 nm<L n <300 nm, more preferably 30 nm<L n <200 nm, particularly preferably 30 nm< Ln &lt; 100 nm. If Ln is too short, the difference may be large, and if Ln is too long, the resistance value may be high. Further, dn is preferably 3 nm<d n <30 nm, more preferably 5 nm<d n < 10 nm. If dn is too long, there is a possibility that the depletion layer does not spread to the whole area from the Schottky electrode to the ohmic electrode when the reverse bias is applied, which may cause a problem in terms of withstand voltage. If dn is too short, there is a possibility that it does not function as a spacer layer between L n and L n + 1 and does not function as a laminate structure. n h is preferably the following formula (6-a), more preferably the following formula (6-b), and still more preferably the following formula (6-c). [Number 13]
Figure 02_image027
(In the formula, ε represents the dielectric constant of the nth semiconductor layer with higher carrier concentration, V e represents the effective voltage applied to the nth semiconductor layer with higher carrier concentration (can be set as V e = 0.1V), q represents the basic charge, dn represents the film thickness of the nth semiconductor layer with higher carrier concentration) If n h is too large, the semiconductor layer with higher carrier concentration will inhibit the application of reverse bias voltage. The extension of the depletion layer makes it difficult to maintain the withstand voltage. If n h is too small, extrinsic carriers need to be injected into the layer with higher carrier concentration during forward application. As a result, a plurality of semiconductor layers with lower carrier concentration work as one layer with lower carrier concentration There is a risk that the resistance value will increase. The layer in contact with the Schottky electrode is preferably a layer with a lower carrier concentration. <Series connection of semiconductor elements> In the previous withstand voltage design of unipolar power devices, when the rated withstand voltage is applied, the electric field strength of the semiconductor interface on the Schottky metal side reaches the vicinity of the dielectric breakdown field, and it is difficult to make semiconductor elements. the link. For example, in the case of a Schottky barrier diode, even if a plurality of components with a withstand voltage of 600 V are connected in series, it is difficult to obtain a withstand voltage of more than 600 V. In the semiconductor device (power device) with low initial carrier concentration of the present invention and using externally injected carriers, in the case of a plurality of serial connections, the withstand voltage is the product of the rated withstand voltage corresponding to the number of connections. and increase. Therefore, the required voltage-resistant components can be easily provided. <Constituent layer of semiconductor element> (1) Semiconductor layer The semiconductor layer is not particularly limited, but preferably contains polycrystalline or amorphous. Furthermore, it is preferable to contain a metal oxide semiconductor, and it is more preferable to contain a metal oxide semiconductor containing one or more elements selected from the group consisting of In, Zn, Ga, Sn, and Al. If it is amorphous, it is excellent in large-area uniformity, and is effective in reducing shock ionization and improving withstand voltage when reverse bias is applied. If it is polycrystalline, it will have better large area uniformity and better conduction characteristics. When producing a semiconductor layer from a metal oxide semiconductor, a film formation method using a sintered body sputtering target excellent in large area can be used. By using a metal oxide semiconductor containing one or more elements selected from In, Zn, Ga, Sn, and Al in the semiconductor layer, the conduction property of the s orbital of the metal element can be utilized, so even if it is amorphous, polycrystalline It also forms a semiconductor layer with overlapping tracks and excellent conduction characteristics. The metal oxide semiconductor may contain one kind or two or more kinds of metal oxides. Examples of the metal oxide include oxides of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, or Al, and the like. It is preferable to contain one or more elements selected from In, Zn, Ga, and Sn. The metal of the metal oxide semiconductor may essentially include one or more selected from In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. In addition, for example, 95 atomic % or more, 98 atomic % or more, or 99 atomic % or more of the metal may be one or more selected from In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, or Al . The metal oxide constituting the metal oxide semiconductor preferably has an atomic ratio satisfying the following formulae (A) to (C). With such a composition, high withstand voltage and low on-resistance can be achieved. 0≦x/(x+y+z)≦0.8 (A) 0≦y/(x+y+z)≦0.8 (B) 0≦z/(x+y+z)≦1.0 (C) (In the formula, x is selected from In, Sn, Ge and The atomic number of one or more elements in Ti, y represents the atomic number of one or more elements selected from Zn, Y, Sm, Ce and Nd, and z represents the atomic number of one or more elements selected from Ga and Al) If When x exceeds 0.8, when x is In or Sn, the insulating properties of metal oxides may be lowered, and there is a possibility that Schottky junctions may not be obtained easily, and when x is Ge or Ti, metal oxides may become difficult to obtain. The insulating property becomes high, which may cause heat generation due to ohmic loss. More preferably, the above-mentioned compositions (A) to (C) are represented by the following formulae (A-1) to (C-1), respectively. 0≦x/(x+y+z)≦0.7 (A-1) 0≦y/(x+y+z)≦0.8 (B-1) When z is Ga: 0.02≦z/(x+y+z)≦1.0 When z is Al: 0.005≦z /(x+y+z)≦0.5 (C-1) (in the formula, x, y and z are the same as the above formulae (A) to (C)) When z is Ga, if it is less than 0.02, there is oxygen in the metal oxide It is easy to separate, and there is a possibility of uneven electrical properties. More preferably, the above-mentioned compositions (A) to (C) are respectively the following formulae (A-2) to (C-2). 0.1≦x/(x＋y＋z)≦0.5 (A-2) 0.1≦y/(x＋y＋z)≦0.5 (B-2) 0.03≦z/(x＋y＋z)≦0.5 (C-2) (where x and y are the same as The above formulae (A) to (C) are the same, and z is Ga). Further, the above compositions (A) and (C) are preferably the following formulae (A-3) and (C-3), respectively. 0≦x/(x+y+z)≦0.25 (A-3) 0.3≦z/(x+y+z)≦1.0 (C-3) (where x, y, and z are the same as the above formulas (A) and (C)) The metal oxide of the metal oxide semiconductor layer may be amorphous or crystalline, and the crystal may be microcrystalline or single crystal. Preferably, the metal oxide is amorphous or microcrystalline. When the metal oxide is made into a single crystal, a method such as crystal growth from a seed crystal, MBE (molecular beam epitaxy) or PLD (pulse laser deposition) is used. If the crystal grows on the SiO 2 surface or the metal surface, crystal defects are likely to be generated, and when used as a device that is energized in the vertical direction, there is a possibility that the crystal defects may lead to defects. When the crystal grows on the SiO 2 surface or the metal surface, the heating temperature, time, etc. are appropriately adjusted so that the particle size does not become too large. On the other hand, in the case of an amorphous state, even if there are dangling bonds, since they do not exist as crystal defects, unevenness in electrical properties and large deterioration in properties can be alleviated. Furthermore, since the covalent bond between the metal oxide and the Si semiconductor is different, the ionic bond is strong, so the energy level formed by the dangling bond is close to the conductive band or the filled body. Therefore, the difference in electrical properties such as mobility due to the structure of the metal oxide is smaller than that of Si, SiC, or the like. If such properties of metal oxides are actively utilized, even single crystals can provide high-voltage and high-reliability high-current diodes or switching elements with high yields. Here, the term "amorphous" means that a cross section in the film thickness direction of the metal oxide layer is obtained, and when it is evaluated by an electron beam diffraction method such as a transmission electron microscope, no significant diffracted light can be obtained. Pointer. Preferably, the diffraction image is obtained from a wide area of about 10 nm from the irradiation area of the electron beam. The so-called obvious light spot refers to the diffraction spot with symmetry observed from the diffraction image. In addition, "amorphous" also includes the case of having a partially crystallized or microcrystallized part. When an electron beam is irradiated to a partially crystallized part, a diffraction image may be confirmed. The so-called "microcrystalline structure" means that the size of the crystal grain size is submicron or less, and there is no clear grain boundary. The so-called "polycrystalline" refers to the size of the crystal grain size exceeding the micron size, and the existence of clear grain boundaries. The carrier concentration of each layer constituting the metal oxide semiconductor layer is usually 1×10 11 to 1×10 18 cm −3 , for example, 1×10 13 to 1×10 18 cm −3 . The carrier concentration can be obtained, for example, by CV measurement. The properties required for diodes are high-speed switching, high withstand voltage, and low on-resistance. As long as a semiconductor device using metal oxide is used, these properties can be combined. The reason is that the band gap of the metal oxide is originally wide and has a high withstand voltage. In addition, since oxygen vacancies tend to be n-type, and p-type is not easily formed, this situation is also advantageous for high-speed switching. In order to reduce the on-resistance, it is sufficient to crystallize it to improve the mobility, but it is preferably limited to the extent that no grain boundary can be formed. Pores are often present in the grain boundaries, and when an electric field is formed, polarization is generated, and the withstand voltage performance may be reduced by the polarization. When the drop in withstand voltage is significant, it is preferable to use it in an amorphous form as it is. When it is used as an amorphous material, although it also depends on the kind of the element which forms a metal oxide layer, what is necessary is just to set a heat processing condition to 500 degrees C or less and within 1 hour, for example. A stable amorphous state can be obtained by heating at a low temperature of 500°C or lower. The film thickness of the semiconductor layer is not limited, but is usually 100 to 8000 nm. (2) Schottky Electrode The metal constituting the Schottky electrode is not particularly limited, preferably selected from Pd, Mo, Pt, Ir, Ru, Ni, W, Cr, Re, Te, Mn, Os, Fe, One or more metals (including alloys) of Rh and Co or oxides of the metals, more preferably one or more metals (including alloys) selected from Pd, Pt, Ir and Ru, or oxides of the metals. Moreover, it is preferable that it is a metal or a metal oxide which forms a good Schottky contact with the withstand voltage layer of the said oxide semiconductor layer. More preferably, in combination with an oxide semiconductor, Pd oxide, Pt oxide, Ir oxide, and Ru oxide that form higher Schottky barriers are used. These oxides usually form semiconductors or insulators by being oxidized, but can be formed by contacting oxide semiconductors to maintain a metal state with high carrier density by selecting the composition or film-forming conditions Good Schottky contact. In order for the oxide to form a good Schottky electrode, the carrier concentration of the Schottky electrode is preferably 10 18 cm -3 or more. If it is less than 10 18 cm -3 , the contact with the oxide semiconductor layer may become a pn junction, which may impair the advantages of Schottky diodes such as high-speed response. The carrier concentration can be obtained, for example, by Hall measurement or the like. Although it does not specifically limit as a manufacturing method for obtaining a metal oxide layer, It can use suitably for the method of performing reactive sputtering of this metal target in an oxygen-containing environment. The thickness of the Schottky electrode is usually 2 nm to 500 nm, preferably 5 nm to 200 nm. If it is too thin, the on-resistance during forward bias may increase due to the influence of the metal in contact. If it is too thick, the on-resistance at the time of forward bias is still increased due to its own resistance, the flatness of the Schottky interface may be deteriorated, and the withstand voltage may be lowered. Regarding the Schottky electrode, in order to reduce the contact resistance with the substrate or the current extraction electrode and improve the adhesion, it is possible to laminate a plurality of layers of metals or metal oxides with different compositions on the side opposite to the side in contact with the semiconductor layer. (3) Ohmic electrode The material of the ohmic electrode is not particularly limited as long as it can make good ohmic connection with the semiconductor layer, and it is preferably one selected from Ti, Mo, Ag, In, Al, W, Co and Ni The above metals (including alloys) or their compounds (oxides, etc.) are more preferably one or more metals (including alloys) selected from Mo, Ti, Au, Ag and Al or their compounds. In addition, the ohmic electrode may be constituted by a plurality of layers. For example, a Mo electrode layer is used on the side in contact with the semiconductor layer. In order to extract a large current, a metal layer such as Au or Al is deposited thickly. This layer can be used as the basis for wire bonding. The thickness of the ohmic electrode is usually 10 nm to 5 μm. (4) Film Formation Method The film formation method of each layer is not particularly limited, and the following methods can be used, namely, thermal CVD (chemical vapor deposition, chemical vapor deposition) method, CAT-CVD (catalytic chemical vapor deposition, catalytic chemical vapor deposition) method Deposition) method, optical CVD method, atomized CVD method, MO-CVD (Metal-organic Chemical Vapor Deposition) method, plasma CVD method and other CVD methods; MBE (Molecular Beam Epitaxy, molecular beam) Epitaxy), ALD (atomic layer deposition, atomic layer deposition) and other atomic-level control film production methods; ion plating, ion beam sputtering, magnetron sputtering and other PVD (Physical Vapor Deposition, Physical Vapor Deposition) Method; doctor blade method, injection method, extrusion method, hot pressing method, sol-gel method, aerosol deposition method and other previously known methods using ceramic steps; coating method, spin coating method, printing method, spray method , electroplating, plating, micellar electrolysis and other wet methods. In the case of selecting a metal oxide semiconductor, the film formation method of the semiconductor layer is preferably sputtering. The film-forming gas is preferably at least one selected from rare gases, oxygen, hydrogen, and water. The distance between the sputtering target and the substrate (TS interval) is preferably 10 mm to 200 mm. If the TS interval is too short, there is a possibility that the discharge cannot be performed. When the TS interval is too long, the film quality of the semiconductor becomes sparse, and there is a possibility that the film has a high characteristic temperature. (5) Substrate The substrate of the semiconductor element is not particularly limited, and known ones can be used. Examples of the substrate include conductive substrates, semiconductor substrates, insulating substrates, and the like. In the vertical semiconductor element, as shown in FIGS. 1 and 2 , a conductive substrate can be used. The conductive substrate may be arranged in contact with a Schottky electrode or an ohmic electrode. As the conductive substrate, a conventionally known substrate having excellent surface smoothness, such as a silicon single crystal substrate, a silicon polycrystalline substrate, and a silicon crystal substrate, can be used. In addition to the silicon substrate, a semiconductor substrate such as a SiC substrate, a GaN substrate, and a GaAs substrate may be used. A metal substrate having excellent conductivity, such as an Al substrate, a Cu substrate, and a Ni substrate, can also be used. In consideration of mass productivity and cost, a silicon substrate is preferred. The silicon substrate has n-type, i-type, and p-type depending on the presence or absence and type of doping. When a current flows in the vertical direction, it is preferably n-type or p-type with lower resistance. As the dopant, previously known B, P, Sb and the like can be used. Especially when the resistance is to be lowered, As or red phosphorus can also be used as a dopant. In the laterally mounted semiconductor element, as shown in FIG. 4 , an insulating substrate can be used. The insulating substrate can be arranged in contact with the semiconductor layer. The insulating substrate is not particularly limited as long as it has insulating properties, and a commonly used one can be arbitrarily selected within a range that does not lose the effect of the present invention. For example, in addition to quartz glass, barium borosilicate glass, aluminoborosilicate glass, aluminosilicate glass and other alkali-free glass substrates and ceramic substrates produced by the fusion method or the float method, other materials with high durability can be used. Plastic substrates, etc., subject to the heat resistance of the processing temperature in this production step. Moreover, a dielectric substrate can also be used as an insulating substrate. As a dielectric substrate, a lithium niobate substrate, a lithium tantalate substrate, a zinc oxide substrate, a crystal substrate, a sapphire substrate, etc. are mentioned. In addition, it can be used for a substrate having an insulating film or a dielectric film on the surface of a metal substrate such as a stainless steel alloy. In addition, an insulating film may be formed on the substrate as a base film. As the base film, a single layer or a stacked layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon oxynitride film can be formed using a CVD method, a sputtering method, or the like. The material of the semiconductor substrate is not particularly limited as long as the smoothness of the surface is maintained. Examples of semiconductor substrates include Si substrates, GaN substrates, SiC substrates, GaP substrates, GaAs substrates, ZnO substrates, Ga 2 O 3 substrates, GaSb substrates, and InP substrates whose carrier concentration is adjusted to 1×10 18 cm -3 or less. Substrate, InAs substrate, InSb substrate, ZnS substrate, ZnTe substrate, diamond substrate, etc. The semiconductor substrate may be single crystal or polycrystalline. Moreover, an amorphous substrate or an amorphous substrate may be partially contained. It can also be used on conductor substrates, semiconductor substrates, insulating substrates, and substrates having semiconductor films formed by methods such as CVD (chemical vapor deposition). As a substrate, it can also be used on the above-mentioned conductive substrate, semiconductor substrate, or insulating substrate, and has an arbitrary structure composed of a plurality of materials, a layered structure, a circuit, a wiring, an electrode, or the like. As the material of any structure, for example, a composite material of various metals or insulating materials, such as a metal for forming a back-end process on a large-scale integrated circuit (LSI), an interlayer insulating film, can be mentioned. The layer of the layer structure is not particularly limited, and an electrode layer, an insulating layer, a semiconductor layer, a dielectric layer, a protective film layer, a stress buffer layer, a light shielding layer, an electron/hole injection layer, and an electron/hole transport layer can be used. , light-emitting layer, electron/hole blocking layer, crystal growth layer, adhesion-improving layer, memory layer, liquid crystal layer, capacitor layer, storage layer and other well-known layers. The electrode layers generally include: Al layer, Si layer, Sc layer, Ti layer, V layer, Cr layer, Ni layer, Cu layer, Zn layer, Ga layer, Ge layer, Y layer, Zr layer, Nb layer, Mo layer, Tc layer, Ru layer, Rh layer, Pd layer, Ag layer, Cd layer, In layer, Sn layer, Sb layer, Te layer, Hf layer, Ta layer, W layer, Re layer, Os layer, Ir layer , Pt layer, Au layer, alloy layer containing more than one metal of these layers, and oxide electrode layer, etc. The carrier concentration of semiconductors such as oxide semiconductors or Si can also be increased for use in the electrode layer. Examples of the insulating layer usually include those selected from the group consisting of Al, Si, Sc, Ti, V, Cr, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag , Cd, In, Sn, Sb, Te, Hf, Ta, W, Re, Os, Ir, Pt and Au consisting of one or more metal oxide insulating films, nitride films, etc. The semiconductor layer is not limited to the crystal state of single crystal, polycrystalline, and amorphous, but widely includes Si layer, GaN layer, SiC layer, GaP layer, GaAs layer, GaSb layer, InP layer, InAs layer, InSb layer, ZnS layer layers, ZnTe layers, diamond layers, oxide semiconductor layers such as Ga 2 O 3 , ZnO, InGaZnO, etc., organic semiconductor layers such as fused pentacene, and the like. Examples of dielectric layers include: lithium niobate layer, lithium tantalate layer, zinc oxide layer, crystal substrate layer, sapphire layer, BaTiO 3 layer, Pb(Zr,Ti)O 3 (PZT) layer, (Pb,La )(Zr,Ti) O3 (PLZT) layer, Pb(Zr,Ti,Nb) O3 (PZTN) layer, Pb(Ni,Nb) O3 - PbTiO3 (PNN-PT) layer, Pb(Ni, Nb)O 3 -PbZnO 3 (PNN-PZ) layer, Pb(Mg,Nb)O 3 -PbTiO 3 (PMN-PT) layer, SrBi 2 Ta 2 O 9 (SBT) layer, (K,Na)TaO 3 layer, (K,Na)NbO 3 layer, BiFeO 3 layer, Bi(Nd,La)TiO x layer (x=2.5～3.0), HfSiO(N) layer, HfO 2 -Al 2 O 3 layer, La 2 O 3 layers, La 2 O 3 -Al 2 O 3 layers, etc. As a film of a protective film layer, irrespective of an inorganic substance or an organic substance, the film which is excellent in insulating property and the permeability|transmittance of water etc. is low can be mentioned. As a protective film layer, a SiO2 layer, a SiNx layer (x=1.20-1.33 ) , a SiON layer, an Al2O3 layer, etc. are mentioned, for example. As a stress buffer layer, an AlGaN layer etc. are mentioned. Examples of the light-shielding layer include a black matrix layer and a color filter layer including a metal, a metal-organic substance, or the like. As an electron/hole injection layer, an oxide semiconductor layer, an organic semiconductor layer, etc. are mentioned. As an electron/hole transport layer, an oxide semiconductor layer, an organic semiconductor layer, etc. are mentioned. As a light-emitting layer, an inorganic semiconductor layer, an organic semiconductor layer, etc. are mentioned. An oxide semiconductor layer etc. are mentioned as an electron/hole blocking layer. Examples of the base material include power generation devices, light emitting devices, sensors, power conversion devices, computing devices, protection devices, optoelectronic devices, displays, memories, semiconductor devices having a back-end process, power storage devices, and the like. The layer of the layer structure may be a single layer or a layer of two or more layers. The semiconductor element of the present invention can be used as a power semiconductor element, a (rectifier) diode element, a Schottky energy barrier diode element, an electrostatic discharge (ESD) protection diode, and a transient voltage protection (TVS) protection diode Bulk, Light Emitting Diode, Metal Semiconductor Field Effect Transistor (MESFET), Junction Field Effect Transistor (JFET), Metal Oxide Film Semiconductor Field Effect Transistor (MOSFET), Schottky Source/Drain MOSFET (Metal -Oxide-Semiconductor Field Effect Transistor, metal oxide semiconductor field effect transistor), avalanche multiplication photoelectric conversion element, solid-state imaging element, solar cell element, photo sensor element, display element, resistance change memory, etc. It is also particularly suitable for power applications due to the high current draw. Electronic circuits using this component can be applied to electrical machines, electronic machines, vehicles, powertrains, and the like. EXAMPLES Example 1 An n-type Si substrate (diameter 4 inches, thickness 250 μm) with a resistivity of 0.001 Ω·cm was mounted on a sputtering apparatus (manufactured by CANON ANELVA: E-200S), and the following multilayer electrodes were formed. However, the backside of the substrate is treated with Ti 100 nm/Au 50 nm in order to eliminate the contact resistance between the probe and the probe during measurement. First, Ti was formed into a film of 15 nm in the environment of DC (Direct Current) 50 W and Ar, and then Pd was formed into a film of 50 nm in the environment of DC 50 W and Ar. A film of 20 nm of PdO was formed in a mixed gas environment with O 2 . Next, the substrate was placed in a sputtering apparatus (manufactured by ULVAC: CS-200) together with the area mask for semiconductors, and InGaZnO (In:Ga:Zn (atomic ratio) = 1:1:1) of 200 nm was formed into a film, and then The oxide of this composition is hereinafter referred to as "InGaZnO (1:1:1)", and the other composite oxides are similarly described as the withstand voltage layer (semiconductor layer) except for the atomic ratio of oxygen. The film-forming conditions were set to: DC300 W, a mixed gas environment of Ar and H 2 O (H 2 O concentration: 1 vol %). The sputtering target-substrate distance (TS spacing) was set to 80 mm. The substrate was taken out and annealed in air at 300° C. for 1 hour using an electric furnace. This substrate was placed in a sputtering apparatus together with an electrode area mask (50 μm in diameter) again, and Mo was formed into a film of 150 nm as an ohmic electrode (50 μm in diameter). After that, an Al electrode of 2 μm was formed using the same mask. The film-forming conditions were all set to DC100 W and Ar environment. As a final treatment, aging treatment in the atmosphere at 200° C. for 1 hour was performed. Furthermore, the element structure is characterized in that, as shown in FIG. 1 , a Schottky electrode is provided under the semiconductor layer, and when a perpendicular line is drawn from the outer peripheral portion of the Schottky electrode to the ohmic electrode surface, the ohmic electrode surface is formed. on the inside of the above-mentioned vertical line. <Inter-electrode distance L> The inter-electrode distance L is obtained by the cross-sectional TEM (transmission electron microscope) image and the EDX (energy dispersive X-ray spectroscopy) image of the cross-sectional TEM. Assume that the layer containing InGaZnO is the semiconductor layer, the Schottky electrode is the PdO layer, the ohmic electrode is Mo, and the portion where the contrast of the TEM cross-sectional image is consistent with the layer containing InGaZnO based on EDX is the semiconductor layer and Defined as the inter-electrode distance L. In addition, the above-mentioned semiconductor layer was sandwiched between Pd and Mo by EDX, and the distance L between electrodes was 200 nm. Taking advantage of the fact that the semiconductor layer is depleted by reverse bias and functions as a resistance layer by forward bias, it is confirmed by CV (capacitance-voltage) measurement that the thickness that should function as a semiconductor is within the above-mentioned L. no problem. According to the minimum capacitance value C min when the reverse voltage is applied and the maximum capacitance value C max when the forward voltage is applied, use the relational expression of C/A=ε r ×ε 0 /d to obtain the film thickness corresponding to C min The difference of the film thickness d max corresponding to d min and C max converges to a value of L±50% relative to L, so it is verified that the distance L between electrodes is 200 nm. However, since the relative permittivity of InGaZnO (1:1:1) in the present film formation method was confirmed to be 16 by film thickness measurement, ε r =16 was used. The relative permittivity of InGaZnO is usually reported to be around 10 to 19. C: Capacitance value (F) A: Effective area of the electrode (cm 2 ) d: Film thickness that functions as a semiconductor (cm) ε r : Relative permittivity ε 0 : The permittivity of vacuum, 8.854E-14[ F/cm] Here, the effective area A of the electrode represents the area that is mutually enclosed with respect to the semiconductor layer in a pair of ohmic electrodes and Schottky electrodes that are separated from each other. Regarding this embodiment, the area of the ohmic electrode with a diameter of 50 μm can be regarded as A. Furthermore, in the CV measurement, a CMU (Capacitance Measure Unit) unit of the following B1505 was used, and the voltage was superimposed by the bias voltage T to perform the measurement. The measurement frequency was 1 kHz, and the AC amplitude was set to 0.03 V. <Identification of Electrode Type> After the identification of the above-mentioned semiconductor layer, the identification of the electrode type was carried out by considering the type of the electrode sandwiching the semiconductor layer material as an ohmic electrode and a Schottky electrode. From the cross-sectional EDX image, it is estimated that the metal or metal compound including Mo and Pd is an ohmic electrode or a Schottky electrode. From the confirmation of the rectification characteristics, it was determined that the Mo side was ohmic and the Pd side was the electrode type of Schottky. Furthermore, by depth-direction XPS (X-ray photoelectron spectroscopy, X-ray photoelectron spectroscopy), the element was subjected to Ar sputtering by the depth-direction method, and the XPS spectrum was confirmed. From the Mo side to the Mo/InGaZnO interface, the peak derived from oxygen in the Mo spectrum of XPS increases gently along with the oxygen concentration contained in InGaZnO, and more than 90% of the XPS spectrum looking at Mo on the Mo layer away from InGaZnO can be It belongs to pure Mo, so the ohmic electrode is set to Mo. On the other hand, at the InGaZnO/PdO interface, from the InGaZnO side to Pd, the peak derived from oxygen in the Pd spectrum of XPS does not gradually decrease with the oxygen concentration contained in InGaZnO, and a certain amount of oxygen contains in Pd. In addition, in the region where Pd was observed by the EDX image, the contrast of the TEM image was clearly seen, and in the depth direction XPS between the pure Pd region and the InGaZnO region, there was an electron density of less than 20 nm. Pure Pd in the Pd region. Thus, the Schottky electrode is a layer containing about 20 nm of Pd or PdO. As shown in Table 2-1, it is recorded as Pd(PdO). <Evaluation of crystallinity> The evaluation of crystallinity was performed by the electron beam diffraction method when the cross-sectional TEM of the semiconductor layer was observed. Diffraction images are obtained from the area irradiated by the electron beam with a diameter of 10 nm or more. At a plurality of points in the direction parallel to the film thickness direction and the cross section, the shape of the light spot could not be confirmed in the diffraction image, so the semiconductor layer was judged to be amorphous, that is, amorphous. <Electrical characteristics results> For the obtained elements, B1505 (HVSMU (High-voltage Source Measure Unit), HCSMU (Heavy-current Source Measure Unit), manufactured by KEYSIGHT TECHNOLOGIES, Inc. MFCMU (Multi-frequency Capacitance Measure Unit), MPSMU (Medium-power Source Measure Unit, equipped with), bias T (N1272A), circuit switcher (N1258A), and Cascade The high-voltage probe instrument EPS 150 TESLA manufactured by the company measures the characteristics of voltage (V)-current (J) and voltage (V)-capacitance (C). In addition, the following items were evaluated. The results are shown in Table 2-1. However, each of the above-mentioned SMUs or CMUs is arranged on the Schottky electrode side during measurement, and a bias voltage is applied. The ohmic electrode side is in a state where 0 V is applied. (1) Measurement of carrier concentration The carrier concentration was obtained using the above-mentioned apparatus and the above-mentioned CV measurement. Create a graph of A 2 /C 2 on the vertical axis and the applied voltage V on the horizontal axis, using the range between 0 V and 2 V as the starting point and the slope of the straight line with -2/(ε r ε 0 N depl ) Proportional to this, the carrier concentration of the semiconductor layer is obtained by setting the carrier concentration n=N depl . The carrier concentration was 1.0×10 14 cm -3 as shown in Table 2-1. In addition, it can be confirmed that the semiconductor is n-type from the behavior of the CV measurement. In addition, the CMU unit of the following B1505 was used for the CV measurement, and the voltage was superimposed by the bias voltage T to carry out the measurement. The measurement frequency was 1 kHz, and the AC amplitude was set to 0.03 V. It was confirmed that the present semiconductor element satisfies the following formula (I). In addition, according to the above, the dielectric constant was calculated from the relative dielectric constant 16 of InGaZnO, V e was set to 0.1 V, and L was set to 200 nm, thereby determining the magnitude relationship. [Number 14]
Figure 02_image029
(2) Measurement of characteristic temperature The characteristic temperature was obtained by the method described above. Using the HCSMU of the above-mentioned device, it is applied to 0 V to 3 V in a manner of applying a forward bias voltage to the element (the HCSMU applies a positive voltage). Take the difference between LogJ-LogV on the vertical axis (LogJ 1 -LogJ 2 )/(LogV 1 -LogV 2 ), which is the "power" of the JV characteristic, and take V on the horizontal axis. Here, J means current density (A/cm 2 ), and is a value obtained by dividing the measured current value (A) by the effective area of the electrode. J 1 , J 2 , V 1 , and V 2 are the current densities and applied voltage values at measurement points 1 and 2 . The average "power" in the range of 2 V to 3 V is 2.5, and the maximum and minimum value of the "power" in this interval is ±0.5 relative to the average value, so it is considered that the semiconductor layer can be used as a band tail at the lower end of the conductivity. The energy level of the semiconductor is applicable to the aforementioned formula (5). According to the formula (5) mentioned above, the "power" 2.5 is equal to I+1, I=Tc/T, and the actual temperature during the measurement is 300 K, so the characteristic temperature is 450 K. (3) Determination of withstand voltage As mentioned above, the withstand voltage can be obtained by measuring the breakdown voltage (V) and dividing it by the length of L. In the case of this Schottky barrier diode, in the case of sweeping the reverse voltage, the initial voltage value reaching the current value of 1×10 −3 A is defined as the breakdown voltage. Using the HVSMU, the breakdown voltage is defined as -62 V since the current value is 1 × 10 -3 A at -62 V when the voltage is applied in the reverse direction. The withstand voltage of unit L is the absolute value obtained by dividing by 200 nm, which is 3.1 MV/cm. (4) Determination of the forward on-resistance Ron@2 V As mentioned above, the HCSMU of the above device is used to apply a forward bias voltage to the element (the HCSMU applies a positive voltage) to 0 V to 2 V. Measure the current density J 2V when 2 V is applied, and define it as forward on-resistance Ron@2 V=2[V]/J 2 V [A/cm 2 ] for calculation. (5) Determination of leakage current value @-5 V Using HVSMU, the current density when a voltage of -5 V is applied in the reverse direction is obtained. Since it is -5.0×10 -8 A/cm 2 , the absolute value is taken, and the leakage current value @-5 V is determined to be 5.0×10 -8 A/cm 2 . Examples 2 to 5, 9, and 18 to 19 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Tables 2-1 and 2-2. The results are shown in Tables 2-1 and 2-2. In addition, the semiconductor elements of these embodiments satisfy the formula (I). Example 6 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 2-1. The results are shown in Table 2-1. In addition, the semiconductor element of this embodiment satisfies the formula (I). In this example, the ohmic electrode of Example 1 was changed from Mo to Ti. When L was evaluated, it was confirmed that the contrast ratio of the TEM image including InGaZnO was shorter than 200 nm by the oxygen abstraction of the Ti electrode, and the thickness of the semiconductor layer was 180 nm. Example 7 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 2-1. The results are shown in Table 2-1. In addition, the semiconductor element of this embodiment satisfies the formula (I). In the embodiment, during the sputtering of Pd in the production of the Schottky electrode, the sputtering was not performed with a mixed gas of Ar and O 2 , and only Ar was used to form a film of 70 nm from beginning to end. As a result, at the InGaZnO/PdO interface from the InGaZnO side to Pd, the oxygen-derived peak in the Pd spectrum of XPS decreases gently along with the oxygen concentration contained in InGaZnO, and it cannot be concluded that oxygen is contained in Pd. In addition, in the region where Pd was observed by the EDX image, there was clearly no region where the contrast of the TEM image could be seen. From this, it is determined that the Schottky electrode is a layer containing Pd with a thickness of about 70 nm. It is recorded as Pd as shown in Table 2-1. Example 8 An n-type Si substrate (diameter 4 inches, thickness 250 μm) with a resistivity of 0.001 Ω·cm was mounted on a sputtering apparatus (manufactured by CANON ANELVA: E-200S), and the following laminated electrodes were formed as ohmic electrode layers . However, for the reverse side of the substrate, Ti100 nm/Au50 nm treatment is performed in order to eliminate the contact resistance between the probe and the probe during measurement. First, a film of 15 nm of Ti was formed in a DC50 W, Ar environment, secondly, a film of 50 nm of Ni was formed in a DC50 W, Ar environment, and finally, as a Schottky electrode, a film of 20 nm was formed in a DC50 W, Ar environment Mo of nm. Next, this substrate was placed in a sputtering apparatus (manufactured by ULVAC: CS-200) together with the area mask for semiconductors, and InGaZnO (1:1:1) of 200 nm was formed as a withstand voltage layer (semiconductor layer). The film-forming conditions were set to: DC300 W, a mixed gas environment of Ar and H 2 O (H 2 O concentration: 1 vol %). The sputtering target-substrate distance (TS spacing) was set to 80 mm. The substrate was taken out and annealed in air at 300° C. for 1 hour using an electric furnace. After placing the substrate and the electrode area mask (50 μm in diameter) in the sputtering apparatus again, the Pd target was placed in a mixed gas of argon and oxygen to form a film of 50 nm of PdO as a Schottky electrode ( 50 μm in diameter). After that, a Pd electrode with a thickness of 100 μm was formed using the same mask. The film-forming conditions were all set to DC100 W and Ar environment. As a final treatment, aging treatment in the atmosphere at 200° C. for 1 hour was performed. Furthermore, the element structure is characterized in that, as shown in FIG. 2 , an ohmic electrode is provided below the semiconductor layer, and when a perpendicular line is drawn from the outer peripheral portion of the Schottky electrode to the ohmic electrode surface, the ohmic electrode surface is located above. Inside the vertical line. The obtained semiconductor element was evaluated in the same manner as in Example 1. The results are shown in Table 2-1. In addition, the semiconductor element of this embodiment satisfies the formula (I). Example 10 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 2-1. The results are shown in Table 2-1. In addition, the semiconductor element of this embodiment satisfies the formula (I). In this example, the annealing temperature after the formation of the semiconductor layer was increased to 500°C, and as a result, it was found that the diffraction image in the cross-sectional TEM measurement changed. The diffracted light spot is wide but exists, and the position of the light spot changes with respect to the measurement position of the plurality of spots. From this, it is judged that the present semiconductor film is polycrystalline. In addition, it was observed that the thickness of the semiconductor layer changed to 190 nm along with the crystallization. Example 11 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 2-2. The results are shown in Table 2-2. In addition, the semiconductor element of this embodiment satisfies the formula (I). In this embodiment, Ru is used for the Schottky electrode. The composition of Si/Ti/Ru/RuO/InGaZnO/Mo is formed. RuO is formed by sputtering using a mixed gas of Ar and oxygen. Example 12 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 2-2. The results are shown in Table 2-2. In addition, the semiconductor element of this embodiment satisfies the formula (I). In this embodiment, Ni is used for the Schottky electrode. The composition of Si/Ti/Ni/NiO/InGaZnO/Mo is formed. NiO is formed by sputtering using a mixed gas of Ar and oxygen. Example 13 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 2-2. The results are shown in Table 2-2. In addition, the semiconductor element of this embodiment satisfies the formula (I). In this example, the semiconductor layer was sputtered using an InSnZnO (1:1:1) target. Example 14 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 2-2. The results are shown in Table 2-2. In addition, the semiconductor element of this embodiment satisfies the formula (I). The semiconductor layer was sputtered using a Ga2O3 target. Since it is an insulating sputtering target, the film formation conditions of 300 W of RF (Radio Freqency, radio frequency) are used instead of DC300 W. Example 15 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 2-2. The results are shown in Table 2-2. In addition, the semiconductor element of this embodiment satisfies the formula (I). In this example, the environment in which the semiconductor layer was formed was set to 100% by volume of Ar, and the temperature of the semiconductor annealing was set to 150° C. in the band. The semiconductor layer was sputtered using a Ga2O3 target. Since it is an insulating sputtering target, the film formation conditions of RF300 W are used instead of DC300 W. Example 16 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 2-2. The results are shown in Table 2-2. In addition, the semiconductor element of this embodiment satisfies the formula (I). In this example, the semiconductor layer was sputtered using an InAlO (93:7) target. It was found that the diffraction image of the obtained cross-sectional TEM measurement changed. The diffracted light spot is wide but exists, and the position of the light spot changes with respect to the measurement site of the plural spots. However, even if a diffraction image was taken in the film thickness direction, no change in the position of the light spot was observed. From this, it is judged that the present semiconductor film is polycrystalline (columnar). Example 17 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 2-2. The results are shown in Table 2-2. In addition, the semiconductor element of this embodiment satisfies the formula (I). In this example, the semiconductor layer was sputtered using an InGaO (1:1) target. In addition, in order to obtain crystallinity, the annealing temperature was increased to 600°C. Along with this, as in Example 8, as shown in FIG. 2 , the PdO Schottky electrode was placed on the upper part of the semiconductor layer. The purpose of this is to reduce the reduction of Schottky barrier properties by reducing PdO to Pd at high temperature. It was found that the diffraction image of the obtained cross-sectional TEM measurement changed. The diffracted light spot is wide but exists, and the position of the light spot changes with respect to the measurement site of the plural spots. However, even if a diffraction image was taken in the film thickness direction, no change in the position of the light spot was observed. From this, it is judged that the present semiconductor film is polycrystalline (columnar). Example 20 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 2-2. The results are shown in Table 2-2. In this embodiment, as shown in FIG. 3, a Schottky electrode is provided on the upper part of the semiconductor layer, and when a vertical line is drawn from the outer periphery of the Schottky electrode to the surface of the ohmic electrode, the ohmic The electrode surface is outside the above-mentioned vertical line. Although the formula (I) was satisfied, compared with Example 8, a decrease in withstand voltage and an increase in leakage current were observed. [table 2-1] Example 1 2 3 4 5 6 7 8 9 10 Components semiconductor layer Semiconductor material InGaZnO (1:1:1) InGaZnO (1:1:1) InGaZnO (1:1:1) InGaZnO (1:1:1) InGaZnO (1:1:1) InGaZnO (1:1:1) InGaZnO (1:1:1) InGaZnO (1:1:1) InGaZnO (1:1:1) InGaZnO (1:1:1) Introducing gas during film formation Ar: 99% H 2 O: 1% Ar: 90% H 2 O: 10% Ar: 89% H 2 O: 1% O 2 : 10% Ar: 90% O 2 : 10% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% crystallinity Amorphous Amorphous Amorphous Amorphous Amorphous Amorphous Amorphous Amorphous Amorphous Polycrystalline TS interval (mm) 80 80 80 80 150 80 80 80 80 80 Annealing temperature (℃) 300 300 300 300 300 300 300 300 400 500 Distance between electrodes L (nm) 200 200 200 200 200 180 200 200 200 190 Ohmic electrode Mo Mo Mo Mo Mo Ti Mo Mo Mo Mo Schottky electrode Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd Pd (PdO) Pd (PdO) Pd (PdO) Components figure 1 figure 1 figure 1 figure 1 figure 1 figure 1 figure 1 figure 2 figure 1 figure 1 Evaluation results Carrier concentration n(cm -3 ) 1.0×10 14 5.0×10 14 5.0×10 13 1.0×10 15 6.0×10 14 1.0×10 15 1.0×10 14 1.0×10 1 4 3.0×10 14 2.0×10 15 Characteristic temperature (K) 450 550 350 800 700 450 450 500 400 870 Withstand voltage (MV/cm) 3.1 2.1 3.5 1.5 2.3 2.5 0.8 1.8 2.7 1.3 Forward conduction resistance Ron(Ωcm 2 )@2 V 4.0×10 4 8.0× 10-4 3.0× 10-4 3.0× 10-3 1.0× 10-3 2.5× 10-4 3.0× 10-4 5.0× 10-4 3.2× 10-4 1.2× 10-3 Leakage current value (A)@-5 V 5.0× 10-8 1.0× 10-7 1.0× 10-8 5.0× 10-7 2.0× 10-7 9.0×10 8 1.0× 10-4 1.0× 10-6 3.0×10 7 5.0×10 4 Relative permittivity ε r 16 16 16 16 16 16 16 16 16 15 εV e /qL 2 (cm -3 ) 2.2×10 15 2.2×10 15 2.2×10 15 2.2×10 15 2.2×10 15 2.7×10 15 2.2×10 15 2.2×10 15 2.2×10 15 2.3×10 15 [Table 2-2] Example 11 12 13 14 15 16 17 18 19 20 Components semiconductor layer Semiconductor material InGaZnO (1:1:1) InGaZnO (1:1:1) InSnZnO (1:1:1) Ga 2 O 3 Ga 2 O 3 InAlO (93:7) InGaO (1:1) InGaZnO (1:1:1) InGaZnO (1:1:1) InGaZnO (1:1:1) Introducing gas during film formation Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% Ar: 100% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% crystallinity Amorphous Amorphous Amorphous Amorphous Amorphous polycrystalline (columnar) polycrystalline (columnar) Amorphous Amorphous Amorphous TS interval (mm) 80 80 80 80 80 80 80 80 80 80 Annealing temperature (℃) 300 300 300 300 150 300 600 300 300 300 Distance between electrodes L (nm) 200 200 200 200 200 200 200 100 500 200 Ohmic electrode Mo Mo Mo Mo Mo Mo In Mo Mo Mo Schottky electrode Ru (RuO) Ni (NiO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Pd (PdO) Components figure 1 figure 1 figure 1 figure 1 figure 1 figure 1 figure 2 figure 1 figure 1 image 3 Evaluation results Carrier concentration n(cm -3 ) 2.0×10 14 3.0×10 14 8.0×10 13 2.0×10 11 3.0×10 14 8.0×10 14 2.0×10 12 1.0×10 14 3.0×10 1 4 1.0×10 14 Characteristic temperature (K) 480 500 380 580 850 330 410 400 500 450 Withstand voltage (MV/cm) 2.4 2.1 2.4 3.9 2.2 1.9 1.3 3.3 2.9 0.9 Forward conduction resistance Ron(Ωcm 2 )@2 V 4.5× 10-4 5.0× 10-4 2.0× 10-4 9.0×10 3 3.0× 10-3 8.0× 10-5 2.0× 10-4 4.0× 10-5 9.0× 10-3 5.0× 10-4 Leakage current value (A)@-5 V 5.0× 10-6 5.0× 10-5 8.0× 10-8 1.0× 10-9 4.0× 10-9 7.0× 10-7 1.5× 10-6 1.0× 10-7 1.0× 10-8 5.0× 10-5 Relative permittivity ε r 16 16 12 14 14 11 12 16 16 16 εV e /qL 2 (cm -3 ) 2.2×10 15 2.2×10 15 1.7×10 15 1.9×10 15 1.9×10 15 1.5×10 15 1.7×10 15 8.8×10 15 3.5×10 14 2.2×10 15 Comparative Example 1 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film-forming conditions were changed as shown in Table 3. The results are disclosed in 3. In this example, the environment during the film formation of InGaZnO was set to 100% by volume of Ar. In addition, annealing after semiconductor film formation was not performed. As a result, the carrier concentration falls outside the range of the formula (I). In addition, the withstand voltage is also 0.1 MV/cm, which makes it difficult to adapt to power applications. The leakage current was 100 mA higher than the compliance current value of the measuring device when -5 V was applied. and cannot be measured. Therefore, in Table 3, it was recorded as >1.0×10 −3 A. Comparative Example 2 A semiconductor element was produced and evaluated in the same manner as in Example 1, except that the film-forming conditions were changed as shown in Table 3. The results are shown in Table 3. In this embodiment, the film formation of the Pd/PdO layer is omitted, and the Schottky electrode becomes Ti. As a result, although the rectification characteristics were observed, the carrier concentration was outside the range of the formula (I). In addition, the leakage current is high, and the withstand voltage reaches 0.3 MV/cm, making it difficult to adapt to power applications. Comparative Example 3 A semiconductor element was produced and evaluated in the same manner as in Example 1 except that the film-forming conditions were changed as shown in Table 3. The results are shown in Table 3. In this example, the semiconductor layer was sputtered using an In 2 O 3 target. It was found that the diffraction image of the obtained cross-sectional TEM measurement changed. The diffracted light spot is wide but exists, and the position of the light spot changes with respect to the measurement site of the plural spots. However, even if a diffraction image was taken in the film thickness direction, no change in the position of the light spot was observed. From this, it is judged that the present semiconductor film is polycrystalline (columnar). Regarding the electrical characteristics, the carrier concentration was high, and the rectification ratio of the fabricated Schottky diode was not obtained, and the carrier concentration measurement by CV measurement was not possible. In addition, since the "power" of the positive direction is also continuously maintained at a value of 2 or less in the range of 2 to 3 V, it is judged that the relationship of the formula (5) does not hold, and it is considered that the characteristic temperature cannot be evaluated. A decrease in withstand voltage and an increase in leakage current were observed. [table 3] Comparative example 1 2 3 Components semiconductor layer Semiconductor material InGaZnO (1:1:1) InGaZnO (1:1:1) In 2 O 3 Introducing gas during film formation Ar: 100% Ar: 99% H 2 O: 1% Ar: 99% H 2 O: 1% crystallinity Amorphous Amorphous polycrystalline (columnar) TS interval (mm) 80 80 80 Annealing temperature (℃) none 300 300 Distance between electrodes L (nm) 200 200 200 Ohmic electrode Mo Mo Mo Schottky electrode Pd (PdO) Ti Pd (PdO) Components figure 1 figure 1 figure 1 Evaluation results Carrier concentration n(cm -3 ) 2.0×10 17 6.0×10 15 - Characteristic temperature (K) 1300 700 - Withstand voltage (MV/cm) 0.1 0.3 0.1 Forward conduction resistance Ron(Ωcm 2 )@2 V 6.0× 10-5 7.0× 10-4 5.0× 10-5 Leakage current value (A)@-5 V >1.0×10 3 8.0× 10-4 >1.0×10 -3 Relative permittivity ε r 16 16 10 εV e /qL 2 (cm -3 ) 2.2×10 15 2.2×10 15 1.4×10 15 [Industrial Applicability] The semiconductor device of the present invention can be used for Schottky barrier diodes and junction field effect transistors. Furthermore, these can be used for electronic circuits, and can be utilized for various electric apparatuses. Several embodiments and/or embodiments of the present invention have been described in detail above, and those exemplary embodiments and/or embodiments may be readily exemplified by those skilled in the art without materially departing from the novel teachings and effects of the present invention. or Examples apply various modifications. Accordingly, such various modifications are included within the scope of the present invention. The entire contents of the description of the Japanese application that will be the basis of the Paris priority in this case are hereby incorporated by reference.

1:半導體元件 2:半導體元件 3:半導體元件 4:半導體元件 10:肖特基電極 12:肖特基電極之外周部 20:歐姆電極 22:歐姆電極面 30:半導體層 40:導電性基板 50:絕緣層 60:絕緣性基板 A:垂線1: Semiconductor components 2: Semiconductor components 3: Semiconductor components 4: Semiconductor components 10: Schottky electrodes 12: The outer periphery of the Schottky electrode 20: Ohmic electrode 22: Ohmic electrode surface 30: Semiconductor layer 40: Conductive substrate 50: Insulation layer 60: Insulating substrate A: vertical line

圖1係本發明之一實施形態之半導體元件之概略剖視圖。 圖2係本發明之其他實施形態之半導體元件之概略剖視圖。 圖3係本發明之其他實施形態之半導體元件之概略立體圖。 圖4係本發明之其他實施形態之半導體元件之概略立體圖。 圖5係用於說明圖2之半導體元件之電極面之圖。FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. 3 is a schematic perspective view of a semiconductor device according to another embodiment of the present invention. 4 is a schematic perspective view of a semiconductor device according to another embodiment of the present invention. FIG. 5 is a view for explaining the electrode surface of the semiconductor element of FIG. 2 .

1:半導體元件 1: Semiconductor components

10:肖特基電極 10: Schottky electrodes

20:歐姆電極 20: Ohmic electrode

30:半導體層 30: Semiconductor layer

40:導電性基板 40: Conductive substrate

Claims (15)

一種半導體元件，其特徵在於： 具有隔開之一對歐姆電極及肖特基電極、以及 與上述歐姆電極及上述肖特基電極相接之半導體層，且 滿足下述式(I)： [數16]
Figure 03_image031
(式中，n為上述半導體層之載子濃度(cm-3 )，ε為上述半導體層之介電常數(F/cm)，Ve 為上述歐姆電極與上述肖特基電極之間之正向有效電壓(V)，q為基本電荷(C)，L為上述歐姆電極與上述肖特基電極之間之距離(cm))， 上述肖特基電極包含選自Pd、Mo、Pt、Ir、Ru、W、Cr、Re、Te、Mn、Os、Fe、Rh、Co及Ni中之一種以上金屬之氧化物。A semiconductor element, characterized in that it has a pair of ohmic electrodes and Schottky electrodes separated from one another, and a semiconductor layer in contact with the ohmic electrodes and the Schottky electrodes, and satisfies the following formula (I): 16]
Figure 03_image031
(wherein, n is the carrier concentration (cm -3 ) of the above-mentioned semiconductor layer, ε is the dielectric constant (F/cm) of the above-mentioned semiconductor layer, and V e is the positive value between the above-mentioned ohmic electrode and the above-mentioned Schottky electrode to the effective voltage (V), q is the basic charge (C), L is the distance (cm) between the above-mentioned ohmic electrode and the above-mentioned Schottky electrode), and the above-mentioned Schottky electrode comprises a group selected from Pd, Mo, Pt, Ir , Ru, W, Cr, Re, Te, Mn, Os, Fe, Rh, Co and Ni oxides of one or more metals. 如請求項1之半導體元件，其中上述半導體層包含金屬氧化物。The semiconductor element of claim 1, wherein the semiconductor layer contains a metal oxide. 如請求項2之半導體元件，其中上述半導體層之金屬氧化物含有選自In、Zn、Ga、Sn及Al中之一種以上之元素。The semiconductor element of claim 2, wherein the metal oxide of the semiconductor layer contains one or more elements selected from the group consisting of In, Zn, Ga, Sn, and Al. 如請求項1或2之半導體元件，其中上述歐姆電極包含選自Ti、Mo、Ag、In、Al、W、Co及Ni中之一種以上之金屬或其化合物。The semiconductor element according to claim 1 or 2, wherein the ohmic electrode comprises one or more metals selected from the group consisting of Ti, Mo, Ag, In, Al, W, Co, and Ni, or a compound thereof. 如請求項1或2之半導體元件，其中上述半導體層包含非晶或多晶。The semiconductor element according to claim 1 or 2, wherein the above-mentioned semiconductor layer comprises amorphous or polycrystalline. 如請求項1或2之半導體元件，其中上述半導體層之特性溫度為1500 K以下。The semiconductor element according to claim 1 or 2, wherein the characteristic temperature of the semiconductor layer is 1500 K or lower. 如請求項1或2之半導體元件，其中於自肖特基電極之外周部向歐姆電極面劃垂線時，上述歐姆電極面處於上述垂線之內側。The semiconductor device of claim 1 or 2, wherein when a vertical line is drawn from the outer peripheral portion of the Schottky electrode to the ohmic electrode surface, the ohmic electrode surface is located inside the vertical line. 如請求項1或2之半導體元件，其耐壓為0.5 MV/cm以上。The semiconductor element of claim 1 or 2 has a withstand voltage of 0.5 MV/cm or more. 如請求項1或2之半導體元件，其中上述半導體層介於上述歐姆電極與上述肖特基電極之間。The semiconductor element of claim 1 or 2, wherein the semiconductor layer is interposed between the ohmic electrode and the Schottky electrode. 如請求項9之半導體元件，其進而具有導電性矽基板，且 上述歐姆電極或上述肖特基電極與上述導電性矽基板相接。The semiconductor element according to claim 9, which further has a conductive silicon substrate, and The ohmic electrode or the Schottky electrode is in contact with the conductive silicon substrate. 如請求項1或2之半導體元件，其中上述歐姆電極與上述肖特基電極隔開間隔地存在於上述半導體層之一表面上。The semiconductor element according to claim 1 or 2, wherein the above-mentioned ohmic electrode and the above-mentioned Schottky electrode are present on a surface of the above-mentioned semiconductor layer with a space therebetween. 一種肖特基能障二極體，其特徵在於：使用如請求項1至11中任一項之半導體元件。A Schottky barrier diode is characterized by using the semiconductor element according to any one of claims 1 to 11. 一種接面場效電晶體，其特徵在於：使用如請求項1至11中任一項之半導體元件。A junction field effect transistor, characterized by using the semiconductor element according to any one of claims 1 to 11. 一種電子電路，其特徵在於：使用如請求項1至11中任一項之半導體元件、如請求項12之肖特基能障二極體或如請求項13之接面場效電晶體。An electronic circuit characterized by using the semiconductor element as claimed in any one of claims 1 to 11, the Schottky barrier diode as claimed in claim 12, or the junction field effect transistor as claimed in claim 13. 一種電氣機器、電子機器、車輛或動力機構，其特徵在於：使用如請求項14之電子電路。An electrical machine, electronic machine, vehicle or powertrain characterized by using the electronic circuit as claimed in claim 14.
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