TW201730809A - 指紋辨識模組及其製造方法 - Google Patents

指紋辨識模組及其製造方法 Download PDF

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TW201730809A
TW201730809A TW105139910A TW105139910A TW201730809A TW 201730809 A TW201730809 A TW 201730809A TW 105139910 A TW105139910 A TW 105139910A TW 105139910 A TW105139910 A TW 105139910A TW 201730809 A TW201730809 A TW 201730809A
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fingerprint
sensing
substrate
cover
circuit board
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TW105139910A
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張清暉
吳東穎
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致伸科技股份有限公司
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2218/00—Aspects of pattern recognition specially adapted for signal processing
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Abstract

本發明提供一種指紋辨識模組，包括：一基板；一指紋感測晶粒，貼附於該電路板上，用以感測一指紋影像；一蓋板膠層，形成於該指紋感測晶粒之一上表面；一蓋板，貼附於該蓋板膠層；以及一模封層，形成於該基板上。該模封層將該電路板上之該指紋感測晶粒，該膠層及該蓋板封裝一起並顯露出該蓋板。本案指紋辨識模組具有薄型化及提昇感測正確性的功效。

Description

指紋辨識模組及其製造方法
本發明係關於一種生物辨識元件，尤其係關於指紋辨識模組。
一般應用於電子產品的指紋辨識裝置主要用以讀取指紋影像，並於確認所讀取的指紋影像與預存的指紋相符時對電子產品進行解鎖操作。早期的指紋辨識裝置多用於門禁系統。近年來，隨著智慧型手機技術的發展，在手機設置指紋辨識裝置的趨勢已經形成。相較於應於門禁系統的指紋辨識裝置，設置於手機的指紋辨識裝置必須因應手機的薄型化而降低指紋辨識裝置的厚度。此外，如何提昇指紋辨識裝置感測指紋影像的正確性也是本技術領域人士所努力的項目。
請參照圖1所示之習知指紋辨識模組之示意圖。圖1的指紋辨識模組10包括一指紋感測晶粒11，一硬式電路板12，一軟性電路板13，一模封層(mold compound)14，一蓋板16以及增加軟性電路板之平整度之一 加強板17。指紋感測晶粒11藉由膠層12A貼附於硬式電路板12上，並使用導線W連接晶粒11與硬式電路板12。硬式電路板12與軟式電路板13由焊錫層13A貼合在一起。軟式電路板13與加強板17則由膠層17A黏合在一起。蓋板16則藉由膠層15黏貼於模封層14上。
當一手指放置於蓋板16時，指紋感測晶粒11，例如電容式指紋感測晶粒，感測手指的指紋影像，並將指紋影像藉由硬式電路板12以及軟式電路板13傳輸至電子裝置進行辨識。對本技術領域之人士而言，圖1的指紋辨識模組10仍具有需改善的項目。首先，在使用感測晶粒感測指紋的情況中，例如電容式指紋感測晶片，指紋感測晶粒11的感測表面與手指之間的距離越短，對於感測的正確性就越高。然而，於圖1的指紋辨識模組10中，手指與晶粒11表面之間的距離包括了晶粒11上表面的模封層的厚度D2與膠層15及蓋板16的厚度總合D1。這是因為在習知指紋辨識模組10的製程中，需要先對晶粒11及導線W進行模封製程以形成模封層14，接著再於模封層14上表面塗佈貼合蓋板16用的膠層15。在形成模封層14時，不可避免地在晶粒11上表面存在有一定厚度的模封層的厚度D2。此厚度則增加了晶粒11感測指紋的距離。
圖1指紋辨識模組1的另一需要改善的項目在於模封層14厚度不均勻的問題。在形成模封層14的過程中，時常無法精確地控制封裝結構的應力，造成模封層14厚度不均勻，而於模封層14的表面14S形成翹折(warpage)，導致形成於模封層14的表面的膠層15的厚度也不均勻，呈現兩邊厚中間薄的或兩邊薄中間厚的狀態。此厚度不均勻的情況將使得晶粒11感測電容值的基準不一致而導致誤判的結果。
本發明之目的在於提供一種具有較小厚度及提昇感測正確性之指紋辨識模組及其製造方法。
於一較佳實施例中，本發明提供一種指紋辨識模組，包括：一基板，具有複數電性接點；一指紋感測晶粒，貼附於該電路板上，用以感測一指紋影像，其中該感測晶粒與該基板上之該複數電性接點經由複數導線連接一起而使該指紋感測晶粒與該基板形成電性接觸；一蓋板膠層，形成於該指紋感測晶粒之一上表面；一蓋板，貼附於該蓋板膠層；以及一模封層，形成於該基板上，其中該模封層將該電路板上之該指紋感測晶粒，該膠層及該蓋板封裝一起並顯露出該蓋板。於又一較佳實施例中，本發明提供一種指紋辨識模組之製造方法，包括以下步驟：(a)將複數指紋感測晶粒黏著於一基板上，其中，該基板上於每一該指紋感測晶粒之周圍具有複數導電接點；(b)對該複數指紋感測晶粒與該基板進行打線連接，而使每一該指紋感測晶粒與該基板形成電性連接；(c)形成一膠層於該複數指紋感測晶粒之上表面；(d)放置一蓋板於該膠層上；(e)對該複數指紋感測晶粒進行封塑處理而使每一該指紋感測晶粒及該膠層被一模封層包覆；以及，(f)執行一切割步驟而形成複數個別之指紋感測晶粒單元；(g)將該複數個別之指紋感測晶粒單元附著於一軟性電路板上；以及(h)切割該軟性電路板而形成複數個別之指紋辨識模組。
10、20、30、40‧‧‧指紋辨識模組
11、21、31、41‧‧‧指紋感測晶粒
12、22、42‧‧‧基板
13、32、46‧‧‧軟性電路板
14、24、34、45‧‧‧模封層
15、23、33、43‧‧‧蓋板膠層
16、25、35、44‧‧‧蓋板
17、27、36‧‧‧金屬板
12A、13A、17A、22A、27A 32A、36A‧‧‧膠層
26A‧‧‧導電層
21S、31S、41S‧‧‧感測區
40A‧‧‧指紋感測晶粒單元
W‧‧‧導線
P‧‧‧電性接點
圖1係習知指紋辨識模組之結構示意圖。
圖2係本案指紋辨識模組之第一較佳實施例結構示意圖。
圖3係本案指紋辨識模組之第二較佳實施例結構示意圖。
圖4係本發明製造指紋辨識模組之製造方法之一較佳實施例示意圖。
圖5係本發明製造指紋辨識模組之製造方法之另一較佳實施例示意圖。
以下參照圖式說明本發明指紋辨識模組之結構及其製造方法之相關實施例。請參照圖2，其為本發明指紋辨識模組之第一較佳實施例示意圖。如圖2所示，本發明指紋辨識模組20包括一指紋感測晶粒(die)21，一基板22，蓋板膠層23，模封層(molding compound)24，一蓋板25，一軟性電路板26。此外，圖2實施例還包括一金屬片27。指紋感測晶粒21藉由黏膠層22A貼附於基板22。蓋板25藉由蓋板膠層23而貼附於模封層24。基板22藉由導電層26A貼附於軟性電路板26。例如，使用表面黏著技術(Surface-mount technology，SMT)，藉由焊錫使基板22與軟性電路板26貼附一起並形成電性連接，金屬片27則藉由黏膠層27A貼附於軟性電路板26。於本實施例中，基板22係硬式電路板。於基板22上指紋感測晶粒21之周圍具有複數電性接點P。藉由導線W連接指紋感測晶粒21與電性接點P而形成紋辨識晶粒20與基板22之間的電性連接。此外，指紋感 測晶粒21具有一感測區21S。蓋板膠層23形成於指紋感測晶粒21的感測區21S上且不與導線W接觸。
於圖1實施例中，指紋感測晶粒21可為，例如，電容式指紋感測器，但本發明並不以此為限。基板22及軟性電路板26則用以將指紋感測晶粒21感測到的指紋影像的像素傳導至指紋辨識模組外部。模封層24將指紋感測晶粒21，導線W，複數電性接點P以及蓋板膠層23密封一起，以隔絕模組外的塵埃。蓋板25提供手指與辨識模組的接觸介面並保護辨識模組的表面不致因為手指的多次接觸而被損壞。藉由將手指放置於蓋板25，指紋感測晶粒20可感測手指的指紋影像。蓋板25可以是，例如玻璃蓋板或陶瓷蓋板。貼附於軟性電路板26之金屬片27係用以加強軟性電路板10的平整度，以避免導線W及複數電性接點P之間產生空焊的情況。當然，於某些情況中也可選擇不使用金屬片27。
依據圖2顯示之本發明指紋辨識模組20的結構，本案指紋辨識模組20的蓋板膠層23與指紋感測晶粒21被模封層24封裝在一起。此結構可免除圖1所示之晶粒11上表面的模封層的厚度D2，因此指紋感測晶粒21的表面至蓋板25的厚度L比厚度(D1+D2)小。亦即，指紋感測晶粒21的表面至蓋板25的距離比圖1指紋辨識模組10之距離小，而有助於提昇指紋感測晶粒21的感測靈敏度。同時，指紋辨識模組20的整體厚度被降低亦有助於指紋辨識模組20的薄型化。
請參照圖3，其為本發明指紋辨識模組之第二實施例示意圖。圖3之指紋辨識模組30包括一指紋感測晶粒31，一軟性電路板32，蓋板膠層33，模封層34，一蓋板35，以及一金屬片36。於軟性電路板32上指紋感測晶粒30之周圍具有複數電性接點P。圖3亦顯示出連接指紋感 測晶粒31與電性接點P之導線W。此外，指紋感測晶粒31具有一感測區31S。指紋感測晶粒31藉由膠層32A而貼附於軟性電路板32。金屬片36則藉由膠層36A而貼附於軟性電路板32底部。圖3實施例於圖2實施例之差異在於，圖3實施例中的電性接點P直接形成於軟性電路板31上，故圖3實施例不需硬式電路板。此結構可進一步降低指紋辨識模組的厚度。
以下參照圖4A-4B說明本案指紋辨識模組之製造方法。為簡要說明之故，圖4A-4B僅顯示蓋板膠層43，而未顯示出其它膠層及導電層。如圖4A所示，複數指紋感測晶粒41(於本例中顯示2個)被貼附於同一基板42上。於本例中，基板42為硬式電路板。接著對每一指紋感測晶粒41進行打線連接步驟，使指紋感測晶粒41藉由導線W與基板42的電性接點P形成電性連接。在打線步驟後，分別於每一指紋感測晶粒41表面之感測區41S形成蓋板膠層43。之後貼附一蓋板44於蓋板膠層43。貼附蓋板44之後將進行一封塑(molding)步驟，使用模塑料將指紋感測晶粒41、蓋板膠層43及蓋板44被模封層45封裝在一起，並顯露出蓋板44的上表面，如圖4B所示。之後進行一切割步驟，將同一基板上的複數指紋感測晶粒41分離而形成個別的指紋感測晶粒單元40A，如圖4C所示。接著，使用，例如，表面黏著技術之製程將複數指紋感測晶粒單元40A貼附於同一軟性電路板46上。以及，對軟性電路板46進行切割，而形成複數指紋辨識模組40，如圖4E所示。
於本發明另一實施例中，亦可使用軟性電路板46做為基板，而省略硬式電路板42的使用。如圖5A所示，複數指紋感測晶粒41(於本例中顯示2個)被貼附於同一軟性電路板46上。接著對每一指紋感測晶粒41進行打線連接步驟，使指紋感測晶粒41藉由導線W與軟性電路板46的電性接點P形成電性連接。在打線步驟後，分別於每一指紋感測晶粒41表 面之感測區41S形成蓋板膠層43並貼附蓋板44。之後進行圖5B之步驟。由於圖5B步驟與圖4B相同，故不再重覆描述。接著進行一切割步驟，將同一軟性電路板46上的複數指紋感測晶粒41分離而形成個別的指紋感測模組50，如圖5C所示。
於本發明的製造方法中，蓋板膠層43及蓋板44於同一步驟中被封塑一起。於此製程中，當模封層45產生翹折現象時，蓋板44會產生相同的翹折形變，使得指紋感測晶粒41的感測區表面至蓋板44的距離保持一致，避免了因翹折形變所導致的誤判。
以上所述僅為本發明之較佳實施例，並非用以限定本發明之申請專利範圍，因此凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾，均應包含於本案之申請專利範圍內。
20‧‧‧指紋辨識模組
21‧‧‧指紋感測晶粒
22‧‧‧基板
23‧‧‧蓋板膠層
24‧‧‧模封層
25‧‧‧蓋板
26‧‧‧軟性電路板
27‧‧‧金屬片
22A、27A‧‧‧膠層
26A‧‧‧導電層
21S‧‧‧感測區
W‧‧‧導線
P‧‧‧電性接點
L‧‧‧厚度

Claims (10)

  1. 一種指紋辨識模組，包括：一基板，具有複數電性接點；一指紋感測晶粒，貼附於該電路板上，用以感測一指紋影像，其中該感測晶粒與該基板上之該複數電性接點經由複數導線連接一起而使該指紋感測晶粒與該基板形成電性接觸；一蓋板膠層，形成於該指紋感測晶粒之一上表面；一蓋板，貼附於該蓋板膠層；以及一模封層，形成於該基板上，其中該模封層將該電路板上之該指紋感測晶粒，該膠層及該蓋板封裝一起並顯露出該蓋板。
  2. 如申請專利範圍第1項之指紋辨識模組，其中該指紋感測晶粒之該上表面具有一感測區，其中該蓋板膠層係形成於該感測區且不與該導線接觸。
  3. 如申請專利範圍第1項之指紋辨識模組，其中該基板係一軟性電路板。
  4. 如申請專利範圍第1項之指紋辨識模組，其中該基板係一硬式電路板，且該指紋辨識模組更包括一軟性電路板貼附於該基板。
  5. 如申請專利範圍第1項之指紋辨識模組，其中該蓋板係一陶瓷蓋板或一玻璃蓋板。
  6. 一種指紋辨識模組之製造方法，包括以下步驟：(a)將複數指紋感測晶粒黏著於一基板上，其中，該基板上於每一該指紋感測晶粒之周圍具有複數導電接點； (b)對該複數指紋感測晶粒與該基板進行打線連接，而使每一該指紋感測晶粒與該基板形成電性連接；(c)形成一膠層於該複數指紋感測晶粒之上表面；(d)放置一蓋板於該膠層上；(e)對該複數指紋感測晶粒進行封塑處理而使每一該指紋感測晶粒及該膠層被一模封層包覆；以及，(f)執行一切割步驟而形成複數個別之指紋感測晶粒單元；(g)將該複數個別之指紋感測晶粒單元附著於一軟性電路板上；以及(h)切割該軟性電路板而形成複數個別之指紋辨識模組。
  7. 如申請專利範圍第6項之指紋辨識模組之製造方法，其中每一該指紋感測晶粒之該上表面具有一感測區，其中該蓋板膠層係分別形成於該感測區且不與該導線接觸。
  8. 如申請專利範圍第6項之指紋辨識模組之製造方法，其中該基板係一硬式電路板。
  9. 一種指紋辨識模組之製造方法，包括以下步驟：(a)將複數指紋感測晶粒黏著於一軟性電路板上，其中，該軟性電路板上於每一該指紋感測晶粒之周圍具有複數導電接點；(b)對該複數指紋感測晶粒與該軟性電路板進行打線連接，而使每一該指紋感測晶粒與該基板形成電性連接；(c)形成一膠層於該複數指紋感測晶粒之上表面；(d)放置一蓋板於該膠層上；(e)對該複數指紋感測晶粒進行封塑處理而使每一該指紋感測晶粒及 該膠層被一模封層包覆；以及，(f)執行一切割步驟而形成複數個別之指紋辨識模組。
  10. 如申請專利範圍第9項之指紋辨識模組之製造方法，其中每一該指紋感測晶粒之該上表面具有一感測區，其中該蓋板膠層係分別形成於該感測區且不與該導線接觸。
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